Index: llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td
@@ -166,6 +166,6 @@
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
+          (RLDICL (i64 (COPY (TABORTWCI 0, (LI 0), 0))), 36, 28)>;
 
 } // [HasHTM]
Index: llvm/trunk/test/CodeGen/PowerPC/htm.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/htm.ll
+++ llvm/trunk/test/CodeGen/PowerPC/htm.ll
@@ -57,16 +57,19 @@
   %0 = tail call i32 @llvm.ppc.tendall()
   %1 = tail call i32 @llvm.ppc.tresume()
   %2 = tail call i32 @llvm.ppc.tsuspend()
+  %3 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test4
 ; CHECK: tend. 1
 ; CHECK: tsr.  1
 ; CHECK: tsr.  0
+; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
 declare i32 @llvm.ppc.tendall()
 declare i32 @llvm.ppc.tresume()
 declare i32 @llvm.ppc.tsuspend()
+declare i64 @llvm.ppc.ttest()
 
 
 define void @test5(i64 %v) {