Index: lib/Target/AVR/AVRISelLowering.cpp
===================================================================
--- lib/Target/AVR/AVRISelLowering.cpp
+++ lib/Target/AVR/AVRISelLowering.cpp
@@ -1190,6 +1190,7 @@
   Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
 
   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
+  SmallVector<SDValue, 8> MemOpChains;
 
   // First, walk the register assignments, inserting copies.
   unsigned AI, AE;
@@ -1249,13 +1250,20 @@
           DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
           DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
 
-      Chain =
-          DAG.getStore(Chain, DL, Arg, PtrOff,
-                       MachinePointerInfo::getStack(MF, VA.getLocMemOffset()),
-                       0);
+      MemOpChains.push_back(DAG.getStore(
+          Chain, DL, Arg, PtrOff,
+          MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), 0));
     }
   }
 
+  // Transform all store nodes into one single node because all store
+  // nodes are independent of each other.
+  if (!MemOpChains.empty()) {
+    // Reverse the order in MemOpChains to match the push order.
+    std::reverse(MemOpChains.begin(), MemOpChains.end());
+    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
+  }
+
   // Build a sequence of copy-to-reg nodes chained together with token chain and
   // flag operands which copy the outgoing args into registers.  The InFlag in
   // necessary since all emited instructions must be stuck together.
Index: test/CodeGen/AVR/call.ll
===================================================================
--- test/CodeGen/AVR/call.ll
+++ test/CodeGen/AVR/call.ll
@@ -52,11 +52,11 @@
 
 define i16 @calli16_stack() {
 ; CHECK-LABEL: calli16_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 9
+; CHECK: ldi [[REG1:r[0-9]+]], 10
 ; CHECK: ldi [[REG2:r[0-9]+]], 2 
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
-; CHECK: ldi [[REG1:r[0-9]+]], 10
+; CHECK: ldi [[REG1:r[0-9]+]], 9
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
@@ -82,14 +82,14 @@
 
 define i32 @calli32_stack() {
 ; CHECK-LABEL: calli32_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 64
-; CHECK: ldi [[REG2:r[0-9]+]], 66
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 15
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 64
+; CHECK: ldi [[REG2:r[0-9]+]], 66
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: call foo32_2
     %result1 = call i32 @foo32_2(i32 1, i32 2, i32 3, i32 4, i32 34554432)
     ret i32 %result1
@@ -113,14 +113,14 @@
 define i64 @calli64_stack() {
 ; CHECK-LABEL: calli64_stack:
 
-; CHECK: ldi [[REG1:r[0-9]+]], 76
-; CHECK: ldi [[REG2:r[0-9]+]], 73
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 31
 ; CHECK: ldi [[REG2:r[0-9]+]], 242
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 76
+; CHECK: ldi [[REG2:r[0-9]+]], 73
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 155
 ; CHECK: ldi [[REG2:r[0-9]+]], 88
 ; CHECK: push [[REG2]]
Index: test/CodeGen/AVR/varargs.ll
===================================================================
--- test/CodeGen/AVR/varargs.ll
+++ test/CodeGen/AVR/varargs.ll
@@ -40,14 +40,14 @@
 declare void @var1223(i16, ...)
 define void @varargcall() {
 ; CHECK-LABEL: varargcall:
-; CHECK: ldi [[REG1:r[0-9]+]], 189
-; CHECK: ldi [[REG2:r[0-9]+]], 205
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 191
 ; CHECK: ldi [[REG2:r[0-9]+]], 223
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 189
+; CHECK: ldi [[REG2:r[0-9]+]], 205
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 205
 ; CHECK: ldi [[REG2:r[0-9]+]], 171
 ; CHECK: push [[REG2]]