Index: test/Transforms/InstCombine/icmp-signbit-shift-and.ll
===================================================================
--- /dev/null
+++ test/Transforms/InstCombine/icmp-signbit-shift-and.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+
+; FIXME: expect (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0
+define i1 @signbit-lshr-and(i32 %x, i32 %y) {
+; CHECK-LABEL: @signbit-lshr-and(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[LSHR]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %lshr = lshr i32 -2147483648, %y
+  %and = and i32 %lshr, %x
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+; FIXME: expect (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0
+define i1 @signbit-shl-and(i32 %x, i32 %y) {
+; CHECK-LABEL: @signbit-shl-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 -2147483648, %y
+  %and = and i32 %shl, %x
+  %r = icmp eq i32 %and, 0
+  ret i1 %r
+}
+