Index: lib/Target/AMDGPU/AMDGPUMCInstLower.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -112,10 +112,10 @@ const MCConstantExpr *One = MCConstantExpr::create(4, Ctx); SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx); - if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD) + if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD) return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx); - assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD); + assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD); return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx); } Index: lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.h +++ lib/Target/AMDGPU/SIInstrInfo.h @@ -157,7 +157,10 @@ MO_REL32 = 4, MO_REL32_LO = 4, // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI. - MO_REL32_HI = 5 + MO_REL32_HI = 5, + + MO_LONG_BRANCH_FORWARD = 6, + MO_LONG_BRANCH_BACKWARD = 7 }; explicit SIInstrInfo(const GCNSubtarget &ST); @@ -1030,12 +1033,6 @@ const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21); const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23); - // For MachineOperands. - enum TargetFlags { - TF_LONG_BRANCH_FORWARD = 1 << 0, - TF_LONG_BRANCH_BACKWARD = 1 << 1 - }; - } // end namespace AMDGPU namespace SI { Index: lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.cpp +++ lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1532,7 +1532,7 @@ BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub0) .addReg(PCReg, 0, AMDGPU::sub0) - .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_FORWARD); + .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD); BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub1) .addReg(PCReg, 0, AMDGPU::sub1) @@ -1542,7 +1542,7 @@ BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub0) .addReg(PCReg, 0, AMDGPU::sub0) - .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_BACKWARD); + .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD); BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32)) .addReg(PCReg, RegState::Define, AMDGPU::sub1) .addReg(PCReg, 0, AMDGPU::sub1)