Index: compiler-rt/lib/builtins/clear_cache.c
===================================================================
--- compiler-rt/lib/builtins/clear_cache.c
+++ compiler-rt/lib/builtins/clear_cache.c
@@ -87,6 +87,11 @@
 // It is expected to invalidate the instruction cache for the
 // specified range.
 
+// PR41575: The implicit clobber of r7 here doesn't play nicely with inlining.
+// Until we determine a better way to fix that, this shouldn't be inlined.
+#if defined(__arm__) && defined(__linux__)
+NOINLINE
+#endif
 void __clear_cache(void *start, void *end) {
 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
 // Intel processors have a unified instruction and data cache