Index: lib/Transforms/InstCombine/InstCombineCompares.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineCompares.cpp +++ lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1781,6 +1781,29 @@ } } + // (V0 & (signbit l>> V1)) ==/!= 0 -> (V0 << V1) >=/< 0 + // (V0 & (signbit << V1)) ==/!= 0 -> (V0 l>> V1) >=/< 0 + Value *V0, *V1, *Shift, *Zero; + ICmpInst::Predicate Pred; + if (match(&Cmp, + m_ICmp(Pred, + m_OneUse(m_c_And( + m_CombineAnd( + m_CombineAnd(m_Shift(m_SignMask(), m_Value(V1)), + m_Value(Shift)), + m_CombineOr(m_Shl(m_Value(), m_Value()), + m_LShr(m_Value(), m_Value()))), + m_OneUse(m_Value(V0)))), + m_CombineAnd(m_Zero(), m_Value(Zero)))) && + Cmp.isEquality(Pred)) { + Value *NewShift = cast(Shift)->getOpcode() == Instruction::LShr + ? Builder.CreateShl(V0, V1) + : Builder.CreateLShr(V0, V1); + ICmpInst::Predicate NewPred = + Pred == CmpInst::ICMP_EQ ? CmpInst::ICMP_SGE : CmpInst::ICMP_SLT; + return new ICmpInst(NewPred, NewShift, Zero); + } + return nullptr; } Index: test/Transforms/InstCombine/icmp-signbit-shift-and.ll =================================================================== --- test/Transforms/InstCombine/icmp-signbit-shift-and.ll +++ test/Transforms/InstCombine/icmp-signbit-shift-and.ll @@ -1,13 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt %s -instcombine -S | FileCheck %s +; Checking: +; (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0 +; (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0 -; FIXME: expect (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0 define i1 @signbit-lshr-and(i32 %x, i32 %y) { ; CHECK-LABEL: @signbit-lshr-and( -; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 -2147483648, [[Y:%.*]] -; CHECK-NEXT: [[AND:%.*]] = and i32 [[LSHR]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i32 -2147483648, %y @@ -16,17 +17,118 @@ ret i1 %r } -; FIXME: expect (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0 define i1 @signbit-shl-and(i32 %x, i32 %y) { ; CHECK-LABEL: @signbit-shl-and( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %shl = shl i32 -2147483648, %y + %and = and i32 %shl, %x + %r = icmp eq i32 %and, 0 + ret i1 %r +} + +define <2 x i1> @signbit-lshr-and-vec(<2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @signbit-lshr-and-vec( +; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %lshr = lshr <2 x i32> , %y + %and = and <2 x i32> %lshr, %x + %r = icmp ne <2 x i32> %and, + ret <2 x i1> %r +} + +; FIXME: Pattern match m_SignMask() match vectors with undefined elements. +define <3 x i1> @signbit-lshr-and-vec-undef1(<3 x i32> %x, <3 x i32> %y) { +; CHECK-LABEL: @signbit-lshr-and-vec-undef1( +; CHECK-NEXT: [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt <3 x i32> [[TMP1]], zeroinitializer +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %lshr = lshr <3 x i32> , %y + %and = and <3 x i32> %lshr, %x + %r = icmp ne <3 x i32> %and, + ret <3 x i1> %r +} + +define <3 x i1> @signbit-lshr-and-vec-undef2(<3 x i32> %x, <3 x i32> %y) { +; CHECK-LABEL: @signbit-lshr-and-vec-undef2( +; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[LSHR]], [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i32> [[AND]], +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %lshr = lshr <3 x i32> , %y + %and = and <3 x i32> %lshr, %x + %r = icmp ne <3 x i32> %and, + ret <3 x i1> %r +} + +define <3 x i1> @signbit-lshr-and-vec-undef3(<3 x i32> %x, <3 x i32> %y) { +; CHECK-LABEL: @signbit-lshr-and-vec-undef3( +; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[LSHR]], [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i32> [[AND]], +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %lshr = lshr <3 x i32> , %y + %and = and <3 x i32> %lshr, %x + %r = icmp ne <3 x i32> %and, + ret <3 x i1> %r +} + +define i1 @signbit-shl-and-extra-use-shl(i32 %x, i32 %y, i32 %z, i32* %p) { +; CHECK-LABEL: @signbit-shl-and-extra-use-shl( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]] +; CHECK-NEXT: store i32 [[XOR]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], [[Y]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1 +; CHECK-NEXT: ret i1 [[R]] +; + %shl = shl i32 -2147483648, %y + %xor = xor i32 %shl, %z ; extra use of shl + store i32 %xor, i32* %p + %and = and i32 %shl, %x + %r = icmp eq i32 %and, 0 + ret i1 %r +} + +define i1 @signbit-shl-and-extra-use-and(i32 %x, i32 %y, i32 %z, i32* %p) { +; CHECK-LABEL: @signbit-shl-and-extra-use-and( ; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] +; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AND]], [[Z:%.*]] +; CHECK-NEXT: store i32 [[MUL]], i32* [[P:%.*]], align 4 ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i32 -2147483648, %y %and = and i32 %shl, %x + %mul = mul i32 %and, %z ; extra use of and + store i32 %mul, i32* %p %r = icmp eq i32 %and, 0 ret i1 %r } +define i1 @signbit-shl-and-extra-use-shl-and(i32 %x, i32 %y, i32 %z, i32* %p) { +; CHECK-LABEL: @signbit-shl-and-extra-use-shl-and( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]] +; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[AND]], [[Z:%.*]] +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[XOR]] +; CHECK-NEXT: store i32 [[ADD]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %shl = shl i32 -2147483648, %y + %and = and i32 %shl, %x + %xor = xor i32 %and, %z ; extra use of and + %add = add i32 %shl, %xor ; extra use of shl + store i32 %add, i32* %p + %r = icmp eq i32 %and, 0 + ret i1 %r +}