Index: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -743,7 +743,8 @@
   // of the MachineBasicBlock so that they are named in the order that we sorted
   // them alphabetically. Eventually we wont need SkipVRegs because we will use
   // named vregs instead.
-  NVC.SkipVRegs();
+  if (IdempotentInstCount)
+    NVC.SkipVRegs();
 
   auto MII = MBB->begin();
   for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
Index: llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
@@ -1,4 +1,5 @@
 # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
 
 # Previously getReservedRegs was called before parsing
 # machineFunctionInfo, but the AMDGPU implementation depends on