Index: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9206,6 +9206,9 @@
   if (!Subtarget->hasNEON())
     return SDValue();
 
+  if (!N->getValueType(0).isSimple())
+    return SDValue();
+
   SDValue Op = N->getOperand(0);
   if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
       Op.getOpcode() != ISD::FMUL)
Index: llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll
+++ llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: convert_v3f32
+; CHECK: strb
+; CHECK: strh
+define void @convert_v3f32() {
+entry:
+  br label %bb
+
+bb:
+  %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02>
+  %2 = fptoui <3 x float> %1 to <3 x i8>
+  %3 = bitcast i8* undef to <3 x i8>*
+  store <3 x i8> %2, <3 x i8>* %3, align 1
+  ret void
+}