diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -3931,3 +3931,99 @@ : mve_vldr_vstr_sc2_addr<0b0, 0b1, (ins mve_addr_q_shift<3>:$addr), "vstrd", "64", 3>; } // let mayStore = 1 + +def VPSELt1 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary, + "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> { + bits<4> Qn; + bits<4> Qd; + bits<4> Qm; + + let Inst{28} = 0b1; + let Inst{25-23} = 0b100; + let Inst{22} = Qd{3}; + let Inst{21-20} = 0b11; + let Inst{19-17} = Qn{2-0}; + let Inst{16} = 0b1; + let Inst{15-13} = Qd{2-0}; + let Inst{12-9} = 0b0111; + let Inst{8} = 0b1; + let Inst{7} = Qn{3}; + let Inst{6} = 0b0; + let Inst{5} = Qm{3}; + let Inst{4} = 0b0; + let Inst{3-1} = Qm{2-0}; + let Inst{0} = 0b1; +} + +foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32", "f16", + "f32"] in { + def : MVEInstAlias; +} + +def VPNOTt1 : MVE_p<(outs ), (ins ), NoItinerary, + "vpnot", "", "", vpred_n, "", []> { + let Inst{31-0} = 0b11111110001100010000111101001101; + let Unpredictable{19-17} = 0b111; + let Unpredictable{12} = 0b1; + let Unpredictable{7} = 0b1; + let Unpredictable{5} = 0b1; + let Defs = [P0]; + let Uses = [P0]; + + let Constraints = ""; +} + +class loloop_start_tp size> + : t2LOL { + bits<4> Rn; + bits<11> label; + let Predicates = [HasMVEInt]; + let Inst{22} = 0b0; + let Inst{21-20} = size; + let Inst{19-16} = Rn{3-0}; + let Inst{13} = opc1; + let Inst{12} = 0b0; + let Inst{11} = !if(opc1, 0b0, label{0}); + let Inst{10-1} = !if(opc1, 0b0000000000, label{10-1}); + let Unpredictable{9-1} = !if(opc1, 0b111111111, 0b000000000); +} + +multiclass loloop_start_tp_size { + def TP8 : loloop_start_tp; + def TP16 : loloop_start_tp; + def TP32 : loloop_start_tp; + def TP64 : loloop_start_tp; +} + +defm MVE_WLS + : loloop_start_tp_size<(outs GPRlr:$LR), (ins rGPR:$Rn, wlslabel_u11:$label), + "wlstp", "$LR, $Rn, $label", 0b0>; +defm MVE_DLS + : loloop_start_tp_size<(outs GPRlr:$LR), (ins rGPR:$Rn), + "dlstp", "$LR, $Rn", 0b1>; + +class loloop_end_tp + : t2LOL { + bits<11> label; + let Predicates = [HasMVEInt]; + let Inst{22-16} = !if(opc1, 0b0001111, 0b0011111); + let Unpredictable{21-20} = !if(opc1, 0b11, 0b00); + let Inst{13} = opc1; + let Inst{12} = 0b0; + let Inst{11} = !if(opc1, 0b0, label{0}); + let Inst{10-1} = !if(opc1, 0b0000000000, label{10-1}); + let Unpredictable{10-1} = !if(opc1, 0b1111111111, 0b0000000000); +} + +def MVE_LEUpdateTP : loloop_end_tp<(outs GPRlr:$LRout), + (ins GPRlr:$LRin, lelabel_u11:$label), + "letp", "$LRin, $label", 0b0>; + +def MVE_LCTP : loloop_end_tp<(outs ), (ins pred:$p), "lctp${p}", "", 0b1> { + let Unpredictable{20-21} = 0b11; + let Unpredictable{11-0} = 0b111111111111; +} diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -6370,7 +6370,7 @@ Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && Mnemonic != "sbcs" && Mnemonic != "rscs" && !(hasMVE() && - (Mnemonic.startswith("vmine") || + (Mnemonic.startswith("vmine") || Mnemonic.startswith("vpsel") || Mnemonic.startswith("vshl") || Mnemonic.startswith("vrshl") || Mnemonic.startswith("vmvne") || Mnemonic.startswith("vorne") || (Mnemonic.startswith("vnege") && !Mnemonic.startswith("vnegeq")) || @@ -6425,7 +6425,7 @@ Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" && Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" && Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" && - Mnemonic != "vcvtt" && Mnemonic != "vcvt") { + Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") { unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1)); if (CC != ~0U) { Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1); @@ -6501,7 +6501,9 @@ Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") || (hasMVE() && (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") || - Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) { + Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") || + Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") || + Mnemonic.startswith("letp")))) { // These mnemonics are never predicable CanAcceptPredicationCode = false; } else if (!isThumb()) { @@ -6763,7 +6765,7 @@ Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4")) return true; - if (Mnemonic.startswith("vctp")) + if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot")) return false; if (Mnemonic.startswith("vmov") && @@ -7916,14 +7918,19 @@ "code specified"); break; } - case ARM::t2WLS: { + case ARM::t2WLS: + case ARM::MVE_WLSTP8: + case ARM::MVE_WLSTP16: + case ARM::MVE_WLSTP32: + case ARM::MVE_WLSTP64: { int idx = Opcode == ARM::t2WLS ? 3 : 4; if (!static_cast(*Operands[idx]).isUnsignedOffset<11, 1>()) return Error(Operands[idx]->getStartLoc(), "loop end is out of range or not a positive multiple of 2"); break; } - case ARM::t2LEUpdate: { + case ARM::t2LEUpdate: + case ARM::MVE_LEUpdateTP: { if (Inst.getOperand(2).isImm() && !(Inst.getOperand(2).getImm() < 0 && Inst.getOperand(2).getImm() >= -4094 && diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -5965,10 +5965,14 @@ const void *Decoder) { DecodeStatus S = MCDisassembler::Success; + if (Inst.getOpcode() == ARM::MVE_LCTP) + return S; + unsigned Imm = fieldFromInstruction(Insn, 11, 1) | fieldFromInstruction(Insn, 1, 10) << 1; switch (Inst.getOpcode()) { case ARM::t2LEUpdate: + case ARM::MVE_LEUpdateTP: Inst.addOperand(MCOperand::createReg(ARM::LR)); Inst.addOperand(MCOperand::createReg(ARM::LR)); LLVM_FALLTHROUGH; @@ -5978,6 +5982,10 @@ return MCDisassembler::Fail; break; case ARM::t2WLS: + case ARM::MVE_WLSTP8: + case ARM::MVE_WLSTP16: + case ARM::MVE_WLSTP32: + case ARM::MVE_WLSTP64: Inst.addOperand(MCOperand::createReg(ARM::LR)); if (!Check(S, DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), @@ -5987,9 +5995,22 @@ return MCDisassembler::Fail; break; case ARM::t2DLS: + case ARM::MVE_DLSTP8: + case ARM::MVE_DLSTP16: + case ARM::MVE_DLSTP32: + case ARM::MVE_DLSTP64: unsigned Rn = fieldFromInstruction(Insn, 16, 4); if (Rn == 0xF) { - return MCDisassembler::Fail; + // Enforce all the rest of the instruction bits in LCTP, which + // won't have been reliably checked based on LCTP's own tablegen + // record, because we came to this decode by a roundabout route. + uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; + if ((Insn & ~SBZMask) != CanonicalLCTP) + return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail + if (Insn != CanonicalLCTP) + Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail + + Inst.setOpcode(ARM::MVE_LCTP); } else { Inst.addOperand(MCOperand::createReg(ARM::LR)); if (!Check(S, DecoderGPRRegisterClass(Inst, diff --git a/llvm/test/MC/ARM/mve-misc.s b/llvm/test/MC/ARM/mve-misc.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/ARM/mve-misc.s @@ -0,0 +1,147 @@ +# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \ +# RUN: | FileCheck --check-prefix=CHECK-NOFP %s +# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \ +# RUN: | FileCheck --check-prefix=CHECK %s +# RUN: FileCheck --check-prefix=ERROR < %t %s + +# CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f] +# CHECK-NOFP: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f] +vpsel q0, q5, q2 + +# CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f] +# CHECK-NOFP: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f] +vpnot + +# CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3] +# CHECK-NOFP: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3] +wlstp.8 lr, r0, #1668 + +# CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3] +# CHECK-NOFP: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3] +wlstp.16 lr, r0, #1668 + +# CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd] +# CHECK-NOFP: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd] +wlstp.32 lr, r4, #2706 + +# CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd] +# CHECK-NOFP: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd] +wlstp.64 lr, lr, #3026 + +# CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6] +# CHECK-NOFP: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6] +wlstp.8 lr, r5, #3436 + +# CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2] +# CHECK-NOFP: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2] +wlstp.16 lr, r1, #1060 + +# CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7] +# CHECK-NOFP: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7] +wlstp.32 lr, r7, #4036 + +# CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9] +# CHECK-NOFP: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9] +wlstp.8 lr, r1, #538 + +# CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2] +# CHECK-NOFP: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2] +wlstp.8 lr, r10, #1404 + +# CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2] +# CHECK-NOFP: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2] +wlstp.8 lr, r10, #1408 + +# CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc] +# CHECK-NOFP: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc] +wlstp.8 lr, r10, #2358 + +# CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf] +# CHECK-NOFP: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf] +wlstp.8 lr, r10, #4086 + +# CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca] +# CHECK-NOFP: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca] +wlstp.8 lr, r11, #1442 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2 +wlstp.8 lr, r10, #1443 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2 +wlstp.8 lr, r10, #4096 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14 +wlstp.8 lr, sp, #1442 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14 +wlstp.16 lr, sp, #1442 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +wlstp.32 r10, r11, #1442 + +# CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0] +# CHECK-NOFP: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0] +dlstp.8 lr, r5 + +# CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0] +# CHECK-NOFP: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0] +dlstp.16 lr, r5 + +# CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0] +# CHECK-NOFP: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0] +dlstp.32 lr, r7 + +# CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0] +# CHECK-NOFP: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0] +dlstp.64 lr, r2 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14 +dlstp.64 lr, sp + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +dlstp.64 r10, r0 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14 +dlstp.64 lr, pc + +# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8] +# CHECK-NOFP: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8] +letp lr, #-2 + +# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0] +# CHECK-NOFP: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0] +letp lr, #-8 + +# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf] +# CHECK-NOFP: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf] +letp lr, #-4094 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +letp r0, #-8 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2 +letp lr, #8 + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2 +letp lr, #-4096 + +# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0] +# CHECK-NOFP: lctp @ encoding: [0x0f,0xf0,0x01,0xe0] +lctp + +# CHECK: it eq @ encoding: [0x08,0xbf] +# CHECK-NOFP: it eq @ encoding: [0x08,0xbf] +it eq +# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0] +# CHECK-NOFP: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0] +lctpeq + +vpste +vpselt.s16 q0, q1, q2 +vpsele.i32 q0, q1, q2 +# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f] +# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f] +# CHECK: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f] +# CHECK-NOFP: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f] +# CHECK: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f] +# CHECK-NOFP: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f] diff --git a/llvm/test/MC/Disassembler/ARM/mve-misc.txt b/llvm/test/MC/Disassembler/ARM/mve-misc.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/mve-misc.txt @@ -0,0 +1,111 @@ +# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s +# RUN: FileCheck --check-prefix=ERROR < %t %s +# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t +# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s + +# CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3b,0xfe,0x05,0x0f] + +# CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x31,0xfe,0x4d,0x0f] + +# CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x00,0xf0,0x43,0xc3] + +# CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x10,0xf0,0x43,0xc3] + +# CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x24,0xf0,0x49,0xcd] + +# CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x3e,0xf0,0xe9,0xcd] + +# CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x05,0xf0,0xb7,0xc6] + +# CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x11,0xf0,0x13,0xc2] + +# CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x27,0xf0,0xe3,0xc7] + +# CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x01,0xf0,0x0d,0xc9] + +# CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0a,0xf0,0xbf,0xc2] + +# CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0a,0xf0,0xc1,0xc2] + +# CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0a,0xf0,0x9b,0xcc] + +# CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0a,0xf0,0xfb,0xcf] + +# CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0b,0xf0,0xd1,0xca] + +# CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x05,0xf0,0x01,0xe0] + +# CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x15,0xf0,0x01,0xe0] + +# CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x27,0xf0,0x01,0xe0] + +# CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x32,0xf0,0x01,0xe0] + +# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x1f,0xf0,0x01,0xc8] + +# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x1f,0xf0,0x05,0xc0] + +# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x1f,0xf0,0xff,0xcf] + +# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x0f,0xf0,0x01,0xe0] + +# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0x1f,0xf0,0x01,0xe0] + +# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x4f,0xf0,0x01,0xe0] + +# The following tests have to go last because of the NOMVE-NOT checks. + +# CHECK: it eq @ encoding: [0x08,0xbf] +# CHECK-NOMVE: it eq @ encoding: [0x08,0xbf] +[0x08,0xbf] +# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0] +# CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0] +[0x0f,0xf0,0x01,0xe0]