diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2477,6 +2477,15 @@ NumBits = 8; Scale = 2; break; + case ARMII::AddrModeT2_i7: + case ARMII::AddrModeT2_i7s2: + case ARMII::AddrModeT2_i7s4: + ImmIdx = FrameRegIdx+1; + InstrOffs = MI.getOperand(ImmIdx).getImm(); + NumBits = 7; + Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 : + AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1); + break; default: llvm_unreachable("Unsupported addressing mode!"); } diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -109,6 +109,9 @@ def AddrMode_i12 : AddrMode<16>; def AddrMode5FP16 : AddrMode<17>; def AddrModeT2_ldrex : AddrMode<18>; +def AddrModeT2_i7s4 : AddrMode<19>; +def AddrModeT2_i7s2 : AddrMode<20>; +def AddrModeT2_i7 : AddrMode<21>; // Load / store index mode. class IndexMode val> { diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1261,6 +1261,15 @@ let MIOperandInfo = (ops GPR:$base); } +// t_addr_offset_none := reg [r0-r7] +def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } +def t_addr_offset_none : MemOperand { + let PrintMethod = "printAddrMode7Operand"; + let DecoderMethod = "DecodetGPRRegisterClass"; + let ParserMatchClass = MemNoOffsetTAsmOperand; + let MIOperandInfo = (ops tGPR:$base); +} + def nohash_imm : Operand { let PrintMethod = "printNoHashImmediate"; } diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -3438,3 +3438,532 @@ let Defs = [P0]; } + +// Register list operands +def VecList2QAsmOperand : AsmOperandClass { + let Name = "VecListTwoMQ"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addMVEVecListOperands"; +} + +def VecList2Q : RegisterOperand { + let ParserMatchClass = VecList2QAsmOperand; +} + +def VecList4QAsmOperand : AsmOperandClass { + let Name = "VecListFourMQ"; + let ParserMethod = "parseVectorList"; + let RenderMethod = "addMVEVecListOperands"; +} + +def VecList4Q : RegisterOperand { + let ParserMatchClass = VecList4QAsmOperand; +} + +class mve_load_store pattern> + : MVE_MI { + let Inst{31-29} = 0b111; + let Inst{28} = U; + let Inst{27-25} = 0b110; + let Inst{24} = P; + let Inst{23} = A; + let Inst{21} = W; + let Inst{20} = load; + let Inst{12} = b12; + let Inst{11-9} = 0b111; +} + +// This class and subsequently named (multi)classes are for the deinterleaved +// vector loads and stores. +class mve_vld_vst_de pat, bits<2> size, bit load, + dag Oops, dag loadIops, dag wbIops, string suffix, + list pattern=[]> + : mve_load_store<1, 0, 1, W, 1, load, + Oops, + !con(loadIops, wbIops), + !strconcat(!if(load, "vld", "vst"), !if(bit0, "4", "2")), + suffix, !if(W, "$VQd, $Rn!", "$VQd, $Rn"), + !if(W, "$Rn.base = $wb", "") # + !if(load, ",$VQdSrc = $VQd", ""), pattern> { + bits<4> VQd; + bits<4> Rn; + let Inst{22} = 0b0; + let Inst{21} = W; + let Inst{19-16} = Rn{3-0}; + let Inst{15-13} = VQd{2-0}; + let Inst{8-7} = size{1-0}; + let Inst{6-5} = pat{1-0}; + let Inst{4-1} = 0b0000; + let Inst{0} = bit0; +} + +multiclass mve_vld_vst_de_pat size, bit load, dag wbOops, + dag wbIops, string suffix> { + def 2P0 : + mve_vld_vst_de; + + def 2P1 : + mve_vld_vst_de; + + def 4P0 : + mve_vld_vst_de; + def 4P1 : + mve_vld_vst_de; + def 4P2 : + mve_vld_vst_de; + def 4P3 : + mve_vld_vst_de; +} + +multiclass mve_vld_vst_de_size { + defm d8 : mve_vld_vst_de_pat; + defm d16 : mve_vld_vst_de_pat; + defm d32 : mve_vld_vst_de_pat; +} + +multiclass mve_vld_vst_de_wb { + defm NoWriteBack + : mve_vld_vst_de_size<0, load, (outs ), (ins t2_addr_offset_none:$Rn)>; + defm WriteBack + : mve_vld_vst_de_size<1, load, (outs t2rGPR:$wb), + (ins t2_nosp_addr_offset_none:$Rn)>; +} + +let mayLoad = 1 in { +defm MVE_VST : mve_vld_vst_de_wb<0b0>; +} + +let mayStore = 1 in { +defm MVE_VLD : mve_vld_vst_de_wb<0b1>; +} + +class mve_load_store_pred pattern=[]> +// Always use vpred_n rather than vpred_r, because we never need an +// 'inactive' parameter: for stores, there isn't an output register, +// and for loads, predicated loads zero the inactive lanes rather than +// preserving their input values. + : MVE_p { + let Inst{28} = U; + let Inst{25} = 0b0; + let Inst{24} = P; + let Inst{22} = 0b0; + let Inst{21} = W; + let Inst{20} = load; +} + +class mve_vldr_vstr_1 size, bit opc1, + dag oops, dag iops, string asm, string suffix, string ops, + string cstr> + : mve_load_store_pred { + bits<11> addr; + bits<3> Qd; + let Inst{23} = addr{7}; + let Inst{19} = opc1; + let Inst{18-16} = addr{10-8}; + let Inst{15-13} = Qd{2-0}; + let Inst{12-9} = 0b0111; + let Inst{8-7} = size{1-0}; + let Inst{6-0} = addr{6-0}; +} + +// This multiclass is used for the vectore stores and loads from consecutive +// memory with a size higher than the written/read memory. +multiclass mve_vldr_vstr_1_addr size, bit opc1, bit load, + string asm, string suffix, int shift, + AddrMode am> { + def _off : + mve_vldr_vstr_1:$addr), + (ins MQPR:$Qd, taddrmode_imm7:$addr)), + asm, suffix, "$Qd, $addr", "" > { + let IM = IndexModePost; + let AM = am; + } + + def _pre : + mve_vldr_vstr_1:$addr), + (ins MQPR:$Qd, taddrmode_imm7:$addr)), + asm, suffix, "$Qd, $addr!", "$addr.base = $wb"> { + let IM = IndexModePre; + let AM = am; + let DecoderMethod = "DecodeMVE_MEM_1_pre<"#shift#">"; + } + def _post : + mve_vldr_vstr_1:$addr), + (ins MQPR:$Qd, t_addr_offset_none:$Rn, + t2am_imm7_offset:$addr)), + asm, suffix, "$Qd, $Rn$addr", "$Rn.base = $wb"> { + bits<4> Rn; + let Inst{18-16} = Rn{2-0}; + let IM = IndexModePost; + let AM = am; + } +} + +let mayLoad = 1 in { +defm MVE_VLDRBS16 + : mve_vldr_vstr_1_addr<0b0, 0b01, 0b0, 0b1, "vldrb", "s16", 0, + AddrModeT2_i7>; +defm MVE_VLDRBS32 + : mve_vldr_vstr_1_addr<0b0, 0b10, 0b0, 0b1, "vldrb", "s32", 0, + AddrModeT2_i7>; +defm MVE_VLDRBU16 + : mve_vldr_vstr_1_addr<0b1, 0b01, 0b0, 0b1, "vldrb", "u16", 0, + AddrModeT2_i7>; +defm MVE_VLDRBU32 + : mve_vldr_vstr_1_addr<0b1, 0b10, 0b0, 0b1, "vldrb", "u32", 0, + AddrModeT2_i7>; +defm MVE_VLDRHS32 + : mve_vldr_vstr_1_addr<0b0, 0b10, 0b1, 0b1, "vldrh", "s32", 1, + AddrModeT2_i7s2>; +defm MVE_VLDRHU32 + : mve_vldr_vstr_1_addr<0b1, 0b10, 0b1, 0b1, "vldrh", "u32", 1, + AddrModeT2_i7s2>; +} // let mayLoad = 1 + +let mayStore = 1 in { +defm MVE_VSTRB16 + : mve_vldr_vstr_1_addr<0b0, 0b01, 0b0, 0b0, "vstrb", "16", 0, + AddrModeT2_i7>; +defm MVE_VSTRB32 + : mve_vldr_vstr_1_addr<0b0, 0b10, 0b0, 0b0, "vstrb", "32", 0, + AddrModeT2_i7>; +defm MVE_VSTRH32 + : mve_vldr_vstr_1_addr<0b0, 0b10, 0b1, 0b0, "vstrh", "32", 1, + AddrModeT2_i7s2>; +} // let mayStore = 1 + +// This multiclass is used for the vector stores and loads from consecutive +// memory with a size equal to the written/read memory. +class mve_vldr_vstr_2 size, dag oops, + dag iops, string asm, string suffix, string ops, + string cstr> + : mve_load_store_pred<0b0, P, W, load, oops, iops, asm, suffix, ops, cstr> { + bits<12> addr; + bits<3> Qd; + let Inst{23} = addr{7}; + let Inst{19-16} = addr{11-8}; + let Inst{15-13} = Qd{2-0}; + let Inst{12-9} = 0b1111; + let Inst{8-7} = size{1-0}; + let Inst{6-0} = addr{6-0}; +} +multiclass mve_vldr_vstr_2_addr size, bit load, string asm, + string suffix, int shift, AddrMode am> { + def _off : + mve_vldr_vstr_2<1, 0, load, size, + !if(load, (outs MQPR:$Qd), (outs)), + !if(load, (ins t2addrmode_imm7:$addr), + (ins MQPR:$Qd, t2addrmode_imm7:$addr)), + asm, suffix, "$Qd, $addr", "" > { + let IM = IndexModePost; + let AM = am; + } + + def _pre : + mve_vldr_vstr_2<1, 1, load, size, + !if(load, (outs t2rGPR:$wb, MQPR:$Qd), (outs t2rGPR:$wb)), + !if(load, (ins t2addrmode_imm7_pre:$addr), + (ins MQPR:$Qd, t2addrmode_imm7_pre:$addr)), + asm, suffix, "$Qd, $addr!", "$addr.base = $wb"> { + let IM = IndexModePre; + let AM = am; + let DecoderMethod = "DecodeMVE_MEM_2_pre<"#shift#">"; + } + + def _post : + mve_vldr_vstr_2<0, 1, load, size, + !if(load, (outs t2rGPR:$wb, MQPR:$Qd), (outs t2rGPR:$wb)), + !if(load, (ins t2_addr_offset_none:$Rn, + t2am_imm7_offset:$addr), + (ins MQPR:$Qd, t2_nosp_addr_offset_none:$Rn, + t2am_imm7_offset:$addr)), + asm, suffix, "$Qd, $Rn$addr", "$Rn.base = $wb"> { + bits<4> Rn; + let Inst{19-16} = Rn{3-0}; + let IM = IndexModePost; + let AM = am; + } +} + +let mayLoad = 1 in { +defm MVE_VLDRBU8 : mve_vldr_vstr_2_addr<0b00, 0b1, "vldrb", "u8", 0, AddrModeT2_i7>; +defm MVE_VLDRHU16 : mve_vldr_vstr_2_addr<0b01, 0b1, "vldrh", "u16", 1, AddrModeT2_i7s2>; +defm MVE_VLDRWU32 : mve_vldr_vstr_2_addr<0b10, 0b1, "vldrw", "u32", 2, AddrModeT2_i7s4>; +} // let mayLoad = 1 + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s8", ".8", ".f8"] in { + def : MnemonicAlias; + } +} + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s16", ".16", ".f16"] in { + def : MnemonicAlias; + } +} + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s32", ".32", ".f32"] in { + def : MnemonicAlias; + } +} + +let mayStore = 1 in { +defm MVE_VSTRBU8 : mve_vldr_vstr_2_addr<0b00, 0b0, "vstrb", "8", 0, AddrModeT2_i7>; +defm MVE_VSTRHU16 : mve_vldr_vstr_2_addr<0b01, 0b0, "vstrh", "16", 1, AddrModeT2_i7s2>; +defm MVE_VSTRWU32 : mve_vldr_vstr_2_addr<0b10, 0b0, "vstrw", "32", 2, AddrModeT2_i7s4>; +} // let mayStore = 1 + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s8", ".8", ".f8"] in { + def : MnemonicAlias; + } +} + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s16", ".16", ".f16"] in { + def : MnemonicAlias; + } +} + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s32", ".32", ".f32"] in { + def : MnemonicAlias; + } +} + +class MemRegRQOffsetAsmOperand : AsmOperandClass { + let Name = "MemRegRQS"#shift#"Offset"; + let PredicateMethod = "isMemRegRQOffset<"#shift#">"; + let RenderMethod = "addMemRegRQOffsetOperands"; +} + +def MemRegRQS0OffsetAsmOperand : MemRegRQOffsetAsmOperand<0>; +def MemRegRQS1OffsetAsmOperand : MemRegRQOffsetAsmOperand<1>; +def MemRegRQS2OffsetAsmOperand : MemRegRQOffsetAsmOperand<2>; +def MemRegRQS3OffsetAsmOperand : MemRegRQOffsetAsmOperand<3>; + +// mve_addr_rq_shift := reg + vreg{ << UXTW #shift} +class mve_addr_rq_shift : MemOperand { + let EncoderMethod = "getMveAddrModeRQOpValue"; + let PrintMethod = "printMveAddrModeRQOperand<"#shift#">"; + let ParserMatchClass = + !cast("MemRegRQS"#shift#"OffsetAsmOperand"); + let DecoderMethod = "DecodeMveAddrModeRQ"; + let MIOperandInfo = (ops GPRnopc:$base, MQPR:$offsreg); +} + +class MemRegQOffsetAsmOperand : AsmOperandClass { + let Name = "MemRegQS"#shift#"Offset"; + let PredicateMethod = "isMemRegQOffset<"#shift#">"; + let RenderMethod = "addMemRegQOffsetOperands"; +} + +def MemRegQS2OffsetAsmOperand : MemRegQOffsetAsmOperand<2>; +def MemRegQS3OffsetAsmOperand : MemRegQOffsetAsmOperand<3>; + +// mve_addr_q_shift := vreg {+ #imm7s2/4} +class mve_addr_q_shift : MemOperand { + let EncoderMethod = "getMveAddrModeQOpValue<"#shift#">"; + // Can be printed same way as other reg + imm operands + let PrintMethod = "printT2AddrModeImm8Operand"; + let ParserMatchClass = + !cast("MemRegQS"#shift#"OffsetAsmOperand"); + let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">"; + let MIOperandInfo = (ops MQPR:$base, i32imm:$imm); +} + +// This multiclass is used for the vector scatter stores and loads from +// consecutive memory with a size larger than the written/read memory. +class mve_vldr_vstr_sc1 size, bits<2> opc1, bit os, + dag addrOps, string asm, string suffix> + : mve_load_store_pred { + bits<7> addr; + bits<3> Qd; + let Inst{23} = 0b1; + let Inst{19-16} = addr{6-3}; + let Inst{15-13} = Qd{2-0}; + let Inst{12-9} = 0b0111; + let Inst{8-7} = size{1-0}; + let Inst{6} = opc1{1}; + let Inst{5} = 0; + let Inst{4} = opc1{0}; + let Inst{3-1} = addr{2-0}; + let Inst{0} = os; +} + +let mayStore = 1 in { +def mveVSTRB8noShift + : mve_vldr_vstr_sc1<0b0, 0b0, 0b00, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vstrb", "8">; +def mveVSTRB16noShift + : mve_vldr_vstr_sc1<0b0, 0b0, 0b01, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vstrb", "16">; +def mveVSTRB32noShift + : mve_vldr_vstr_sc1<0b0, 0b0, 0b10, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vstrb", "32">; +} // let mayStore = 1 + +multiclass mve_vldr_vstr_sc1_shift size, bits<2> opc1, + int shift, string asm, string suffix> { +def noShift + : mve_vldr_vstr_sc1:$addr), asm, suffix>; + +def Shift + : mve_vldr_vstr_sc1:$addr), asm, suffix>; +} + +let mayLoad = 1 in { +def MVE_VLDRBU8noShift + : mve_vldr_vstr_sc1<0b1, 0b1, 0b00, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u8">; +def MVE_VLDRBU16noShift + : mve_vldr_vstr_sc1<0b1, 0b1, 0b01, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u16">; +def MVE_VLDRBS16noShift + : mve_vldr_vstr_sc1<0b0, 0b1, 0b01, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vldrb", "s16">; +def MVE_VLDRBU32noShift + : mve_vldr_vstr_sc1<0b1, 0b1, 0b10, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u32">; +def MVE_VLDRBS32noShift + : mve_vldr_vstr_sc1<0b0, 0b1, 0b10, 0b00, 0b0, + (ins mve_addr_rq_shift<0>:$addr), "vldrb", "s32">; +defm MVE_VLDRHU16 + : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b01, 0b01, 1, "vldrh", "u16">; +defm MVE_VLDRHU32 + : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b10, 0b01, 1, "vldrh", "u32">; +defm MVE_VLDRHS32 + : mve_vldr_vstr_sc1_shift<0b0, 0b1, 0b10, 0b01, 1, "vldrh", "s32">; +defm MVE_VLDRWU32 + : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b10, 0b10, 2, "vldrw", "u32">; +defm MVE_VLDRDU64 + : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b11, 0b11, 3, "vldrd", "u64">; +} // let mayLoad = 1 + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s64", ".64", ".f64"] in { + def : MnemonicAlias; + } +} + +let mayStore = 1 in { +defm MVE_VSTRH16 + : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b01, 0b01, 1, "vstrh", "16">; +defm MVE_VSTRH32 + : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b10, 0b01, 1, "vstrh", "32">; +defm MVE_VSTRW32 + : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b10, 0b10, 2, "vstrw", "32">; +defm MVE_VSTRD64 + : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b11, 0b11, 3, "vstrd", "64">; +} // let mayStore = 1 + +foreach cond = ["", "t", "e"] in { + foreach suffix = [".s64", ".64", ".f64"] in { + def : MnemonicAlias; + } +} + +// This multiclass is used for the vector scatter stores and loads from +// consecutive memory with a size equal to the written/read memory. +class mve_vldr_vstr_sc2 + : mve_load_store_pred<0b1, 0b1, W, load, + !if(load, !con(wbops, (outs MQPR:$Qd)), wbops), + !if(load, addrOps, !con((ins MQPR:$Qd), addrOps)), + asm, suffix, ops, + !if(load, !strconcat (cstr, ",@earlyclobber $Qd"), + cstr)> { + bits<11> addr; + bits<3> Qd; + let Inst{23} = addr{7}; + let Inst{19-17} = addr{10-8}; + let Inst{16} = 0b0; + let Inst{15-13} = Qd{2-0}; + let Inst{12-9} = 0b1111; + let Inst{8} = opc1; + let Inst{7} = 0b0; + let Inst{6-0} = addr{6-0}; +} + + +multiclass mve_vldr_vstr_sc2_addr { + def NoWriteBack + : mve_vldr_vstr_sc2<0b0, load, opc1, (outs), addrOps, asm, + "$Qd, $addr", suffix, "">; + let DecoderMethod="DecodeMVE_MEM_3_pre<"#shift#">" in { + def WriteBack + : mve_vldr_vstr_sc2<0b1, load, opc1, (outs MQPR:$wb), addrOps, + asm, "$Qd, $addr!", suffix, "$addr.base = $wb">; + } +} + +let mayLoad = 1 in { +defm MVE_VLDRWU32 + : mve_vldr_vstr_sc2_addr<0b1, 0b0, (ins mve_addr_q_shift<2>:$addr), "vldrw", + "u32", 2>; +defm MVE_VLDRDU64 + : mve_vldr_vstr_sc2_addr<0b1, 0b1, (ins mve_addr_q_shift<3>:$addr), "vldrd", + "u64", 3>; +} // let mayLoad = 1 + +let mayStore = 1 in { +defm MVE_VSTRW32 + : mve_vldr_vstr_sc2_addr<0b0, 0b0, (ins mve_addr_q_shift<2>:$addr), "vstrw", + "32", 2>; +defm MVE_VSTRD64 + : mve_vldr_vstr_sc2_addr<0b0, 0b1, (ins mve_addr_q_shift<3>:$addr), "vstrd", + "64", 3>; +} // let mayStore = 1 diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -214,7 +214,7 @@ def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";} def t2addrmode_posimm8 : MemOperand { let PrintMethod = "printT2AddrModeImm8Operand"; - let EncoderMethod = "getT2AddrModeImm8OpValue"; + let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; let DecoderMethod = "DecodeT2AddrModeImm8"; let ParserMatchClass = MemPosImm8OffsetAsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); @@ -225,7 +225,7 @@ def t2addrmode_negimm8 : MemOperand, ComplexPattern { let PrintMethod = "printT2AddrModeImm8Operand"; - let EncoderMethod = "getT2AddrModeImm8OpValue"; + let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; let DecoderMethod = "DecodeT2AddrModeImm8"; let ParserMatchClass = MemNegImm8OffsetAsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); @@ -235,7 +235,7 @@ def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } class T2AddrMode_Imm8 : MemOperand, ComplexPattern { - let EncoderMethod = "getT2AddrModeImm8OpValue"; + let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; let DecoderMethod = "DecodeT2AddrModeImm8"; let ParserMatchClass = MemImm8OffsetAsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); @@ -309,6 +309,75 @@ let DecoderMethod = "DecodeT2Imm7S4"; } +// taddrmode_imm7 := reg[r0-r7] +/- (imm7 << shift) +class TMemImm7ShiftOffsetAsmOperand + : AsmOperandClass {let Name = "TMemImm7Shift"#shift#"Offset";} + +def TMemImm7Shift0OffsetAsmOperand : TMemImm7ShiftOffsetAsmOperand<0>; +def TMemImm7Shift1OffsetAsmOperand : TMemImm7ShiftOffsetAsmOperand<1>; + +class taddrmode_imm7 : MemOperand { + let ParserMatchClass = + !cast("TMemImm7Shift"#shift#"OffsetAsmOperand"); + // They are printed the same way as the T2 imm8 version + let PrintMethod = "printT2AddrModeImm8Operand"; + // This can also be the same as the T2 version. + let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">"; + let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">"; + let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); +} + +// t2addrmode_imm7 := reg +/- (imm7) +class MemImm7ShiftOffsetAsmOperand +: AsmOperandClass {let Name = "MemImm7Shift"#shift#"Offset"; } + +def MemImm7Shift0OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<0>; +def MemImm7Shift1OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<1>; +def MemImm7Shift2OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<2>; +class T2AddrMode_Imm7 : MemOperand, + ComplexPattern", []> { + let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">"; + let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 0>"; + let ParserMatchClass = + !cast("MemImm7Shift"#shift#"OffsetAsmOperand"); + let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); +} + +class t2addrmode_imm7 : T2AddrMode_Imm7 { + // They are printed the same way as the imm8 version + let PrintMethod = "printT2AddrModeImm8Operand"; +} + +class MemImm7ShiftOffsetWBAsmOperand +: AsmOperandClass {let Name = "MemImm7Shift"#shift#"OffsetWB"; } + +def MemImm7Shift0OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<0>; +def MemImm7Shift1OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<1>; +def MemImm7Shift2OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<2>; + +class t2addrmode_imm7_pre : T2AddrMode_Imm7 { + // They are printed the same way as the imm8 version + let PrintMethod = "printT2AddrModeImm8Operand"; + let ParserMatchClass = + !cast("MemImm7Shift"#shift#"OffsetWBAsmOperand"); + let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 1>"; + let MIOperandInfo = (ops rGPR:$base, i32imm:$offsim); +} + +class t2am_imm7shiftOffsetAsmOperand + : AsmOperandClass { let Name = "Imm7Shift"#shift; } +def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>; +def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>; +def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>; + +class t2am_imm7_offset : MemOperand { + // They are printed the same way as the imm8 version + let PrintMethod = "printT2AddrModeImm8OffsetOperand"; + let ParserMatchClass = + !cast("t2am_imm7shift"#shift#"OffsetAsmOperand"); + let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">"; + let DecoderMethod = "DecodeT2Imm7<"#shift#">"; +} // t2addrmode_imm0_1020s4 := reg + (imm8 << 2) def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { let Name = "MemImm0_1020s4Offset"; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1035,7 +1035,7 @@ if (!CE) return false; Val = CE->getValue(); } - else if (isMem()) { + else if (isGPRMem()) { if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; if(Memory.BaseRegNum != ARM::PC) return false; Val = Memory.OffsetImm->getValue(); @@ -1069,7 +1069,14 @@ int64_t Value = CE->getValue(); return ((Value & 3) == 0) && Value >= N && Value <= M; } - + template + bool isImmediateS2() const { + if (!isImm()) return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return ((Value & 1) == 0) && Value >= N && Value <= M; + } bool isFBits16() const { return isImmediate<0, 17>(); } @@ -1082,6 +1089,18 @@ bool isImm7s4() const { return isImmediateS4<-508, 508>(); } + bool isImm7Shift0() const { + return isImmediate<-127, 127>(); + } + bool isImm7Shift1() const { + return isImmediateS2<-255, 255>(); + } + bool isImm7Shift2() const { + return isImmediateS4<-511, 511>(); + } + bool isImm7() const { + return isImmediate<-127, 127>(); + } bool isImm0_1020s4() const { return isImmediateS4<0, 1020>(); } @@ -1263,6 +1282,22 @@ bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; } bool isMem() const override { + return isGPRMem() || isMVEMem(); + } + bool isMVEMem() const { + if (Kind != k_Memory) + return false; + if (Memory.BaseRegNum && + !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && + !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) + return false; + if (Memory.OffsetRegNum && + !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( + Memory.OffsetRegNum)) + return false; + return true; + } + bool isGPRMem() const { if (Kind != k_Memory) return false; if (Memory.BaseRegNum && @@ -1353,14 +1388,14 @@ return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; } bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { - if (!isMem()) + if (!isGPRMem()) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const { - if (!isMem()) + if (!isGPRMem()) return false; if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( @@ -1372,7 +1407,7 @@ (alignOK || Memory.Alignment == Alignment); } bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const { - if (!isMem()) + if (!isGPRMem()) return false; if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( @@ -1383,8 +1418,20 @@ return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } + bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const { + if (!isGPRMem()) + return false; + + if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( + Memory.BaseRegNum)) + return false; + + // No offset of any kind. + return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && + (alignOK || Memory.Alignment == Alignment); + } bool isMemPCRelImm12() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base register must be PC. if (Memory.BaseRegNum != ARM::PC) @@ -1471,7 +1518,7 @@ } bool isAddrMode2() const { - if (!isMem() || Memory.Alignment != 0) return false; + if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return true; // Immediate offset in range [-4095, 4095]. @@ -1496,7 +1543,7 @@ // and we reject it. if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.Alignment != 0) return false; + if (!isGPRMem() || Memory.Alignment != 0) return false; // No shifts are legal for AM3. if (Memory.ShiftType != ARM_AM::no_shift) return false; // Check for register offset. @@ -1530,7 +1577,7 @@ // and we reject it. if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.Alignment != 0) return false; + if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return false; // Immediate offset in range [-1020, 1020] and a multiple of 4. @@ -1546,7 +1593,7 @@ // and we reject it. if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.Alignment != 0) return false; + if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return false; // Immediate offset in range [-510, 510] and a multiple of 2. @@ -1557,14 +1604,14 @@ } bool isMemTBB() const { - if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || + if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return true; } bool isMemTBH() const { - if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || + if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || Memory.Alignment != 0 ) return false; @@ -1572,13 +1619,13 @@ } bool isMemRegOffset() const { - if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) + if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) return false; return true; } bool isT2MemRegOffset() const { - if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || + if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) return false; // Only lsl #{0, 1, 2, 3} allowed. @@ -1592,7 +1639,7 @@ bool isMemThumbRR() const { // Thumb reg+reg addressing is simple. Just two registers, a base and // an offset. No shifts, negations or any other complicating factors. - if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || + if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return isARMLowRegister(Memory.BaseRegNum) && @@ -1600,7 +1647,7 @@ } bool isMemThumbRIs4() const { - if (!isMem() || Memory.OffsetRegNum != 0 || + if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 124]. @@ -1610,7 +1657,7 @@ } bool isMemThumbRIs2() const { - if (!isMem() || Memory.OffsetRegNum != 0 || + if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 62]. @@ -1620,7 +1667,7 @@ } bool isMemThumbRIs1() const { - if (!isMem() || Memory.OffsetRegNum != 0 || + if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset in range [0, 31]. @@ -1630,7 +1677,7 @@ } bool isMemThumbSPI() const { - if (!isMem() || Memory.OffsetRegNum != 0 || + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 1020]. @@ -1645,7 +1692,7 @@ // and we reject it. if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [-1020, 1020]. if (!Memory.OffsetImm) return true; @@ -1660,7 +1707,7 @@ // and we reject it. if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( Memory.BaseRegNum)) return false; @@ -1671,7 +1718,7 @@ return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN; } bool isMemImm0_1020s4Offset() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [0, 1020]. if (!Memory.OffsetImm) return true; @@ -1680,7 +1727,7 @@ } bool isMemImm8Offset() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; @@ -1690,9 +1737,136 @@ return (Val == std::numeric_limits::min()) || (Val > -256 && Val < 256); } + bool isTMemImm7Shift0Offset() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(Memory.BaseRegNum)) + return false; + // Immediate offset in range [-127, 127]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || (Val > -128 && Val < 128); + } + bool isTMemImm7Shift1Offset() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(Memory.BaseRegNum)) + return false; + // Immediate offset is multiple of 2 and in range [-254, 254]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || + (Val > -256 && Val < 256 && ((Val & 0x1) == 0)); + } + bool isMemImm7Shift0Offset() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset in range [-127, 127]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || (Val > -128 && Val < 128); + } + bool isMemImm7Shift1Offset() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset is multiple of 2 and in range [-254, 254]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || + (Val > -256 && Val < 256 && ((Val & 0x1) == 0)); + } + bool isMemImm7Shift2Offset() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset is multiple of 4 in range [-508, 508]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || + (Val > -512 && Val < 512 && ((Val & 0x3) == 0)); + } + bool isMemImm7Shift0OffsetWB() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset in range [-127, 127]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || (Val > -128 && Val < 128); + } + bool isMemImm7Shift1OffsetWB() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset is multiple of 2 and in range [-254, 254]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || + (Val > -256 && Val < 256 && ((Val & 0x1) == 0)); + } + bool isMemImm7Shift2OffsetWB() const { + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || + !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( + Memory.BaseRegNum)) + return false; + // Immediate offset is multiple of 4 in range [-508, 508]. + if (!Memory.OffsetImm) return true; + int64_t Val = Memory.OffsetImm->getValue(); + return (Val == INT32_MIN) || + (Val > -512 && Val < 512 && ((Val & 0x3) == 0)); + } + template bool isMemRegRQOffset() const { + if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0) + return false; + + if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( + Memory.BaseRegNum)) + return false; + if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( + Memory.OffsetRegNum)) + return false; + + if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) + return false; + + if (shift > 0 && + (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) + return false; + + return true; + } + + template bool isMemRegQOffset() const { + if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + return false; + + if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( + Memory.BaseRegNum)) + return false; + + if(!Memory.OffsetImm) return true; + static_assert(shift < 56, + "Such that we dont shift by a value higher than 62"); + int64_t Val = Memory.OffsetImm->getValue(); + + // The value must be a multiple of (1 << shift) + if ((Val & ((1U << shift) - 1)) != 0) + return false; + + // And be in the right range, depending on the amount that it is shifted + // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set + // separately. + int64_t Range = (1U << (7+shift)) - 1; + return (Val == INT32_MIN) || (Val > -Range && Val < Range); + } bool isMemPosImm8Offset() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 255]. if (!Memory.OffsetImm) return true; @@ -1701,7 +1875,7 @@ } bool isMemNegImm8Offset() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; @@ -1713,7 +1887,7 @@ } bool isMemUImm12Offset() const { - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 4095]. if (!Memory.OffsetImm) return true; @@ -1729,7 +1903,7 @@ if (isImm() && !isa(getImm())) return true; - if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) + if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; @@ -1780,6 +1954,12 @@ return VectorList.Count == 1; } + bool isVecListTwoMQ() const { + return isSingleSpacedVectorList() && VectorList.Count == 2 && + ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( + VectorList.RegNum); + } + bool isVecListDPair() const { if (!isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] @@ -1813,6 +1993,12 @@ return VectorList.Count == 4; } + bool isVecListFourMQ() const { + return isSingleSpacedVectorList() && VectorList.Count == 4 && + ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( + VectorList.RegNum); + } + bool isSingleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; } @@ -2445,6 +2631,30 @@ Inst.addOperand(MCOperand::createImm(CE->getValue())); } + void addImm7Shift0Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::createImm(CE->getValue())); + } + + void addImm7Shift1Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::createImm(CE->getValue())); + } + + void addImm7Shift2Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::createImm(CE->getValue())); + } + + void addImm7Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::createImm(CE->getValue())); + } + void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored @@ -2554,7 +2764,7 @@ return; } - assert(isMem() && "Unknown value type!"); + assert(isGPRMem() && "Unknown value type!"); assert(isa(Memory.OffsetImm) && "Unknown value type!"); Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); } @@ -2584,6 +2794,16 @@ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); } + void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + } + + void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + } + void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); int32_t Imm = Memory.OffsetImm->getValue(); @@ -2840,6 +3060,62 @@ addMemImm8OffsetOperands(Inst, N); } + void addTMemImm7Shift0OffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addTMemImm7Shift1OffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift0OffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift1OffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift2OffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift0OffsetWBOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift1OffsetWBOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + + void addMemImm7Shift2OffsetWBOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If this is an immediate, it's a label reference. @@ -2900,6 +3176,19 @@ Inst.addOperand(MCOperand::createImm(Val)); } + void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); + } + + void addMemRegQOffsetOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; + Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); + Inst.addOperand(MCOperand::createImm(Val)); + } + void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); @@ -3007,6 +3296,37 @@ Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); } + void addMVEVecListOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + + // When we come here, the VectorList field will identify a range + // of q-registers by its base register and length, and it will + // have already been error-checked to be the expected length of + // range and contain only q-regs in the range q0-q7. So we can + // count on the base register being in the range q0-q6 (for 2 + // regs) or q0-q4 (for 4) + // + // The MVE instructions taking a register range of this kind will + // need an operand in the QQPR or QQQQPR class, representing the + // entire range as a unit. So we must translate into that class, + // by finding the index of the base register in the MQPR reg + // class, and returning the super-register at the corresponding + // index in the target class. + + const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; + const MCRegisterClass *RC_out = (VectorList.Count == 2) ? + &ARMMCRegisterClasses[ARM::QQPRRegClassID] : + &ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; + + unsigned I, E = RC_out->getNumRegs(); + for (I = 0; I < E; I++) + if (RC_in->getRegister(I) == VectorList.RegNum) + break; + assert(I < E && "Invalid vector list start register!"); + + Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I))); + } + void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); @@ -4286,7 +4606,7 @@ // As an extension (to match gas), support a plain D register or Q register // (without encosing curly braces) as a single or double entry list, // respectively. - if (Parser.getTok().is(AsmToken::Identifier)) { + if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) { SMLoc E = Parser.getTok().getEndLoc(); int Reg = tryParseRegister(); if (Reg == -1) @@ -4354,9 +4674,14 @@ unsigned Count = 1; int Spacing = 0; unsigned FirstReg = Reg; + + if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { + Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected"); + return MatchOperand_ParseFail; + } // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. - if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { + else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { FirstReg = Reg = getDRegFromQReg(Reg); Spacing = 1; // double-spacing requires explicit D registers, otherwise // it's ambiguous with four-register single spaced. @@ -4386,14 +4711,17 @@ return MatchOperand_ParseFail; } // Allow Q regs and just interpret them as the two D sub-registers. - if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) + if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) EndReg = getDRegFromQReg(EndReg) + 1; // If the register is the same as the start reg, there's nothing // more to do. if (Reg == EndReg) continue; // The register must be in the same register class as the first. - if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { + if ((hasMVE() && + !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || + (!hasMVE() && + !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { Error(AfterMinusLoc, "invalid register in register list"); return MatchOperand_ParseFail; } @@ -4426,13 +4754,21 @@ Error(RegLoc, "register expected"); return MatchOperand_ParseFail; } + + if (hasMVE()) { + if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { + Error(RegLoc, "vector register in range Q0-Q7 expected"); + return MatchOperand_ParseFail; + } + Spacing = 1; + } // vector register lists must be contiguous. // It's OK to use the enumeration values directly here rather, as the // VFP register classes have the enum sorted properly. // // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. - if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { + else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { if (!Spacing) Spacing = 1; // Register range implies a single spaced list. else if (Spacing == 2) { @@ -4495,7 +4831,7 @@ case NoLanes: // Two-register operands have been converted to the // composite register classes. - if (Count == 2) { + if (Count == 2 && !hasMVE()) { const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; @@ -4507,7 +4843,7 @@ case AllLanes: // Two-register operands have been converted to the // composite register classes. - if (Count == 2) { + if (Count == 2 && !hasMVE()) { const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; @@ -5632,6 +5968,8 @@ St = ARM_AM::ror; else if (ShiftName == "rrx" || ShiftName == "RRX") St = ARM_AM::rrx; + else if (ShiftName == "uxtw" || ShiftName == "UXTW") + St= ARM_AM::uxtw; else return Error(Loc, "illegal shift operator"); Parser.Lex(); // Eat shift type token. @@ -6155,7 +6493,10 @@ Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" || Mnemonic == "csetm" || - Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst")) { + Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") || + (hasMVE() && + (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") || + Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) { // These mnemonics are never predicable CanAcceptPredicationCode = false; } else if (!isThumb()) { @@ -6413,6 +6754,10 @@ if (!hasMVE() || Operands.size() < 3) return true; + if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") || + Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4")) + return true; + if (Mnemonic.startswith("vctp")) return false; @@ -6486,7 +6831,7 @@ if (!Op2.isReg()) return; - if (!Op3.isMem()) + if (!Op3.isGPRMem()) return; const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); @@ -7259,6 +7604,63 @@ "destination register and base register can't be identical"); return false; } + + case ARM::MVE_VLDRBU8noShift: + case ARM::MVE_VLDRBU16noShift: + case ARM::MVE_VLDRBS16noShift: + case ARM::MVE_VLDRBU32noShift: + case ARM::MVE_VLDRBS32noShift: + case ARM::MVE_VLDRHU16Shift: + case ARM::MVE_VLDRHU16noShift: + case ARM::MVE_VLDRHU32Shift: + case ARM::MVE_VLDRHU32noShift: + case ARM::MVE_VLDRHS32Shift: + case ARM::MVE_VLDRHS32noShift: + case ARM::MVE_VLDRWU32Shift: + case ARM::MVE_VLDRWU32noShift: + case ARM::MVE_VLDRDU64Shift: + case ARM::MVE_VLDRDU64noShift: { + // Qd must be different from Qm. + const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + + if (Qd == Qm) { + return Error(Operands[3]->getStartLoc(), + "destination vector register and vector offset register " + "can't be identical"); + } + return false; + } + + case ARM::MVE_VLDRWU32NoWriteBack: + case ARM::MVE_VLDRDU64NoWriteBack: { + // Qd must be different from Qm. + const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(0).getReg()); + const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + + if (Qd == Qm) { + return Error(Operands[3]->getStartLoc(), + "destination vector register and vector pointer register " + "can't be identical"); + } + return false; + } + + case ARM::MVE_VLDRWU32WriteBack: + case ARM::MVE_VLDRDU64WriteBack: { + // Qd must be different from Qm. + // NOTE: The first operand is a junk writeback operand that isn't used. + const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); + + if (Qd == Qm) { + return Error(Operands[3]->getStartLoc(), + "destination vector register and vector pointer register " + "can't be identical"); + } + return false; + } + case ARM::SBFX: case ARM::t2SBFX: case ARM::UBFX: diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -208,6 +208,8 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, @@ -228,6 +230,10 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, @@ -336,6 +342,11 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, @@ -432,8 +443,17 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, @@ -519,6 +539,15 @@ static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); +template +static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); @@ -1243,6 +1272,17 @@ return S; } +static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + if (RegNo == 13 || RegNo == 15) + Check(S, MCDisassembler::SoftFail); + + Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + static const uint16_t SPRDecoderTable[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, @@ -4145,6 +4185,21 @@ return MCDisassembler::Success; } +template +static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + int imm = Val & 0x7F; + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x80)) + imm *= -1; + if (imm != INT32_MIN) + imm <<= shift; + Inst.addOperand(MCOperand::createImm(imm)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; @@ -4191,6 +4246,43 @@ return S; } +template +static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, + uint64_t Address, + const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction(Val, 8, 3); + unsigned imm = + fieldFromInstruction(Val, 0, 8); + + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +template +static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, + uint64_t Address, + const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Rn = fieldFromInstruction(Val, 8, 4); + unsigned imm = fieldFromInstruction(Val, 0, 8); + if (WriteBack) { + if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; @@ -4338,6 +4430,43 @@ return S; } +static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Rn = fieldFromInstruction(Insn, 3, 4); + unsigned Qm = fieldFromInstruction(Insn, 0, 3); + + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +template +static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + unsigned Qm = fieldFromInstruction(Insn, 8, 3); + int imm = fieldFromInstruction(Insn, 0, 7); + + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler::Fail; + + if(!fieldFromInstruction(Insn, 7, 1)) { + if (imm == 0) + imm = INT32_MIN; // indicate -0 + else + imm *= -1; + } + if (imm != INT32_MIN) + imm <<= shift; + Inst.addOperand(MCOperand::createImm(imm)); + + return S; +} + static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { // Val is passed in as S:J1:J2:imm10H:imm10L:'0' @@ -5940,6 +6069,38 @@ return MCDisassembler::Success; } +static const uint16_t QQPRDecoderTable[] = { + ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, + ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 +}; + +static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 6) + return MCDisassembler::Fail; + + unsigned Register = QQPRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Register)); + return MCDisassembler::Success; +} + +static const uint16_t QQQQPRDecoderTable[] = { + ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, + ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 +}; + +static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 4) + return MCDisassembler::Fail; + + unsigned Register = QQQQPRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Register)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { @@ -6163,6 +6324,66 @@ return S; } +template +static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned Rn = fieldFromInstruction(Val, 16, 3); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeTAddrModeImm7(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +template +static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned Rn = fieldFromInstruction(Val, 16, 4); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeT2AddrModeImm7(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +template +static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned Qm = fieldFromInstruction(Val, 17, 3); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Qm << 8); + + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeMveAddrModeQ(Inst, addr, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h @@ -30,7 +30,8 @@ lsl, lsr, ror, - rrx + rrx, + uxtw }; enum AddrOpc { @@ -48,6 +49,7 @@ case ARM_AM::lsr: return "lsr"; case ARM_AM::ror: return "ror"; case ARM_AM::rrx: return "rrx"; + case ARM_AM::uxtw: return "uxtw"; } } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h @@ -202,6 +202,9 @@ AddrMode_i12 = 16, AddrMode5FP16 = 17, // i8 * 2 AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst + AddrModeT2_i7s4 = 19, // i7 * 4 + AddrModeT2_i7s2 = 20, // i7 * 2 + AddrModeT2_i7 = 21, // i7 * 1 }; inline static const char *AddrModeToString(AddrMode addrmode) { @@ -225,6 +228,9 @@ case AddrModeT2_i8s4: return "AddrModeT2_i8s4"; case AddrMode_i12: return "AddrMode_i12"; case AddrModeT2_ldrex:return "AddrModeT2_ldrex"; + case AddrModeT2_i7s4: return "AddrModeT2_i7s4"; + case AddrModeT2_i7s2: return "AddrModeT2_i7s2"; + case AddrModeT2_i7: return "AddrModeT2_i7"; } } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -218,6 +218,10 @@ const MCSubtargetInfo &STI, raw_ostream &O); void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); + void printMVEVectorListTwoQ(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printMVEVectorListFourQ(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); void printVectorListFour(const MCInst *MI, unsigned OpNum, @@ -252,6 +256,11 @@ raw_ostream &O); void printVPTMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); + template + void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); + void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, raw_ostream &O); void printExpandedImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -603,6 +603,40 @@ << markup(">"); } +template +void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO1 = MI->getOperand(OpNum); + const MCOperand &MO2 = MI->getOperand(OpNum + 1); + + O << markup(" 0) + printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup); + + O << "]" << markup(">"); +} + +void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO1 = MI->getOperand(OpNum); + const MCOperand &MO2 = MI->getOperand(OpNum + 1); + + O << markup(""); + + O << "]" << markup(">"); +} + void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -1424,6 +1458,44 @@ O << "}"; } +void ARMInstPrinter::printMVEVectorListTwoQ(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + // MVE vector lists are always written as a list of q-registers, + // never d-registers. getSubReg will give us the four d-regs making + // up a QQPR, so we take every other one of those and find its + // super-reg in the MQPR class in order to get the list of q-regs to + // print. + auto MQPR = &MRI.getRegClass(ARM::MQPRRegClassID); + unsigned Reg = MI->getOperand(OpNum).getReg(); + const char *Prefix = "{"; + for (auto SubIdx: {ARM::dsub_0, ARM::dsub_2}) { + unsigned SubReg = MRI.getMatchingSuperReg(MRI.getSubReg(Reg, SubIdx), + ARM::dsub_0, MQPR); + O << Prefix; + printRegName(O, SubReg); + Prefix = ", "; + } + O << "}"; +} + +void ARMInstPrinter::printMVEVectorListFourQ(const MCInst *MI, unsigned OpNum, + const MCSubtargetInfo &STI, + raw_ostream &O) { + // Same as printMVEVectorListTwoQ but with four q-registers. + auto MQPR = &MRI.getRegClass(ARM::MQPRRegClassID); + unsigned Reg = MI->getOperand(OpNum).getReg(); + const char *Prefix = "{"; + for (auto SubIdx: {ARM::dsub_0, ARM::dsub_2, ARM::dsub_4, ARM::dsub_6}) { + unsigned SubReg = MRI.getMatchingSuperReg(MRI.getSubReg(Reg, SubIdx), + ARM::dsub_0, MQPR); + O << Prefix; + printRegName(O, SubReg); + Prefix = ", "; + } + O << "}"; +} + void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -204,6 +204,19 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' + /// operand. + uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}' + /// operand. + template + uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' /// operand as needed by load/store instructions. uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, @@ -234,8 +247,10 @@ case ARM_AM::asr: return 2; case ARM_AM::ror: case ARM_AM::rrx: return 3; + case ARM_AM::uxtw: + default: + llvm_unreachable("Invalid ShiftOpc!"); } - llvm_unreachable("Invalid ShiftOpc!"); } /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. @@ -334,7 +349,8 @@ unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, + template + unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, @@ -1015,6 +1031,58 @@ Binary |= (1U << Bits); return Binary; } + +/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' +/// operand. +uint32_t ARMMCCodeEmitter:: +getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // {6-3} Rn + // {2-0} Qm + const MCOperand &M0 = MI.getOperand(OpIdx); + const MCOperand &M1 = MI.getOperand(OpIdx + 1); + + unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); + unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); + + assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); + + return (Rn << 3) | Qm; +} + +/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' +/// operand. +template +uint32_t ARMMCCodeEmitter:: +getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // {10-8} Qm + // {7-0} Imm + const MCOperand &M0 = MI.getOperand(OpIdx); + const MCOperand &M1 = MI.getOperand(OpIdx + 1); + + unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); + int32_t Imm = M1.getImm(); + + bool isAdd = Imm >= 0; + + Imm >>= shift; + + if (!isAdd) + Imm = -(uint32_t)Imm; + + Imm &= 0x7f; + + if (isAdd) + Imm |= 0x80; + + assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); + + return (Qm << 8) | Imm; +} + /// getT2AddrModeImm8s4OpValue - Return encoding info for /// 'reg +/- imm8<<2' operand. uint32_t ARMMCCodeEmitter:: @@ -1515,25 +1583,26 @@ return Value; } +template unsigned ARMMCCodeEmitter:: -getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { +getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO2 = MI.getOperand(OpNum+1); // FIXME: Needs fixup support. unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); - // Even though the immediate is 8 bits long, we need 9 bits in order + // If the immediate is B bits long, we need B+1 bits in order // to represent the (inverse of the) sign bit. - Value <<= 9; - int32_t tmp = (int32_t)MO2.getImm(); + Value <<= (Bits + 1); + int32_t tmp = (int32_t)MO2.getImm() >> Shift; if (tmp < 0) tmp = abs(tmp); else - Value |= 256; // Set the ADD bit - Value |= tmp & 255; + Value |= (1U << Bits); // Set the ADD bit + Value |= tmp & ((1U << Bits) - 1); return Value; } diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -610,9 +610,22 @@ Offset = -Offset; isSub = true; } + } else if (AddrMode == ARMII::AddrModeT2_i7s4 || + AddrMode == ARMII::AddrModeT2_i7s2 || + AddrMode == ARMII::AddrModeT2_i7) { + Offset += MI.getOperand(FrameRegIdx + 1).getImm(); + NumBits = 7; + unsigned OffsetMask = 0x0; + switch (AddrMode) { + case ARMII::AddrModeT2_i7s4: NumBits += 2; OffsetMask = 0x3; break; + case ARMII::AddrModeT2_i7s2: NumBits += 1; OffsetMask = 0x1; break; + } + // MCInst operand expects already scaled value. + Scale = 1; + assert((Offset & OffsetMask) == 0 && "Can't encode this offset!"); } else if (AddrMode == ARMII::AddrModeT2_i8s4) { Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4; - NumBits = 10; // 8 bits scaled by 4 + NumBits = 8 + 2; // MCInst operand expects already scaled value. Scale = 1; assert((Offset & 3) == 0 && "Can't encode this offset!"); diff --git a/llvm/test/MC/ARM/mve-load-store.s b/llvm/test/MC/ARM/mve-load-store.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/ARM/mve-load-store.s @@ -0,0 +1,2254 @@ +# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \ +# RUN: | FileCheck --check-prefix=CHECK-NOFP %s +# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \ +# RUN: | FileCheck --check-prefix=CHECK %s +# RUN: FileCheck --check-prefix=ERROR < %t %s + +# CHECK: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e] +# CHECK-NOFP: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e] +vld20.8 {q0, q1}, [sp] + +# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e] +# CHECK-NOFP: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e] +vld20.8 {q0, q1}, [r0] + +# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e] +# CHECK-NOFP: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e] +vld20.8 {q0, q1}, [r0]! + +# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e] +# CHECK-NOFP: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e] +vld20.8 {q0, q1}, [r11] + +# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe] +# CHECK-NOFP: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe] +vld20.8 {q5, q6}, [r0]! + +# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e] +# CHECK-NOFP: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e] +vld21.8 {q0, q1}, [r0] + +# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e] +# CHECK-NOFP: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e] +vld21.8 {q3, q4}, [r0]! + +# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e] +# CHECK-NOFP: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e] +vld20.16 {q0, q1}, [r0] + +# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e] +# CHECK-NOFP: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e] +vld20.16 {q0, q1}, [r0]! + +# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e] +# CHECK-NOFP: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e] +vld20.16 {q0, q1}, [r11] + +# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe] +# CHECK-NOFP: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe] +vld20.16 {q5, q6}, [r0]! + +# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e] +# CHECK-NOFP: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e] +vld21.16 {q0, q1}, [r0] + +# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e] +# CHECK-NOFP: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e] +vld21.16 {q3, q4}, [r0]! + +# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f] +# CHECK-NOFP: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f] +vld20.32 {q0, q1}, [r0] + +# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f] +# CHECK-NOFP: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f] +vld20.32 {q0, q1}, [r0]! + +# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f] +# CHECK-NOFP: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f] +vld20.32 {q0, q1}, [r11] + +# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf] +# CHECK-NOFP: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf] +vld20.32 {q5, q6}, [r0]! + +# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f] +# CHECK-NOFP: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f] +vld21.32 {q0, q1}, [r0] + +# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f] +# CHECK-NOFP: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f] +vld21.32 {q3, q4}, [r0]! + +# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e] +# CHECK-NOFP: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e] +vst20.8 {q0, q1}, [r0] + +# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e] +# CHECK-NOFP: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e] +vst20.8 {q0, q1}, [r0]! + +# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e] +# CHECK-NOFP: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e] +vst20.8 {q0, q1}, [r11] + +# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe] +# CHECK-NOFP: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe] +vst20.8 {q5, q6}, [r0]! + +# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e] +# CHECK-NOFP: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e] +vst21.8 {q0, q1}, [r0] + +# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e] +# CHECK-NOFP: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e] +vst21.8 {q3, q4}, [r0]! + +# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e] +# CHECK-NOFP: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e] +vst20.16 {q0, q1}, [r0] + +# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e] +# CHECK-NOFP: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e] +vst20.16 {q0, q1}, [r0]! + +# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e] +# CHECK-NOFP: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e] +vst20.16 {q0, q1}, [r11] + +# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe] +# CHECK-NOFP: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe] +vst20.16 {q5, q6}, [r0]! + +# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e] +# CHECK-NOFP: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e] +vst21.16 {q0, q1}, [r0] + +# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e] +# CHECK-NOFP: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e] +vst21.16 {q3, q4}, [r0]! + +# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f] +# CHECK-NOFP: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f] +vst20.32 {q0, q1}, [r0] + +# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f] +# CHECK-NOFP: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f] +vst20.32 {q0, q1}, [r0]! + +# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f] +# CHECK-NOFP: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f] +vst20.32 {q0, q1}, [r11] + +# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf] +# CHECK-NOFP: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf] +vst20.32 {q5, q6}, [r0]! + +# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f] +# CHECK-NOFP: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f] +vst21.32 {q0, q1}, [r0] + +# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f] +# CHECK-NOFP: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f] +vst21.32 {q3, q4}, [r0]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.8 {q0, q1}, [sp]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.64 {q0, q1}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range +vld20.32 {q0, q2}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.32 {q0, q1, q2}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.32 {q0}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction +vld20.32 q0, q1, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected +vld20.32 {q7, q8}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected +vld20.32 {d0, d1}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction +vld22.32 {q0, q1}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.32 {q0, q1}, [pc] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld20.32 {q0, q1}, [r0, #4] + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e] +# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e] +vld40.8 {q0, q1, q2, q3}, [r0] + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e] +# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e] +vld40.8 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e] +# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e] +vld40.8 {q0, q1, q2, q3}, [r11] + +# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e] +# CHECK-NOFP: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e] +vld40.8 {q3, q4, q5, q6}, [r0]! + +# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e] +# CHECK-NOFP: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e] +vld41.8 {q0, q1, q2, q3}, [r0] + +# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e] +# CHECK-NOFP: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e] +vld41.8 {q4, q5, q6, q7}, [r0]! + +# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e] +# CHECK-NOFP: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e] +vld42.8 {q0, q1, q2, q3}, [r0] + +# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e] +# CHECK-NOFP: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e] +vld42.8 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e] +# CHECK-NOFP: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e] +vld43.8 {q0, q1, q2, q3}, [r0] + +# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e] +# CHECK-NOFP: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e] +vld43.8 {q4, q5, q6, q7}, [r0]! + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e] +# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e] +vld40.16 {q0, q1, q2, q3}, [r0] + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e] +# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e] +vld40.16 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e] +# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e] +vld40.16 {q0, q1, q2, q3}, [r11] + +# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e] +# CHECK-NOFP: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e] +vld40.16 {q3, q4, q5, q6}, [r0]! + +# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e] +# CHECK-NOFP: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e] +vld41.16 {q0, q1, q2, q3}, [r0] + +# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e] +# CHECK-NOFP: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e] +vld41.16 {q4, q5, q6, q7}, [r0]! + +# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e] +# CHECK-NOFP: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e] +vld42.16 {q0, q1, q2, q3}, [r0] + +# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e] +# CHECK-NOFP: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e] +vld42.16 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e] +# CHECK-NOFP: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e] +vld43.16 {q0, q1, q2, q3}, [r0] + +# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e] +# CHECK-NOFP: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e] +vld43.16 {q4, q5, q6, q7}, [r0]! + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f] +# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f] +vld40.32 {q0, q1, q2, q3}, [r0] + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f] +# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f] +vld40.32 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f] +# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f] +vld40.32 {q0, q1, q2, q3}, [r11] + +# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f] +# CHECK-NOFP: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f] +vld40.32 {q3, q4, q5, q6}, [r0]! + +# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f] +# CHECK-NOFP: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f] +vld41.32 {q0, q1, q2, q3}, [r0] + +# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f] +# CHECK-NOFP: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f] +vld41.32 {q4, q5, q6, q7}, [r0]! + +# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f] +# CHECK-NOFP: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f] +vld42.32 {q0, q1, q2, q3}, [r0] + +# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f] +# CHECK-NOFP: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f] +vld42.32 {q0, q1, q2, q3}, [r0]! + +# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f] +# CHECK-NOFP: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f] +vld43.32 {q0, q1, q2, q3}, [r0] + +# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f] +# CHECK-NOFP: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f] +vld43.32 {q4, q5, q6, q7}, [r0]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.64 {q0, q1, q2, q3}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range +vld40.32 {q0, q2, q3, q4}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.32 {q0, q1, q2, q3, q4}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.32 {q0, q1}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.32 {q0, q1, q2}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction +vld40.32 q0, q1, q2, q3, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected +vld40.32 {q5, q6, q7, q8}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected +vld40.32 {d0, d1, d2, d3}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction +vld44.32 {q0, q1, q2, q3}, [r0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.32 {q0, q1, q2, q3}, [pc] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vld40.32 {q0, q1, q2, q3}, [r0, #4] + +# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +vldrb.u8 q0, [r0] + +# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e] +# CHECK-NOFP: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e] +vldrb.u8 q1, [r0] + +# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e] +vldrb.u8 q0, [r11] + +# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e] +# CHECK-NOFP: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e] +vldrb.u8 q3, [r11] + +# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e] +vldrb.u8 q0, [r4, #56] + +# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e] +# CHECK-NOFP: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e] +vldrb.u8 q4, [r4, #56] + +# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +vldrb.u8 q0, [r8, #56] + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +vldrb.u8 q5, [r4, #56]! + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +vldrb.u8 q5, [r4, #56]! + +# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe] +vldrb.u8 q5, [r4], #-25 + +# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe] +vldrb.u8 q5, [r10], #-25 + +# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe] +vldrb.u8 q5, [sp, #-25] + +# CHECK: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe] +vldrb.u8 q5, [sp, #-127] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrb.u8 q0, [r0, #128] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrb.u8 q0, [r0, #-128]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrb.u8 q0, [r0], #128 + +# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +vstrb.8 q0, [r0] + +# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e] +# CHECK-NOFP: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e] +vstrb.8 q1, [r0] + +# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e] +vstrb.8 q0, [r11] + +# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e] +# CHECK-NOFP: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e] +vstrb.8 q3, [r11] + +# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e] +vstrb.8 q0, [r4, #56] + +# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +vstrb.8 q4, [r4, #56] + +# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e] +vstrb.8 q0, [r8, #56] + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +vstrb.8 q5, [r4, #56]! + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +vstrb.8 q5, [r4, #56]! + +# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe] +vstrb.8 q5, [r4], #-25 + +# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe] +vstrb.8 q5, [r10], #-25 + +# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe] +# CHECK-NOFP: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe] +vstrb.8 q5, [sp, #-25] + +# CHECK: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe] +# CHECK-NOFP: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe] +vstrb.8 q5, [sp, #127] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrb.u8 q0, [r0, #128] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrb.u8 q0, [r0, #-128]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrb.u8 q0, [r0], #128 + +# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e] +# CHECK-NOFP: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e] +vldrb.u16 q0, [r0] + +# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e] +# CHECK-NOFP: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e] +vldrb.u16 q1, [r0] + +# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e] +# CHECK-NOFP: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e] +vldrb.u16 q0, [r7] + +# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e] +# CHECK-NOFP: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e] +vldrb.u16 q3, [r7] + +# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e] +# CHECK-NOFP: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e] +vldrb.u16 q0, [r4, #56] + +# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e] +# CHECK-NOFP: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e] +vldrb.u16 q4, [r4, #56] + +# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e] +# CHECK-NOFP: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e] +vldrb.u16 q0, [r2, #56] + +# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +vldrb.u16 q5, [r4, #56]! + +# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +vldrb.u16 q5, [r4, #56]! + +# CHECK: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae] +vldrb.u16 q5, [r4], #-1 + +# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae] +vldrb.u16 q5, [r3], #-25 + +# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae] +vldrb.u16 q5, [r6, #-25] + +# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae] +# CHECK-NOFP: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae] +vldrb.u16 q5, [r6, #-64] + +# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e] +# CHECK-NOFP: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e] +vldrb.s16 q0, [r0] + +# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e] +# CHECK-NOFP: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e] +vldrb.s16 q1, [r0] + +# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e] +# CHECK-NOFP: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e] +vldrb.s16 q0, [r7] + +# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e] +# CHECK-NOFP: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e] +vldrb.s16 q3, [r7] + +# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e] +# CHECK-NOFP: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e] +vldrb.s16 q0, [r4, #56] + +# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e] +# CHECK-NOFP: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e] +vldrb.s16 q4, [r4, #56] + +# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e] +# CHECK-NOFP: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e] +vldrb.s16 q0, [r2, #56] + +# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +vldrb.s16 q5, [r4, #56]! + +# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +vldrb.s16 q5, [r4, #56]! + +# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae] +vldrb.s16 q5, [r4], #-25 + +# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae] +vldrb.s16 q5, [r3], #-25 + +# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae] +vldrb.s16 q5, [r6, #-25] + +# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae] +# CHECK-NOFP: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae] +vldrb.s16 q5, [r6, #-64] + +# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e] +# CHECK-NOFP: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e] +vstrb.16 q0, [r0] + +# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e] +# CHECK-NOFP: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e] +vstrb.16 q1, [r0] + +# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e] +# CHECK-NOFP: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e] +vstrb.16 q0, [r7] + +# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e] +# CHECK-NOFP: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e] +vstrb.16 q3, [r7] + +# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e] +# CHECK-NOFP: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e] +vstrb.16 q0, [r4, #56] + +# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e] +# CHECK-NOFP: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e] +vstrb.16 q4, [r4, #56] + +# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e] +# CHECK-NOFP: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e] +vstrb.16 q0, [r5, #56] + +# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +# CHECK-NOFP: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +vstrb.16 q5, [r4, #56]! + +# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +# CHECK-NOFP: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +vstrb.16 q5, [r4, #56]! + +# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae] +# CHECK-NOFP: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae] +vstrb.16 q5, [r4], #-25 + +# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae] +# CHECK-NOFP: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae] +vstrb.16 q5, [r3], #-25 + +# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae] +# CHECK-NOFP: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae] +vstrb.16 q5, [r2, #-25] + +# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae] +# CHECK-NOFP: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae] +vstrb.16 q5, [r2, #-64] + +# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f] +# CHECK-NOFP: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f] +vldrb.u32 q0, [r0] + +# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f] +# CHECK-NOFP: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f] +vldrb.u32 q1, [r0] + +# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f] +# CHECK-NOFP: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f] +vldrb.u32 q0, [r7] + +# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f] +# CHECK-NOFP: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f] +vldrb.u32 q3, [r7] + +# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f] +# CHECK-NOFP: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f] +vldrb.u32 q0, [r4, #56] + +# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f] +# CHECK-NOFP: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f] +vldrb.u32 q4, [r4, #56] + +# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f] +# CHECK-NOFP: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f] +vldrb.u32 q0, [r2, #56] + +# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +vldrb.u32 q5, [r4, #56]! + +# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +vldrb.u32 q5, [r4, #56]! + +# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf] +vldrb.u32 q5, [r4], #-25 + +# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf] +vldrb.u32 q5, [r3], #-25 + +# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf] +vldrb.u32 q5, [r6, #-25] + +# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf] +# CHECK-NOFP: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf] +vldrb.u32 q5, [r6, #-64] + +# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f] +# CHECK-NOFP: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f] +vldrb.s32 q0, [r0] + +# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f] +# CHECK-NOFP: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f] +vldrb.s32 q1, [r0] + +# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f] +# CHECK-NOFP: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f] +vldrb.s32 q0, [r7] + +# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f] +# CHECK-NOFP: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f] +vldrb.s32 q3, [r7] + +# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f] +# CHECK-NOFP: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f] +vldrb.s32 q0, [r4, #56] + +# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f] +# CHECK-NOFP: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f] +vldrb.s32 q4, [r4, #56] + +# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f] +# CHECK-NOFP: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f] +vldrb.s32 q0, [r2, #56] + +# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +vldrb.s32 q5, [r4, #56]! + +# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +vldrb.s32 q5, [r4, #56]! + +# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf] +vldrb.s32 q5, [r4], #-25 + +# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf] +vldrb.s32 q5, [r3], #-25 + +# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf] +vldrb.s32 q5, [r6, #-25] + +# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf] +# CHECK-NOFP: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf] +vldrb.s32 q5, [r6, #-64] + +# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f] +# CHECK-NOFP: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f] +vstrb.32 q0, [r0] + +# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f] +# CHECK-NOFP: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f] +vstrb.32 q1, [r0] + +# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f] +# CHECK-NOFP: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f] +vstrb.32 q0, [r7] + +# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f] +# CHECK-NOFP: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f] +vstrb.32 q3, [r7] + +# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f] +# CHECK-NOFP: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f] +vstrb.32 q0, [r4, #56] + +# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f] +# CHECK-NOFP: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f] +vstrb.32 q4, [r4, #56] + +# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f] +# CHECK-NOFP: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f] +vstrb.32 q0, [r5, #56] + +# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +vstrb.32 q5, [r4, #56]! + +# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +vstrb.32 q5, [r4, #56]! + +# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf] +vstrb.32 q5, [r4], #-25 + +# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf] +vstrb.32 q5, [r3], #-25 + +# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf] +vstrb.32 q5, [r2, #-25] + +# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf] +# CHECK-NOFP: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf] +vstrb.32 q5, [r2, #-64] + +# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +vldrh.u16 q0, [r0] + +# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e] +# CHECK-NOFP: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e] +vldrh.u16 q1, [r0] + +# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e] +vldrh.u16 q0, [r11] + +# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e] +# CHECK-NOFP: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e] +vldrh.u16 q3, [r11] + +# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +vldrh.u16 q0, [r4, #56] + +# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e] +# CHECK-NOFP: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e] +vldrh.u16 q4, [r4, #56] + +# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e] +vldrh.u16 q0, [r8, #56] + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +vldrh.u16 q5, [r4, #56]! + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +vldrh.u16 q5, [r4, #56]! + +# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe] +vldrh.u16 q5, [r4], #-26 + +# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe] +vldrh.u16 q5, [r10], #-26 + +# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe] +vldrh.u16 q5, [sp, #-26] + +# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe] +vldrh.u16 q5, [sp, #-64] + +# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe] +vldrh.u16 q5, [sp, #-254] + +# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe] +vldrh.u16 q5, [r10], #254 + +# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +vstrh.16 q0, [r0] + +# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e] +# CHECK-NOFP: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e] +vstrh.16 q1, [r0] + +# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e] +vstrh.16 q0, [r11] + +# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e] +# CHECK-NOFP: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e] +vstrh.16 q3, [r11] + +# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +vstrh.16 q0, [r4, #56] + +# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e] +# CHECK-NOFP: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e] +vstrh.16 q4, [r4, #56] + +# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e] +vstrh.16 q0, [r8, #56] + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +vstrh.16 q5, [r4, #56]! + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +vstrh.16 q5, [r4, #56]! + +# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe] +vstrh.16 q5, [r4], #-26 + +# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe] +vstrh.16 q5, [r10], #-26 + +# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe] +# CHECK-NOFP: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe] +vstrh.16 q5, [sp, #-26] + +# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe] +# CHECK-NOFP: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe] +vstrh.16 q5, [sp, #-64] + +# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe] +# CHECK-NOFP: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe] +vstrh.16 q5, [sp, #-254] + +# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe] +vstrh.16 q5, [r10], #254 + +# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f] +# CHECK-NOFP: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f] +vldrh.u32 q0, [r0] + +# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f] +# CHECK-NOFP: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f] +vldrh.u32 q1, [r0] + +# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f] +# CHECK-NOFP: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f] +vldrh.u32 q0, [r7] + +# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f] +# CHECK-NOFP: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f] +vldrh.u32 q3, [r7] + +# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f] +# CHECK-NOFP: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f] +vldrh.u32 q0, [r4, #56] + +# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f] +# CHECK-NOFP: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f] +vldrh.u32 q4, [r4, #56] + +# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f] +# CHECK-NOFP: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f] +vldrh.u32 q0, [r2, #56] + +# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +vldrh.u32 q5, [r4, #56]! + +# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +vldrh.u32 q5, [r4, #56]! + +# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf] +vldrh.u32 q5, [r4], #-26 + +# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf] +vldrh.u32 q5, [r3], #-26 + +# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf] +vldrh.u32 q5, [r6, #-26] + +# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf] +vldrh.u32 q5, [r6, #-64] + +# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf] +vldrh.u32 q5, [r6, #-254] + +# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf] +# CHECK-NOFP: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf] +vldrh.u32 q5, [r4, #254]! + +# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f] +# CHECK-NOFP: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f] +vldrh.s32 q0, [r0] + +# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f] +# CHECK-NOFP: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f] +vldrh.s32 q1, [r0] + +# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f] +# CHECK-NOFP: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f] +vldrh.s32 q0, [r7] + +# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f] +# CHECK-NOFP: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f] +vldrh.s32 q3, [r7] + +# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f] +# CHECK-NOFP: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f] +vldrh.s32 q0, [r4, #56] + +# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f] +# CHECK-NOFP: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f] +vldrh.s32 q4, [r4, #56] + +# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f] +# CHECK-NOFP: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f] +vldrh.s32 q0, [r2, #56] + +# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +vldrh.s32 q5, [r4, #56]! + +# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +vldrh.s32 q5, [r4, #56]! + +# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf] +vldrh.s32 q5, [r4], #-26 + +# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf] +vldrh.s32 q5, [r3], #-26 + +# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf] +vldrh.s32 q5, [r6, #-26] + +# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf] +vldrh.s32 q5, [r6, #-64] + +# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf] +vldrh.s32 q5, [r6, #-254] + +# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf] +# CHECK-NOFP: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf] +vldrh.s32 q5, [r4, #254]! + +# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f] +# CHECK-NOFP: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f] +vstrh.32 q0, [r0] + +# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f] +# CHECK-NOFP: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f] +vstrh.32 q1, [r0] + +# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f] +# CHECK-NOFP: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f] +vstrh.32 q0, [r7] + +# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f] +# CHECK-NOFP: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f] +vstrh.32 q3, [r7] + +# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f] +# CHECK-NOFP: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f] +vstrh.32 q0, [r4, #56] + +# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f] +# CHECK-NOFP: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f] +vstrh.32 q4, [r4, #56] + +# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f] +# CHECK-NOFP: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f] +vstrh.32 q0, [r5, #56] + +# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +vstrh.32 q5, [r4, #56]! + +# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +vstrh.32 q5, [r4, #56]! + +# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf] +vstrh.32 q5, [r4], #-26 + +# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf] +vstrh.32 q5, [r3], #-26 + +# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf] +vstrh.32 q5, [r2, #-26] + +# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf] +vstrh.32 q5, [r2, #-64] + +# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf] +vstrh.32 q5, [r2, #-254] + +# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf] +# CHECK-NOFP: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf] +vstrh.32 q5, [r4, #254]! + +# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +vldrw.u32 q0, [r0] + +# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f] +# CHECK-NOFP: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f] +vldrw.u32 q1, [r0] + +# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f] +vldrw.u32 q0, [r11] + +# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f] +# CHECK-NOFP: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f] +vldrw.u32 q3, [r11] + +# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +vldrw.u32 q0, [r4, #56] + +# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f] +# CHECK-NOFP: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f] +vldrw.u32 q4, [r4, #56] + +# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f] +vldrw.u32 q0, [r8, #56] + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +vldrw.u32 q5, [r4, #56]! + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +vldrw.u32 q5, [r4, #56]! + +# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf] +vldrw.u32 q5, [r4], #-28 + +# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf] +vldrw.u32 q5, [r10], #-28 + +# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf] +vldrw.u32 q5, [sp, #-28] + +# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf] +vldrw.u32 q5, [sp, #-64] + +# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf] +vldrw.u32 q5, [sp, #-508] + +# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf] +vldrw.u32 q5, [r4, #508]! + +# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +vstrw.32 q0, [r0] + +# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f] +# CHECK-NOFP: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f] +vstrw.32 q1, [r0] + +# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f] +vstrw.32 q0, [r11] + +# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f] +# CHECK-NOFP: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f] +vstrw.32 q3, [r11] + +# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +vstrw.32 q0, [r4, #56] + +# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f] +# CHECK-NOFP: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f] +vstrw.32 q4, [r4, #56] + +# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f] +vstrw.32 q0, [r8, #56] + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +vstrw.32 q5, [r4, #56]! + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +vstrw.32 q5, [r4, #56]! + +# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf] +vstrw.32 q5, [r4], #-28 + +# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf] +vstrw.32 q5, [r10], #-28 + +# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf] +# CHECK-NOFP: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf] +vstrw.32 q5, [sp, #-28] + +# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf] +# CHECK-NOFP: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf] +vstrw.32 q5, [sp, #-64] + +# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf] +# CHECK-NOFP: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf] +vstrw.32 q5, [sp, #-508] + +# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf] +vstrw.32 q5, [r4, #508]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrb.16 q0, [r8] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrh.u32 q0, [r8] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrw.32 q5, [sp, #-64]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrw.32 q5, [sp, #-3] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrw.32 q5, [sp, #512] + +# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +vldrb.u8 q0, [r0, q1] + +# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e] +# CHECK-NOFP: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e] +vldrb.u8 q3, [r10, q1] + +# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e] +# CHECK-NOFP: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e] +vldrb.u16 q0, [r0, q1] + +# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e] +# CHECK-NOFP: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e] +vldrb.u16 q3, [r9, q1] + +# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e] +# CHECK-NOFP: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e] +vldrb.s16 q0, [r0, q1] + +# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e] +# CHECK-NOFP: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e] +vldrb.s16 q3, [sp, q1] + +# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f] +# CHECK-NOFP: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f] +vldrb.u32 q0, [r0, q1] + +# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f] +# CHECK-NOFP: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f] +vldrb.u32 q3, [r0, q1] + +# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f] +# CHECK-NOFP: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f] +vldrb.s32 q0, [r0, q1] + +# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f] +# CHECK-NOFP: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f] +vldrb.s32 q3, [r0, q1] + +# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e] +# CHECK-NOFP: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e] +vldrh.u16 q0, [r0, q1] + +# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +vldrh.u16 q3, [r0, q1] + +# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f] +# CHECK-NOFP: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f] +vldrh.u32 q0, [r0, q1] + +# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f] +# CHECK-NOFP: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f] +vldrh.u32 q3, [r0, q1] + +# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f] +# CHECK-NOFP: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f] +vldrh.s32 q0, [r0, q1] + +# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f] +# CHECK-NOFP: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f] +vldrh.s32 q3, [r0, q1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrb.u8 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrb.u16 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrb.s16 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrb.u32 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrb.s32 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.u16 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.u32 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.s32 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.u16 q0, [r0, q0, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.u32 q0, [r0, q0, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrh.s32 q0, [r0, q0, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrw.u32 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrw.u32 q0, [r0, q0, uxtw #2] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrd.u64 q0, [r0, q0] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical +vldrd.u64 q0, [r0, q0, uxtw #3] + +# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +vldrh.u16 q0, [r0, q1, uxtw #1] + +# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +vldrw.u32 q0, [r0, q1] + +# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f] +# CHECK-NOFP: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f] +vldrw.u32 q3, [r0, q1] + +# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +vldrw.u32 q0, [r0, q1, uxtw #2] + +# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f] +vldrw.u32 q0, [sp, q1, uxtw #2] + +# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +vldrd.u64 q0, [r0, q1] + +# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f] +# CHECK-NOFP: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f] +vldrd.u64 q3, [r0, q1] + +# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +vldrd.u64 q0, [r0, q1, uxtw #3] + +# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f] +vldrd.u64 q0, [sp, q1, uxtw #3] + +# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +vstrb.8 q0, [r0, q1] + +# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e] +# CHECK-NOFP: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e] +vstrb.8 q3, [r10, q1] + +# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e] +# CHECK-NOFP: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e] +vstrb.8 q3, [r0, q3] + +# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e] +# CHECK-NOFP: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e] +vstrb.16 q0, [r0, q1] + +# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e] +# CHECK-NOFP: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e] +vstrb.16 q3, [sp, q1] + +# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e] +# CHECK-NOFP: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e] +vstrb.16 q3, [r0, q3] + +# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f] +# CHECK-NOFP: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f] +vstrb.32 q0, [r0, q1] + +# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f] +# CHECK-NOFP: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f] +vstrb.32 q3, [r0, q1] + +# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f] +# CHECK-NOFP: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f] +vstrb.32 q3, [r0, q3] + +# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e] +# CHECK-NOFP: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e] +vstrh.16 q0, [r0, q1] + +# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +vstrh.16 q3, [r0, q1] + +# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e] +# CHECK-NOFP: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e] +vstrh.16 q3, [r0, q3] + +# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f] +# CHECK-NOFP: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f] +vstrh.32 q0, [r0, q1] + +# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f] +# CHECK-NOFP: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f] +vstrh.32 q3, [r0, q1] + +# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f] +# CHECK-NOFP: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f] +vstrh.32 q3, [r0, q3] + +# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +vstrh.16 q0, [r0, q1, uxtw #1] + +# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f] +# CHECK-NOFP: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f] +vstrh.32 q3, [r8, q3, uxtw #1] + +# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +vstrw.32 q0, [r0, q1] + +# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f] +# CHECK-NOFP: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f] +vstrw.32 q3, [r0, q1] + +# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f] +# CHECK-NOFP: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f] +vstrw.32 q3, [r0, q3] + +# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +vstrw.32 q0, [r0, q1, uxtw #2] + +# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f] +# CHECK-NOFP: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f] +vstrw.32 q0, [sp, q1, uxtw #2] + +# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f] +# CHECK-NOFP: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f] +vstrd.64 q0, [r0, q1] + +# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +vstrd.64 q3, [r0, q1] + +# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f] +# CHECK-NOFP: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f] +vstrd.64 q3, [r0, q3] + +# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +vstrd.64 q0, [r0, q1, uxtw #3] + +# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f] +# CHECK-NOFP: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f] +vstrd.64 q0, [sp, q1, uxtw #3] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7] +vstrw.32 q9, [sp, q1, uxtw #2] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrh.16 q3, [pc, q1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrd.64 q0, [r0, q1, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrd.u64 q0, [r0, q1, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrd.64 q0, [r0, q1, uxtw #2] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrd.u64 q0, [r0, q1, uxtw #2] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrw.u32 q0, [r0, q1, uxtw #1] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrh.16 q0, [r0, q1, uxtw #2] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrb.32 q0, [r11, q1, uxtw #1] + +# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +vldrw.u32 q0, [q1] + +# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe] +vldrw.u32 q7, [q1] + +# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +vldrw.u32 q7, [q1]! + +# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +vldrw.u32 q7, [q1, #4] + +# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe] +vldrw.u32 q7, [q1, #-4] + +# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe] +vldrw.u32 q7, [q1, #508] + +# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe] +vldrw.u32 q7, [q1, #-508] + +# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe] +vldrw.u32 q7, [q1, #264] + +# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +vldrw.u32 q7, [q1, #4]! + +# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +vstrw.32 q0, [q1] + +# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe] +vstrw.32 q7, [q1] + +# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +vstrw.32 q7, [q1]! + +# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe] +vstrw.32 q7, [q7] + +# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe] +vstrw.32 q7, [q1, #4] + +# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe] +vstrw.32 q7, [q1, #-4] + +# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +vstrw.32 q7, [q1, #508] + +# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe] +vstrw.32 q7, [q1, #-508] + +# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +vstrw.32 q7, [q1, #264]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7] +vstrw.32 q8, [q1]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrw.32 q4, [q1, #3]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vldrw.u32 q7, [q1, #512] + +# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +vldrd.u64 q0, [q1] + +# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff] +vldrd.u64 q7, [q1] + +# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +vldrd.u64 q7, [q1]! + +# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +vldrd.u64 q7, [q1, #8] + +# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff] +vldrd.u64 q7, [q1, #-8] + +# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff] +vldrd.u64 q7, [q1, #1016] + +# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff] +vldrd.u64 q7, [q1, #-1016] + +# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +vldrd.u64 q7, [q1, #264] + +# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff] +vldrd.u64 q7, [q1, #624] + +# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +vldrd.u64 q7, [q1, #264] + +# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +vldrd.u64 q7, [q1, #-1016]! + +# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +vstrd.64 q0, [q1] + +# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff] +vstrd.64 q7, [q1] + +# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +vstrd.64 q7, [q1]! + +# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff] +vstrd.64 q7, [q7] + +# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff] +vstrd.64 q7, [q1, #8] + +# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +vstrd.64 q7, [q1, #-8]! + +# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +vstrd.64 q7, [q1, #1016] + +# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff] +vstrd.64 q7, [q1, #-1016] + +# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +vstrd.64 q7, [q1, #264] + +# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff] +vstrd.64 q7, [q1, #624] + +# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +vstrd.64 q7, [q1, #264] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7] +vldrd.u64 q8, [q1]! + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrd.64 q7, [q1, #1024] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrd.64 q4, [q1, #3] + +# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction +vstrd.64 q4, [q1, #4] + +# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +vldrb.s8 q0, [r0] + +# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +vldrb.f8 q0, [r0] + +# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +vldrb.8 q0, [r0] + +# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +vldrb.s8 q0, [r8, #56] + +# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +vldrb.f8 q0, [r8, #56] + +# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +vldrb.8 q0, [r8, #56] + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +vldrb.s8 q5, [r4, #56]! + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +vldrb.f8 q5, [r4, #56]! + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +vldrb.8 q5, [r4, #56]! + +# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +vstrb.u8 q0, [r0] + +# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +vstrb.s8 q0, [r0] + +# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +vstrb.f8 q0, [r0] + +# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +vstrb.u8 q4, [r4, #56] + +# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +vstrb.s8 q4, [r4, #56] + +# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +vstrb.f8 q4, [r4, #56] + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +vstrb.u8 q5, [r4, #56]! + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +vstrb.s8 q5, [r4, #56]! + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +vstrb.f8 q5, [r4, #56]! + +# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +vldrh.s16 q0, [r0] + +# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +vldrh.f16 q0, [r0] + +# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +vldrh.16 q0, [r0] + +# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +vldrh.s16 q0, [r4, #56] + +# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +vldrh.f16 q0, [r4, #56] + +# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +vldrh.16 q0, [r4, #56] + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +vldrh.s16 q5, [r4, #56]! + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +vldrh.f16 q5, [r4, #56]! + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +vldrh.16 q5, [r4, #56]! + +# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +vstrh.u16 q0, [r0] + +# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +vstrh.s16 q0, [r0] + +# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +vstrh.f16 q0, [r0] + +# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +vstrh.u16 q0, [r4, #56] + +# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +vstrh.s16 q0, [r4, #56] + +# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +vstrh.f16 q0, [r4, #56] + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +vstrh.u16 q5, [r4, #56]! + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +vstrh.s16 q5, [r4, #56]! + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +vstrh.f16 q5, [r4, #56]! + +# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +vldrw.s32 q0, [r0] + +# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +vldrw.f32 q0, [r0] + +# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +vldrw.32 q0, [r0] + +# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +vldrw.s32 q0, [r4, #56] + +# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +vldrw.f32 q0, [r4, #56] + +# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +vldrw.32 q0, [r4, #56] + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +vldrw.s32 q5, [r4, #56]! + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +vldrw.f32 q5, [r4, #56]! + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +vldrw.32 q5, [r4, #56]! + +# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +vstrw.u32 q0, [r0] + +# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +vstrw.s32 q0, [r0] + +# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +vstrw.f32 q0, [r0] + +# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +vstrw.u32 q0, [r4, #56] + +# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +vstrw.s32 q0, [r4, #56] + +# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +vstrw.f32 q0, [r4, #56] + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +vstrw.u32 q5, [r4, #56]! + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +vstrw.s32 q5, [r4, #56]! + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +vstrw.f32 q5, [r4, #56]! + +# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +vldrb.s8 q0, [r0, q1] + +# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +vldrb.f8 q0, [r0, q1] + +# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +vldrb.8 q0, [r0, q1] + +# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +vldrh.s16 q3, [r0, q1] + +# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +vldrh.f16 q3, [r0, q1] + +# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +vldrh.16 q3, [r0, q1] + +# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +vldrh.s16 q0, [r0, q1, uxtw #1] + +# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +vldrh.f16 q0, [r0, q1, uxtw #1] + +# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +vldrh.16 q0, [r0, q1, uxtw #1] + +# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +vldrw.s32 q0, [r0, q1] + +# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +vldrw.f32 q0, [r0, q1] + +# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +vldrw.32 q0, [r0, q1] + +# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +vldrw.s32 q0, [r0, q1, uxtw #2] + +# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +vldrw.f32 q0, [r0, q1, uxtw #2] + +# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +vldrw.32 q0, [r0, q1, uxtw #2] + +# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +vldrd.s64 q0, [r0, q1] + +# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +vldrd.f64 q0, [r0, q1] + +# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +vldrd.64 q0, [r0, q1] + +# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +vldrd.s64 q0, [r0, q1, uxtw #3] + +# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +vldrd.f64 q0, [r0, q1, uxtw #3] + +# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +vldrd.64 q0, [r0, q1, uxtw #3] + +# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +vstrb.u8 q0, [r0, q1] + +# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +vstrb.s8 q0, [r0, q1] + +# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +vstrb.f8 q0, [r0, q1] + +# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +vstrh.u16 q3, [r0, q1] + +# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +vstrh.s16 q3, [r0, q1] + +# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +vstrh.f16 q3, [r0, q1] + +# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +vstrh.u16 q0, [r0, q1, uxtw #1] + +# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +vstrh.s16 q0, [r0, q1, uxtw #1] + +# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +vstrh.f16 q0, [r0, q1, uxtw #1] + +# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +vstrw.u32 q0, [r0, q1] + +# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +vstrw.s32 q0, [r0, q1] + +# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +vstrw.f32 q0, [r0, q1] + +# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +vstrw.u32 q0, [r0, q1, uxtw #2] + +# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +vstrw.s32 q0, [r0, q1, uxtw #2] + +# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +vstrw.f32 q0, [r0, q1, uxtw #2] + +# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +vstrd.u64 q3, [r0, q1] + +# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +vstrd.s64 q3, [r0, q1] + +# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +vstrd.f64 q3, [r0, q1] + +# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +vstrd.u64 q0, [r0, q1, uxtw #3] + +# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +vstrd.s64 q0, [r0, q1, uxtw #3] + +# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +vstrd.f64 q0, [r0, q1, uxtw #3] + +# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +vldrw.s32 q0, [q1] + +# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +vldrw.f32 q0, [q1] + +# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +vldrw.32 q0, [q1] + +# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +vldrw.s32 q7, [q1]! + +# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +vldrw.f32 q7, [q1]! + +# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +vldrw.32 q7, [q1]! + +# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +vldrw.s32 q7, [q1, #4] + +# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +vldrw.f32 q7, [q1, #4] + +# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +vldrw.32 q7, [q1, #4] + +# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +vldrw.s32 q7, [q1, #4]! + +# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +vldrw.f32 q7, [q1, #4]! + +# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe] +vldrw.u32 q7, [q1, #4]! + +# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +vstrw.u32 q0, [q1] + +# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +vstrw.s32 q0, [q1] + +# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +vstrw.f32 q0, [q1] + +# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +vstrw.u32 q7, [q1]! + +# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +vstrw.s32 q7, [q1]! + +# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +vstrw.f32 q7, [q1]! + +# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +vstrw.u32 q7, [q1, #508] + +# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +vstrw.s32 q7, [q1, #508] + +# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +vstrw.f32 q7, [q1, #508] + +# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +vstrw.u32 q7, [q1, #264]! + +# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +vstrw.s32 q7, [q1, #264]! + +# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +vstrw.f32 q7, [q1, #264]! + +# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +vldrd.s64 q0, [q1] + +# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +vldrd.f64 q0, [q1] + +# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +vldrd.64 q0, [q1] + +# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +vldrd.s64 q7, [q1]! + +# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +vldrd.f64 q7, [q1]! + +# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +vldrd.64 q7, [q1]! + +# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +vldrd.s64 q7, [q1, #8] + +# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +vldrd.f64 q7, [q1, #8] + +# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +vldrd.64 q7, [q1, #8] + +# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +vldrd.s64 q7, [q1, #-1016]! + +# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +vldrd.f64 q7, [q1, #-1016]! + +# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff] +vldrd.64 q7, [q1, #-1016]! + +# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +vstrd.u64 q0, [q1] + +# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +vstrd.s64 q0, [q1] + +# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +vstrd.f64 q0, [q1] + +# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +vstrd.u64 q7, [q1]! + +# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +vstrd.s64 q7, [q1]! + +# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +vstrd.f64 q7, [q1]! + +# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +vstrd.u64 q7, [q1, #1016] + +# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +vstrd.s64 q7, [q1, #1016] + +# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +vstrd.f64 q7, [q1, #1016] + +# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +vstrd.u64 q7, [q1, #-8]! + +# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +vstrd.s64 q7, [q1, #-8]! + +# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +vstrd.f64 q7, [q1, #-8]! + +vpste +vstrwt.f32 q7, [q1, #264]! +vldrde.64 q7, [q1, #8] +# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f] +# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f] +# CHECK: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOFP: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOFP: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] diff --git a/llvm/test/MC/Disassembler/ARM/mve-load-store.txt b/llvm/test/MC/Disassembler/ARM/mve-load-store.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/mve-load-store.txt @@ -0,0 +1,1642 @@ +# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s +# RUN: FileCheck --check-prefix=ERROR < %t %s +# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t +# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s + +# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x00,0x1e] + +# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x00,0x1e] + +# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x00,0x1e] + +# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x00,0xbe] + +# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x20,0x1e] + +# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x20,0x7e] + +# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x80,0x1e] + +# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x80,0x1e] + +# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x80,0x1e] + +# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x80,0xbe] + +# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xa0,0x1e] + +# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0xa0,0x7e] + +# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x00,0x1f] + +# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x00,0x1f] + +# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x00,0x1f] + +# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x00,0xbf] + +# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x20,0x1f] + +# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x20,0x7f] + +# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0x00,0x1e] + +# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x00,0x1e] + +# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xfc,0x00,0x1e] + +# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x00,0xbe] + +# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0x20,0x1e] + +# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x20,0x7e] + +# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0x80,0x1e] + +# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x80,0x1e] + +# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xfc,0x80,0x1e] + +# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x80,0xbe] + +# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0xa0,0x1e] + +# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0xa0,0x7e] + +# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0x00,0x1f] + +# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x00,0x1f] + +# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xfc,0x00,0x1f] + +# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x00,0xbf] + +# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xfc,0x20,0x1f] + +# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa0,0xfc,0x20,0x7f] + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x01,0x1e] + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x01,0x1e] + +# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x01,0x1e] + +# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x01,0x7e] + +# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x21,0x1e] + +# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x21,0x9e] + +# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x41,0x1e] + +# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x41,0x1e] + +# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x61,0x1e] + +# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x61,0x9e] + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x81,0x1e] + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x81,0x1e] + +# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x81,0x1e] + +# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x81,0x7e] + +# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xa1,0x1e] + +# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0xa1,0x9e] + +# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xc1,0x1e] + +# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0xc1,0x1e] + +# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xe1,0x1e] + +# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0xe1,0x9e] + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x01,0x1f] + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x01,0x1f] + +# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xfc,0x01,0x1f] + +# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x01,0x7f] + +# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x21,0x1f] + +# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x21,0x9f] + +# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x41,0x1f] + +# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x41,0x1f] + +# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x61,0x1f] + +# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb0,0xfc,0x61,0x9f] + +# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x1e] + +# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x3e] + +# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x00,0x1e] + +# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x00,0x7e] + +# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x38,0x1e] + +# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x38,0x9e] + +# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xed,0x38,0x1e] + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x38,0xbe] + +# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x38,0xbe] + +# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xec,0x19,0xbe] + +# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3a,0xec,0x19,0xbe] + +# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x19,0xbe] + +# CHECK: vldrb.u8 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x40,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x40,0xbe] + +# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x1e] + +# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x3e] + +# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x00,0x1e] + +# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x00,0x7e] + +# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x38,0x1e] + +# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x38,0x9e] + +# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xed,0x38,0x1e] + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x38,0xbe] + +# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x38,0xbe] + +# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x24,0xec,0x19,0xbe] + +# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x2a,0xec,0x19,0xbe] + +# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x19,0xbe] + +# CHECK: vstrb.8 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x40,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x40,0xbe] + +# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding +[0xad,0xec,0x00,0x1e] + +# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfd,0x80,0x0e] + +# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfd,0x80,0x2e] + +# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xfd,0x80,0x0e] + +# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xfd,0x80,0x6e] + +# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xfd,0xb8,0x0e] + +# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xfd,0xb8,0x8e] + +# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0xb8,0x0e] + +# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xfd,0xb8,0xae] + +# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xfd,0xb8,0xae] + +# CHECK: vldrb.u16 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xfc,0x99,0xae] + +# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x33,0xfc,0x99,0xae] + +# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xfd,0x99,0xae] + +# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xfd,0xc0,0xae] + +# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x80,0x0e] + +# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x80,0x2e] + +# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xed,0x80,0x0e] + +# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xed,0x80,0x6e] + +# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0xb8,0x0e] + +# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0xb8,0x8e] + +# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xed,0xb8,0x0e] + +# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0xb8,0xae] + +# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0xb8,0xae] + +# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xec,0x99,0xae] + +# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x33,0xec,0x99,0xae] + +# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xed,0x99,0xae] + +# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xed,0xc0,0xae] + +# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x80,0x0e] + +# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x80,0x2e] + +# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x87,0xed,0x80,0x0e] + +# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x87,0xed,0x80,0x6e] + +# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0xb8,0x0e] + +# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0xb8,0x8e] + +# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x85,0xed,0xb8,0x0e] + +# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0xb8,0xae] + +# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0xb8,0xae] + +# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x24,0xec,0x99,0xae] + +# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x23,0xec,0x99,0xae] + +# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xed,0x99,0xae] + +# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xed,0xc0,0xae] + +# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfd,0x00,0x0f] + +# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfd,0x00,0x2f] + +# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xfd,0x00,0x0f] + +# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xfd,0x00,0x6f] + +# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xfd,0x38,0x0f] + +# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xfd,0x38,0x8f] + +# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x38,0x0f] + +# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xfd,0x38,0xaf] + +# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xfd,0x38,0xaf] + +# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xfc,0x19,0xaf] + +# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x33,0xfc,0x19,0xaf] + +# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xfd,0x19,0xaf] + +# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xfd,0x40,0xaf] + +# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x0f] + +# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x2f] + +# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xed,0x00,0x0f] + +# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x97,0xed,0x00,0x6f] + +# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x38,0x0f] + +# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x38,0x8f] + +# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xed,0x38,0x0f] + +# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x38,0xaf] + +# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x38,0xaf] + +# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xec,0x19,0xaf] + +# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x33,0xec,0x19,0xaf] + +# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xed,0x19,0xaf] + +# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x16,0xed,0x40,0xaf] + +# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x0f] + +# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x2f] + +# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x87,0xed,0x00,0x0f] + +# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x87,0xed,0x00,0x6f] + +# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x38,0x0f] + +# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x38,0x8f] + +# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x85,0xed,0x38,0x0f] + +# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x38,0xaf] + +# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x38,0xaf] + +# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x24,0xec,0x19,0xaf] + +# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x23,0xec,0x19,0xaf] + +# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xed,0x19,0xaf] + +# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xed,0x40,0xaf] + +# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x80,0x1e] + +# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x80,0x3e] + +# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x80,0x1e] + +# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x80,0x7e] + +# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x9c,0x1e] + +# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x9c,0x9e] + +# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xed,0x9c,0x1e] + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x9c,0xbe] + +# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x9c,0xbe] + +# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xec,0x8d,0xbe] + +# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3a,0xec,0x8d,0xbe] + +# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x8d,0xbe] + +# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0xa0,0xbe] + +# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0xff,0xbe] + +# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xba,0xec,0xff,0xbe] + +# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x80,0x1e] + +# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x80,0x3e] + +# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x80,0x1e] + +# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x80,0x7e] + +# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x9c,0x1e] + +# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x9c,0x9e] + +# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xed,0x9c,0x1e] + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x9c,0xbe] + +# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x9c,0xbe] + +# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x24,0xec,0x8d,0xbe] + +# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x2a,0xec,0x8d,0xbe] + +# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x8d,0xbe] + +# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0xa0,0xbe] + +# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0xff,0xbe] + +# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xaa,0xec,0xff,0xbe] + +# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xfd,0x00,0x0f] + +# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xfd,0x00,0x2f] + +# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9f,0xfd,0x00,0x0f] + +# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9f,0xfd,0x00,0x6f] + +# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9c,0xfd,0x1c,0x0f] + +# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9c,0xfd,0x1c,0x8f] + +# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9a,0xfd,0x1c,0x0f] + +# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xfd,0x1c,0xaf] + +# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xfd,0x1c,0xaf] + +# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3c,0xfc,0x0d,0xaf] + +# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3b,0xfc,0x0d,0xaf] + +# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xfd,0x0d,0xaf] + +# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xfd,0x20,0xaf] + +# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xfd,0x7f,0xaf] + +# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xfd,0x7f,0xaf] + +# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xed,0x00,0x0f] + +# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xed,0x00,0x2f] + +# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9f,0xed,0x00,0x0f] + +# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9f,0xed,0x00,0x6f] + +# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9c,0xed,0x1c,0x0f] + +# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9c,0xed,0x1c,0x8f] + +# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9a,0xed,0x1c,0x0f] + +# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xed,0x1c,0xaf] + +# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xed,0x1c,0xaf] + +# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3c,0xec,0x0d,0xaf] + +# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3b,0xec,0x0d,0xaf] + +# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xed,0x0d,0xaf] + +# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xed,0x20,0xaf] + +# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1e,0xed,0x7f,0xaf] + +# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbc,0xed,0x7f,0xaf] + +# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xed,0x00,0x0f] + +# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xed,0x00,0x2f] + +# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8f,0xed,0x00,0x0f] + +# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8f,0xed,0x00,0x6f] + +# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8c,0xed,0x1c,0x0f] + +# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8c,0xed,0x1c,0x8f] + +# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8d,0xed,0x1c,0x0f] + +# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xac,0xed,0x1c,0xaf] + +# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xac,0xed,0x1c,0xaf] + +# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x2c,0xec,0x0d,0xaf] + +# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x2b,0xec,0x0d,0xaf] + +# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0a,0xed,0x0d,0xaf] + +# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0a,0xed,0x20,0xaf] + +# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0a,0xed,0x7f,0xaf] + +# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xac,0xed,0x7f,0xaf] + +# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x1f] + +# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xed,0x00,0x3f] + +# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x00,0x1f] + +# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9b,0xed,0x00,0x7f] + +# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x0e,0x1f] + +# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x94,0xed,0x0e,0x9f] + +# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xed,0x0e,0x1f] + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x0e,0xbf] + +# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x0e,0xbf] + +# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x34,0xec,0x07,0xbf] + +# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x3a,0xec,0x07,0xbf] + +# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x07,0xbf] + +# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x10,0xbf] + +# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x1d,0xed,0x7f,0xbf] + +# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb4,0xed,0x7f,0xbf] + +# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xbd,0xed,0x7f,0xbf] + +# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x1f] + +# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xed,0x00,0x3f] + +# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x00,0x1f] + +# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8b,0xed,0x00,0x7f] + +# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x0e,0x1f] + +# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x84,0xed,0x0e,0x9f] + +# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xed,0x0e,0x1f] + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x0e,0xbf] + +# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x0e,0xbf] + +# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x24,0xec,0x07,0xbf] + +# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x2a,0xec,0x07,0xbf] + +# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x07,0xbf] + +# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x10,0xbf] + +# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x0d,0xed,0x7f,0xbf] + +# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa4,0xed,0x7f,0xbf] + +# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xad,0xed,0x7f,0xbf] + +# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x02,0x0e] + +# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9a,0xfc,0x02,0x6e] + +# CHECK: vldrb.u8 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x06,0x6e] + +# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x82,0x0e] + +# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x99,0xfc,0x82,0x6e] + +# CHECK: vldrb.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x86,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x86,0x6e] + +# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x82,0x0e] + +# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9d,0xec,0x82,0x6e] + +# CHECK: vldrb.s16 q3, [r0, q3] @ encoding: [0x90,0xec,0x86,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x86,0x6e] + +# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x02,0x0f] + +# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x02,0x6f] + +# CHECK: vldrb.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x06,0x6f] + +# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x02,0x0f] + +# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x02,0x6f] + +# CHECK: vldrb.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x06,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x06,0x6f] + +# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x92,0x0e] + +# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x92,0x6e] + +# CHECK: vldrh.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x96,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x96,0x6e] + +# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x12,0x0f] + +# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x12,0x6f] + +# CHECK: vldrh.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x16,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x16,0x6f] + +# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x12,0x0f] + +# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x12,0x6f] + +# CHECK: vldrh.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x16,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xec,0x16,0x6f] + +# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x93,0x0e] + +# CHECK: vldrh.u32 q3, [r8, q3, uxtw #1] @ encoding: [0x98,0xfc,0x17,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x98,0xfc,0x17,0x6f] + +# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x42,0x0f] + +# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x42,0x6f] + +# CHECK: vldrw.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x46,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x46,0x6f] + +# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0x43,0x0f] + +# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9d,0xfc,0x43,0x0f] + +# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xd2,0x0f] + +# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xd2,0x6f] + +# CHECK: vldrd.u64 q3, [r0, q3] @ encoding: [0x90,0xfc,0xd6,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xd6,0x6f] + +# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x90,0xfc,0xd3,0x0f] + +# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9d,0xfc,0xd3,0x0f] + +# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x02,0x0e] + +# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8a,0xec,0x02,0x6e] + +# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x06,0x6e] + +# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x82,0x0e] + +# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8d,0xec,0x82,0x6e] + +# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x86,0x6e] + +# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x02,0x0f] + +# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x02,0x6f] + +# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x06,0x6f] + +# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x92,0x0e] + +# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x92,0x6e] + +# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x96,0x6e] + +# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x12,0x0f] + +# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x12,0x6f] + +# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x16,0x6f] + +# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x93,0x0e] + +# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x88,0xec,0x17,0x6f] + +# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x42,0x0f] + +# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x42,0x6f] + +# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x46,0x6f] + +# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0x43,0x0f] + +# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8d,0xec,0x43,0x0f] + +# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0xd2,0x0f] + +# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0xd2,0x6f] + +# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0xd6,0x6f] + +# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x80,0xec,0xd3,0x0f] + +# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8d,0xec,0xd3,0x0f] + +# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x00,0x1e] + +# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x00,0xfe] + +# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb2,0xfd,0x00,0xfe] + +# CHECK: vldrw.u32 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9e,0xfd,0x00,0xfe] + +# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x01,0xfe] + +# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x12,0xfd,0x01,0xfe] + +# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x7f,0xfe] + +# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x12,0xfd,0x7f,0xfe] + +# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x42,0xfe] + +# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x00,0x1e] + +# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x00,0xfe] + +# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa2,0xfd,0x00,0xfe] + +# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8e,0xfd,0x00,0xfe] + +# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x01,0xfe] + +# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xfd,0x01,0xfe] + +# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x7f,0xfe] + +# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xfd,0x7f,0xfe] + +# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa2,0xfd,0x42,0xfe] + +# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x00,0x1f] + +# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x00,0xff] + +# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xb2,0xfd,0x00,0xff] + +# CHECK: vldrd.u64 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x9e,0xfd,0x00,0xff] + +# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x01,0xff] + +# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x12,0xfd,0x01,0xff] + +# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x7f,0xff] + +# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x12,0xfd,0x7f,0xff] + +# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x21,0xff] + +# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x4e,0xff] + +# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x92,0xfd,0x21,0xff] + +# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x00,0x1f] + +# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x00,0xff] + +# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0xa2,0xfd,0x00,0xff] + +# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x8e,0xfd,0x00,0xff] + +# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x01,0xff] + +# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x22,0xfd,0x01,0xff] + +# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x7f,0xff] + +# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x02,0xfd,0x7f,0xff] + +# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x21,0xff] + +# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x4e,0xff] + +# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff] +# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding +[0x82,0xfd,0x21,0xff] + +# CHECK: vldrb.u8 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3e] +[0x92,0xed,0x00,0x3e] + +# CHECK: vldrb.u8 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3e] +[0x12,0xed,0x00,0x3e] + +# CHECK: vldrb.u16 q1, [r2] @ encoding: [0x92,0xfd,0x80,0x2e] +[0x92,0xfd,0x80,0x2e] + +# CHECK: vldrb.u16 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x80,0x2e] +[0x12,0xfd,0x80,0x2e] + +# CHECK: vldrb.s16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x2e] +[0x92,0xed,0x80,0x2e] + +# CHECK: vldrb.s16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x2e] +[0x12,0xed,0x80,0x2e] + +# CHECK: vldrb.u32 q1, [r2] @ encoding: [0x92,0xfd,0x00,0x2f] +[0x92,0xfd,0x00,0x2f] + +# CHECK: vldrb.u32 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x00,0x2f] +[0x12,0xfd,0x00,0x2f] + +# CHECK: vldrb.s32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x2f] +[0x92,0xed,0x00,0x2f] + +# CHECK: vldrb.s32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x2f] +[0x12,0xed,0x00,0x2f] + +# CHECK: vldrh.u16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x3e] +[0x92,0xed,0x80,0x3e] + +# CHECK: vldrh.u16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x3e] +[0x12,0xed,0x80,0x3e] + +# CHECK: vldrh.u32 q1, [r2] @ encoding: [0x9a,0xfd,0x00,0x2f] +[0x9a,0xfd,0x00,0x2f] + +# CHECK: vldrh.u32 q1, [r2, #-0] @ encoding: [0x1a,0xfd,0x00,0x2f] +[0x1a,0xfd,0x00,0x2f] + +# CHECK: vldrh.s32 q1, [r2] @ encoding: [0x9a,0xed,0x00,0x2f] +[0x9a,0xed,0x00,0x2f] + +# CHECK: vldrh.s32 q1, [r2, #-0] @ encoding: [0x1a,0xed,0x00,0x2f] +[0x1a,0xed,0x00,0x2f] + +# CHECK: vldrw.u32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3f] +[0x92,0xed,0x00,0x3f] + +# CHECK: vldrw.u32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3f] +[0x12,0xed,0x00,0x3f] + +# CHECK: vldrw.u32 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3e] +[0x94,0xfd,0x00,0x3e] + +# CHECK: vldrw.u32 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3e] +[0x14,0xfd,0x00,0x3e] + +# CHECK: vldrd.u64 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3f] +[0x94,0xfd,0x00,0x3f] + +# CHECK: vldrd.u64 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3f] +[0x14,0xfd,0x00,0x3f] + +# CHECK: vstrb.8 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3e] +[0x82,0xed,0x00,0x3e] + +# CHECK: vstrb.8 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3e] +[0x02,0xed,0x00,0x3e] + +# CHECK: vstrb.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x2e] +[0x82,0xed,0x80,0x2e] + +# CHECK: vstrb.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x2e] +[0x02,0xed,0x80,0x2e] + +# CHECK: vstrb.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x2f] +[0x82,0xed,0x00,0x2f] + +# CHECK: vstrb.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x2f] +[0x02,0xed,0x00,0x2f] + +# CHECK: vstrh.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x3e] +[0x82,0xed,0x80,0x3e] + +# CHECK: vstrh.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x3e] +[0x02,0xed,0x80,0x3e] + +# CHECK: vstrh.32 q1, [r2] @ encoding: [0x8a,0xed,0x00,0x2f] +[0x8a,0xed,0x00,0x2f] + +# CHECK: vstrh.32 q1, [r2, #-0] @ encoding: [0x0a,0xed,0x00,0x2f] +[0x0a,0xed,0x00,0x2f] + +# CHECK: vstrw.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3f] +[0x82,0xed,0x00,0x3f] + +# CHECK: vstrw.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3f] +[0x02,0xed,0x00,0x3f] + +# CHECK: vstrw.32 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3e] +[0x84,0xfd,0x00,0x3e] + +# CHECK: vstrw.32 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3e] +[0x04,0xfd,0x00,0x3e] + +# CHECK: vstrd.64 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3f] +[0x84,0xfd,0x00,0x3f] + +# CHECK: vstrd.64 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3f] +[0x04,0xfd,0x00,0x3f] +