diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -483,6 +483,14 @@
   let ParserMatchClass = VCADDRotImmAsmOperand;
 }
 
+// Power of two operand
+def powertwo_asmoperand : AsmOperandClass { let Name = "PowerTwo"; }
+def powertwo : Operand<i32> {
+  let EncoderMethod = "getPowerTwoOpValue";
+  let DecoderMethod = "DecodePowerTwoOperand";
+  let ParserMatchClass = powertwo_asmoperand;
+}
+
 // Vector indexing
 class MVEVectorIndexOperand<string size> : AsmOperandClass {
   let Name = "MVEVectorIndex"#size;
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2765,6 +2765,432 @@
 
 // end of mve_qDest_qSrc
 
+// start of mve_qDest_rSrc
+
+class MVE_qr_base<dag oops, dag iops, InstrItinClass itin, string iname,
+                  string suffix, string ops, vpred_ops vpred, string cstr,
+                  list<dag> pattern=[]>
+   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<5> Rm;
+
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b111;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{3-0} = Rm{3-0};
+}
+
+class MVE_qDest_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, "",
+           pattern>;
+
+class MVE_qDestSrc_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_n, "$Qd = $Qd_src",
+           pattern>;
+
+class MVE_qDest_single_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, rGPR:$Rm), NoItinerary, iname,
+          suffix, "$Qd, $Rm", vpred_n, "$Qd = $Qd_src", pattern> {
+  bits<4> Qd;
+  bits<5> Rm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{3-0} = Rm{3-0};
+}
+
+class VADDVSUBt2i<string iname, string suffix, bits<2> size,
+                  bit bit_5, bit bit_12, bit bit_16,
+                  bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{16} = bit_16;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = bit_5;
+}
+
+def VSUBt2i8  : VADDVSUBt2i<"vsub", "i8", 0b00, 0b0, 0b1, 0b1, 0b0>;
+def VSUBt2i16 : VADDVSUBt2i<"vsub", "i16", 0b01, 0b0, 0b1, 0b1, 0b0>;
+def VSUBt2i32 : VADDVSUBt2i<"vsub", "i32", 0b10, 0b0, 0b1, 0b1, 0b0>;
+
+def VQSUBt2s8  : VADDVSUBt2i<"vqsub", "s8", 0b00, 0b1, 0b1, 0b0, 0b0>;
+def VQSUBt2s16 : VADDVSUBt2i<"vqsub", "s16", 0b01, 0b1, 0b1, 0b0, 0b0>;
+def VQSUBt2s32 : VADDVSUBt2i<"vqsub", "s32", 0b10, 0b1, 0b1, 0b0,  0b0>;
+def VQSUBt2u8  : VADDVSUBt2i<"vqsub", "u8", 0b00, 0b1, 0b1, 0b0, 0b1>;
+def VQSUBt2u16 : VADDVSUBt2i<"vqsub", "u16", 0b01, 0b1, 0b1, 0b0, 0b1>;
+def VQSUBt2u32 : VADDVSUBt2i<"vqsub", "u32", 0b10, 0b1, 0b1, 0b0, 0b1>;
+
+def VADDt2i8  : VADDVSUBt2i<"vadd", "i8", 0b00, 0b0, 0b0, 0b1, 0b0>;
+def VADDt2i16 : VADDVSUBt2i<"vadd", "i16", 0b01, 0b0, 0b0, 0b1, 0b0>;
+def VADDt2i32 : VADDVSUBt2i<"vadd", "i32", 0b10, 0b0, 0b0, 0b1, 0b0>;
+
+def VQADDt2s8  : VADDVSUBt2i<"vqadd", "s8", 0b00, 0b1, 0b0, 0b0, 0b0>;
+def VQADDt2s16 : VADDVSUBt2i<"vqadd", "s16", 0b01, 0b1, 0b0, 0b0, 0b0>;
+def VQADDt2s32 : VADDVSUBt2i<"vqadd", "s32", 0b10, 0b1, 0b0, 0b0,  0b0>;
+def VQADDt2u8  : VADDVSUBt2i<"vqadd", "u8", 0b00, 0b1, 0b0, 0b0, 0b1>;
+def VQADDt2u16 : VADDVSUBt2i<"vqadd", "u16", 0b01, 0b1, 0b0, 0b0, 0b1>;
+def VQADDt2u32 : VADDVSUBt2i<"vqadd", "u32", 0b10, 0b1, 0b0, 0b0, 0b1>;
+
+class VQDMULLt2<string iname, string suffix, bit size,
+                bit T, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b0;
+  let Inst{12} = T;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b1;
+}
+
+multiclass VQDMULLt2_half_multi<string suffix, bit size> {
+  def bh : VQDMULLt2<"vqdmullb", suffix, size, 0b0>;
+  def th : VQDMULLt2<"vqdmullt", suffix, size, 0b1>;
+}
+
+defm VQDMULLt2s16 : VQDMULLt2_half_multi<"s16", 0b0>;
+defm VQDMULLt2s32 : VQDMULLt2_half_multi<"s32", 0b1>;
+
+class VADDVSUBt2f<string iname, string suffix, bit size, bit bit_12,
+                  list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VSUBt2f32 : VADDVSUBt2f<"vsub", "f32", 0b0, 0b1>;
+def VSUBt2f16 : VADDVSUBt2f<"vsub", "f16", 0b1, 0b1>;
+
+def VADDt2f32 : VADDVSUBt2f<"vadd", "f32", 0b0, 0b0>;
+def VADDt2f16 : VADDVSUBt2f<"vadd", "f16", 0b1, 0b0>;
+
+class VHSUBVHADDt2<string iname, string suffix, bit U, bits<2> size,
+                   bit bit_12, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b0;
+}
+
+def VHSUBt2s8  : VHSUBVHADDt2<"vhsub", "s8", 0b0, 0b00, 0b1>;
+def VHSUBt2s16 : VHSUBVHADDt2<"vhsub", "s16", 0b0, 0b01, 0b1>;
+def VHSUBt2s32 : VHSUBVHADDt2<"vhsub", "s32", 0b0, 0b10, 0b1>;
+def VHSUBt2u8  : VHSUBVHADDt2<"vhsub", "u8", 0b1, 0b00, 0b1>;
+def VHSUBt2u16 : VHSUBVHADDt2<"vhsub", "u16", 0b1, 0b01, 0b1>;
+def VHSUBt2u32 : VHSUBVHADDt2<"vhsub", "u32", 0b1, 0b10, 0b1>;
+
+def VHADDt2s8  : VHSUBVHADDt2<"vhadd", "s8", 0b0, 0b00, 0b0>;
+def VHADDt2s16 : VHSUBVHADDt2<"vhadd", "s16", 0b0, 0b01, 0b0>;
+def VHADDt2s32 : VHSUBVHADDt2<"vhadd", "s32", 0b0, 0b10, 0b0>;
+def VHADDt2u8  : VHSUBVHADDt2<"vhadd", "u8", 0b1, 0b00, 0b0>;
+def VHADDt2u16 : VHSUBVHADDt2<"vhadd", "u16", 0b1, 0b01, 0b0>;
+def VHADDt2u32 : VHSUBVHADDt2<"vhadd", "u32", 0b1, 0b10, 0b0>;
+
+class VQSHLVSHL<string iname, string suffix, bit U, bits<2> size,
+                bit bit_7, bit bit_17, list<dag> pattern=[]>
+  : MVE_qDest_single_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b100;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b1;
+  let Inst{12-8} = 0b11110;
+  let Inst{7} = bit_7;
+  let Inst{6-4} = 0b110;
+}
+
+multiclass VQSHL_helper<string iname, bit bit_7, bit bit_17> {
+  def s8  : VQSHLVSHL<iname, "s8", 0b0, 0b00, bit_7, bit_17>;
+  def s16 : VQSHLVSHL<iname, "s16", 0b0, 0b01, bit_7, bit_17>;
+  def s32 : VQSHLVSHL<iname, "s32", 0b0, 0b10, bit_7, bit_17>;
+  def u8  : VQSHLVSHL<iname, "u8", 0b1, 0b00, bit_7, bit_17>;
+  def u16 : VQSHLVSHL<iname, "u16", 0b1, 0b01, bit_7, bit_17>;
+  def u32 : VQSHLVSHL<iname, "u32", 0b1, 0b10, bit_7, bit_17>;
+}
+
+defm VQRSHLt2 : VQSHL_helper<"vqrshl", 0b1, 0b1>;
+defm VQSHLt1  : VQSHL_helper<"vqshl", 0b1, 0b0>;
+defm VRSHLt2  : VQSHL_helper<"vrshl", 0b0, 0b1>;
+defm VSHLt2   : VQSHL_helper<"vshl", 0b0, 0b0>;
+
+class VBRSRt1<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VBRSRt18  : VBRSRt1<"vbrsr", "8", 0b00>;
+def VBRSRt116 : VBRSRt1<"vbrsr", "16", 0b01>;
+def VBRSRt132 : VBRSRt1<"vbrsr", "32", 0b10>;
+
+class VMULt2<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VMULt2i8   : VMULt2<"vmul", "i8", 0b00>;
+def VMULt2i16  : VMULt2<"vmul", "i16", 0b01>;
+def VMULt2i32  : VMULt2<"vmul", "i32", 0b10>;
+
+class VMULt2f<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VMULt2f32 : VMULt2f<"vmul", "f32", 0b0>;
+def VMULt2f16 : VMULt2f<"vmul", "f16", 0b1>;
+
+class VQDMULHt3<string iname, string suffix, bits<2> size, bit bit_28,
+                list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VQDMULHt3s8  : VQDMULHt3<"vqdmulh", "s8", 0b00, 0b0>;
+def VQDMULHt3s16 : VQDMULHt3<"vqdmulh", "s16", 0b01, 0b0>;
+def VQDMULHt3s32 : VQDMULHt3<"vqdmulh", "s32", 0b10, 0b0>;
+
+def VQRDMULHt4s8  : VQDMULHt3<"vqrdmulh", "s8", 0b00, 0b1>;
+def VQRDMULHt4s16 : VQDMULHt3<"vqrdmulh", "s16", 0b01, 0b1>;
+def VQRDMULHt4s32 : VQDMULHt3<"vqrdmulh", "s32", 0b10, 0b1>;
+
+class VFMASt1<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VFMASt1f32  : VFMASt1<"vfmas", "f32", 0b0>;
+def VFMASt1f16  : VFMASt1<"vfmas", "f16", 0b1>;
+
+class VMLASt1<string iname, string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def VMLASt1s8   : VMLASt1<"vmlas", "s8", 0b0, 0b00>;
+def VMLASt1s16  : VMLASt1<"vmlas", "s16", 0b0, 0b01>;
+def VMLASt1s32  : VMLASt1<"vmlas", "s32", 0b0, 0b10>;
+def VMLASt1u8   : VMLASt1<"vmlas", "u8", 0b1, 0b00>;
+def VMLASt1u16  : VMLASt1<"vmlas", "u16", 0b1, 0b01>;
+def VMLASt1u32  : VMLASt1<"vmlas", "u32", 0b1, 0b10>;
+
+class VFMAt1<string iname, string suffix, bit size,
+             list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VFMAt1rf32 : VFMAt1<"vfma", "f32", 0b0>;
+def VFMAt1rf16 : VFMAt1<"vfma", "f16", 0b1>;
+
+class VMLAt1<string iname, string suffix, bit U, bits<2> size,
+             list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def VMLAt1s8  : VMLAt1<"vmla", "s8", 0b0, 0b00>;
+def VMLAt1s16 : VMLAt1<"vmla", "s16", 0b0, 0b01>;
+def VMLAt1s32 : VMLAt1<"vmla", "s32", 0b0, 0b10>;
+def VMLAt1u8  : VMLAt1<"vmla", "u8", 0b1, 0b00>;
+def VMLAt1u16 : VMLAt1<"vmla", "u16", 0b1, 0b01>;
+def VMLAt1u32 : VMLAt1<"vmla", "u32", 0b1, 0b10>;
+
+class VQDMLAH<string iname, string suffix, bit U, bits<2> size,
+               bit bit_5, bit bit_12, list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b0;
+  let Inst{5} = bit_5;
+}
+
+multiclass VQDMLAH_helper<string iname, bit bit_5, bit bit_12> {
+  def s8  : VQDMLAH<iname, "s8", 0b0, 0b00, bit_5, bit_12>;
+  def s16 : VQDMLAH<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
+  def s32 : VQDMLAH<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
+  def u8  : VQDMLAH<iname, "u8", 0b1, 0b00, bit_5, bit_12>;
+  def u16 : VQDMLAH<iname, "u16", 0b1, 0b01, bit_5, bit_12>;
+  def u32 : VQDMLAH<iname, "u32", 0b1, 0b10, bit_5, bit_12>;
+}
+
+defm VQDMLASHt1  : VQDMLAH_helper<"vqdmlash", 0b1, 0b1>;
+defm VQRDMLASHt2 : VQDMLAH_helper<"vqrdmlash", 0b0, 0b1>;
+defm VQDMLAHt1   : VQDMLAH_helper<"vqdmlah", 0b1, 0b0>;
+defm VQRDMLAHt1  : VQDMLAH_helper<"vqrdmlah", 0b0, 0b0>;
+
+class VIDUP<string iname, string suffix, bits<2> size, bit bit_12,
+            list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, tGPROdd:$Rm, powertwo:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $Rm, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<5> Rm;
+  bits<5> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-4} = 0b110;
+  let Inst{3-1} = Rm{3-1};
+  let Inst{0} = imm{0};
+}
+
+def VIWDUPt1u8  : VIDUP<"viwdup", "u8", 0b00, 0b0>;
+def VIWDUPt1u16 : VIDUP<"viwdup", "u16", 0b01, 0b0>;
+def VIWDUPt1u32 : VIDUP<"viwdup", "u32", 0b10, 0b0>;
+
+def VDWDUPt1u8  : VIDUP<"vdwdup", "u8", 0b00, 0b1>;
+def VDWDUPt1u16 : VIDUP<"vdwdup", "u16", 0b01, 0b1>;
+def VDWDUPt1u32 : VIDUP<"vdwdup", "u32", 0b10, 0b1>;
+
+class VIDUPt2<string iname, string suffix, bits<2> size, bit bit_12,
+              list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, powertwo:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<5> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-1} = 0b110111;
+  let Inst{0} = imm{0};
+}
+
+def VIDUPt2u8  : VIDUPt2<"vidup", "u8", 0b00, 0b0>;
+def VIDUPt2u16 : VIDUPt2<"vidup", "u16", 0b01, 0b0>;
+def VIDUPt2u32 : VIDUPt2<"vidup", "u32", 0b10, 0b0>;
+
+def VDDUPt2u8  : VIDUPt2<"vddup", "u8", 0b00, 0b1>;
+def VDDUPt2u16 : VIDUPt2<"vddup", "u16", 0b01, 0b1>;
+def VDDUPt2u32 : VIDUPt2<"vddup", "u32", 0b10, 0b1>;
+
+
+class VCTPt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
+          "$Rn", vpred_n, "", pattern> {
+  bits<4> Rn;
+
+  let Inst{28-27} = 0b10;
+  let Inst{26-22} = 0b00000;
+  let Inst{21-20} = size;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{15-11} = 0b11101;
+  let Inst{10-0}  = 0b00000000001;
+  let Unpredictable{10-0} = 0b11111111111;
+
+  let Constraints = "";
+  let DecoderMethod = "DecodeMveVCTP";
+}
+
+def VCTPt18  : VCTPt1<"8", 0b00>;
+def VCTPt116 : VCTPt1<"16", 0b01>;
+def VCTPt132 : VCTPt1<"32", 0b10>;
+def VCTPt164 : VCTPt1<"64", 0b11>;
+
+// end of mve_qDest_rSrc
+
 class t2VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1300,6 +1300,13 @@
     int64_t Value = CE->getValue();
     return Value == 90 || Value == 270;
   }
+  bool isPowerTwo() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value == 1 || Value == 2 || Value == 4 || Value == 8;
+  }
   bool isModImm() const { return Kind == k_ModifiedImmediate; }
 
   bool isModImmNot() const {
@@ -5998,7 +6005,8 @@
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
        !(hasMVE() &&
-         (Mnemonic.startswith("vmine") || Mnemonic.startswith("vshl") ||
+         (Mnemonic.startswith("vmine") ||
+          Mnemonic.startswith("vshl") || Mnemonic.startswith("vrshl") ||
           Mnemonic.startswith("vmvne") || Mnemonic.startswith("vorne") ||
           (Mnemonic.startswith("vnege") && !Mnemonic.startswith("vnegeq")) ||
           (Mnemonic.startswith("vmule") && !Mnemonic.startswith("vmuleq")) ||
@@ -6024,7 +6032,8 @@
         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
-        Mnemonic == "bxns" || Mnemonic == "blxns" ||
+        Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
+        Mnemonic == "vmlas" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;
@@ -6382,6 +6391,9 @@
   if (!hasMVE() || Operands.size() < 3)
     return true;
 
+  if (Mnemonic.startswith("vctp"))
+    return false;
+
   for (auto &Operand : Operands) {
     // We check both QPR and MQPR to more accurately report errors when
     // using Q registers outside of the allowed range.
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -519,6 +519,9 @@
 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
                                           const void *Decoder);
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
 template <int shift>
 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
                                              uint64_t Address,
@@ -533,6 +536,8 @@
                                       uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMveVCMP(MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
                                                   uint64_t Address,
                                                   const void *Decoder);
@@ -6152,6 +6157,18 @@
   return S;
 }
 
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val > 3)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(1 << Val));
+  return S;
+}
+
 template <int shift>
 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
                                              uint64_t Address,
@@ -6398,3 +6415,13 @@
 
   return S;
 }
+
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  return S;
+}
diff --git a/llvm/test/MC/ARM/mve-qdest-rsrc.s b/llvm/test/MC/ARM/mve-qdest-rsrc.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/mve-qdest-rsrc.s
@@ -0,0 +1,602 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOFP: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+vsub.i8 q0, q3, r3
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOFP: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+vsub.i16 q0, q7, lr
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOFP: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+vsub.i32 q1, q5, r10
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOFP: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+vadd.i8 q1, q4, r7
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOFP: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+vadd.i16 q0, q6, r11
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOFP: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+vadd.i32 q0, q1, r6
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOFP: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+vqsub.s8 q2, q2, r8
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOFP: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+vqsub.s16 q1, q4, r0
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOFP: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+vqsub.s32 q0, q2, r0
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+vqsub.u8 q0, q1, r2
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOFP: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+vqsub.u16 q0, q2, r6
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+vqsub.u32 q0, q2, r2
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOFP: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+vqadd.s8 q0, q6, r1
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOFP: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+vqadd.s16 q3, q4, r2
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOFP: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+vqadd.s32 q0, q5, r11
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOFP: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+vqadd.u8 q0, q1, r8
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOFP: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+vqadd.u16 q0, q5, r9
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOFP: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+vqadd.u32 q0, q0, r7
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+vqdmullb.s16 q0, q1, r6
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+vqdmullt.s16 q0, q1, r0
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+vqdmullt.s32 q0, q4, r5
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOFP-NOT: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+vsub.f16 q0, q3, r7
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOFP-NOT: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+vsub.f32 q1, q1, r10
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOFP-NOT: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+vadd.f16 q0, q1, lr
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOFP-NOT: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+vadd.f32 q1, q4, r4
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOFP: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+vhsub.s8 q0, q3, lr
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOFP: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+vhsub.s16 q0, q0, r6
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOFP: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+vhsub.s32 q1, q2, r7
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOFP: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+vhsub.u8 q1, q6, r5
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOFP: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+vhsub.u16 q0, q4, r10
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOFP: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+vhsub.u32 q0, q4, r12
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+vhadd.s8 q0, q2, r1
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+vhadd.s16 q0, q2, r1
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOFP: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+vhadd.s32 q0, q0, r10
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOFP: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+vhadd.u8 q0, q5, lr
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOFP: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+vhadd.u16 q1, q2, r2
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOFP: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+vhadd.u32 q0, q2, r11
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+vqrshl.s8 q0, r0
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+vqrshl.s16 q0, r3
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOFP: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+vqrshl.s32 q0, lr
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+vqrshl.u8 q0, r0
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOFP: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+vqrshl.u16 q0, r2
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+vqrshl.u32 q0, r3
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+vqshl.s8 q0, r0
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOFP: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+vqshl.s16 q1, r1
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+vqshl.s32 q0, r3
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOFP: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+vqshl.u8 q0, r1
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOFP: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+vqshl.u16 q0, r11
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOFP: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+vqshl.u32 q0, lr
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOFP: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+vrshl.s8 q0, r6
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOFP: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+vrshl.s16 q0, lr
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOFP: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+vrshl.s32 q0, r4
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOFP: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+vrshl.u8 q0, r0
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+vrshl.u16 q0, r10
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOFP: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+vrshl.u32 q0, r1
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+vshl.s8 q0, lr
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+vshl.s16 q0, lr
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOFP: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+vshl.s32 q0, r1
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+vshl.u8 q0, r10
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOFP: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+vshl.u16 q1, r10
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOFP: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+vshl.u32 q0, r12
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOFP: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+vbrsr.8 q0, q4, r8
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOFP: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+vbrsr.16 q0, q1, r1
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOFP: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+vbrsr.32 q0, q6, r0
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOFP: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+vmul.i8 q0, q0, r12
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOFP: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+vmul.i16 q0, q4, r7
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOFP: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+vmul.i32 q0, q1, r11
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOFP-NOT: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+vmul.f16 q0, q0, r10
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOFP-NOT: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+vmul.f32 q0, q1, r7
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOFP: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+vqdmulh.s8 q0, q1, r6
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOFP: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+vqdmulh.s16 q0, q2, r2
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOFP: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+vqdmulh.s32 q1, q3, r8
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOFP: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+vqrdmulh.s8 q0, q2, r6
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+vqrdmulh.s16 q0, q0, r2
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+vqrdmulh.s32 q0, q0, r2
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOFP-NOT: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+vfmas.f16 q0, q0, r12
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOFP-NOT: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+vfmas.f32 q0, q3, lr
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+vmlas.s8 q0, q0, r6
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOFP: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+vmlas.s16 q0, q2, r9
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+vmlas.s32 q0, q7, r6
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOFP: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+vmlas.u8 q0, q5, lr
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+vmlas.u16 q0, q3, r12
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOFP: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+vmlas.u32 q1, q1, r11
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOFP-NOT: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+vfma.f16 q1, q1, r6
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOFP-NOT: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+vfmas.f32 q7, q4, r6
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOFP: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+vmla.s8 q0, q3, r8
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+vmla.s16 q1, q3, r10
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOFP: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+vmla.s32 q1, q3, r1
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOFP: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+vmla.u8 q0, q7, r10
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOFP: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+vmla.u16 q0, q0, r7
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOFP: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+vmla.u32 q1, q6, r10
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOFP: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+vqdmlash.s8 q0, q0, r5
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOFP: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+vqdmlash.s16 q0, q5, lr
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOFP: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+vqdmlash.s32 q0, q2, r3
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOFP: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+vqdmlash.u8 q0, q4, r2
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOFP: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+vqdmlash.u16 q1, q4, r2
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOFP: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+vqdmlash.u32 q1, q5, r0
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOFP: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+vqdmlah.s8 q0, q3, r3
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOFP: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+vqdmlah.s16 q5, q3, r9
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOFP: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+vqdmlah.s32 q0, q1, r11
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOFP: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+vqdmlah.u8 q0, q2, lr
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOFP: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+vqdmlah.u16 q0, q3, r10
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOFP: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+vqdmlah.u32 q1, q5, r2
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOFP: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+vqrdmlash.s8 q0, q5, r10
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOFP: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+vqrdmlash.s16 q0, q3, r2
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOFP: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+vqrdmlash.s32 q0, q0, r4
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOFP: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+vqrdmlash.u8 q0, q4, r9
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+vqrdmlash.u16 q0, q6, r12
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOFP: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+vqrdmlash.u32 q0, q3, r7
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+vqrdmlah.s8 q0, q5, r11
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOFP: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+vqrdmlah.s16 q0, q2, r10
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+vqrdmlah.s32 q0, q4, r11
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+vqrdmlah.u8 q0, q4, r2
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOFP: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+vqrdmlah.u16 q0, q6, r1
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+vqrdmlah.u32 q0, q4, r2
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOFP: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+viwdup.u8 q0, lr, r1, #1
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOFP: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+viwdup.u16 q1, r10, r1, #8
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOFP: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+viwdup.u32 q6, r10, r5, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+viwdup.u32 q6, r10, r5, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+viwdup.u32 q6, r3, r5, #4
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOFP: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+vdwdup.u8 q0, r12, r11, #8
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOFP: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+vdwdup.u16 q0, r12, r1, #2
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOFP: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+vdwdup.u32 q0, r0, r7, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vdwdup.u32 q0, r0, r7, #9
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOFP: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+vidup.u8 q0, lr, #2
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOFP: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+vidup.u16 q0, lr, #4
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOFP: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+vidup.u32 q0, r12, #1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vidup.u32 q0, r12, #3
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+vddup.u8 q0, r4, #4
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+vddup.u16 q0, r10, #4
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOFP: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+vddup.u32 q2, r0, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vddup.u32 q2, r0, #5
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+vctp.8 lr
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+vctp.16 r0
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+vctp.32 r10
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+vctp.64 r1
+
+vpste
+vmult.i8 q0, q1, q2
+vmule.i16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+
+vpste
+vmult.i16 q0, q1, q2
+vmule.i16 q1, q2, q3
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+# CHECK-NOFP: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+
+vqrshl.u32 q0, r0
+# CHECK: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+
+vpste
+vqrshlt.u16 q0, r0
+vqrshle.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+# CHECK-NOFP: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+
+vpste
+vrshlt.u16 q0, q1, q2
+vrshle.s32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK-NOFP: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+# CHECK-NOFP: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+
+vpste
+vshlt.s8 q0, r0
+vshle.u32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK-NOFP: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
+# CHECK-NOFP: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
diff --git a/llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt b/llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt
@@ -0,0 +1,531 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x43,0x1f]
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x4e,0x1f]
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x4a,0x3f]
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x47,0x2f]
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x4b,0x0f]
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x46,0x0f]
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x68,0x5f]
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x60,0x3f]
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x60,0x1f]
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x62,0x1f]
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x66,0x1f]
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x62,0x1f]
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x61,0x0f]
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x62,0x6f]
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x6b,0x0f]
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x68,0x0f]
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x69,0x0f]
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xfe,0x67,0x0f]
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x66,0x0f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x60,0x1f]
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x65,0x1f]
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x47,0x1f]
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x4a,0x3f]
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x4e,0x0f]
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x44,0x2f]
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x4e,0x1f]
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x46,0x1f]
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x47,0x3f]
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xfe,0x45,0x3f]
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x4a,0x1f]
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x4c,0x1f]
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x4a,0x0f]
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xfe,0x4e,0x0f]
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x42,0x2f]
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x4b,0x0f]
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0xe0,0x1e]
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0xe3,0x1e]
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0xee,0x1e]
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0xe0,0x1e]
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0xe2,0x1e]
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0xe3,0x1e]
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0xe0,0x1e]
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0xe1,0x3e]
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0xe3,0x1e]
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0xe1,0x1e]
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0xeb,0x1e]
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0xee,0x1e]
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x66,0x1e]
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x6e,0x1e]
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x64,0x1e]
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x60,0x1e]
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x6a,0x1e]
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x61,0x1e]
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x61,0x1e]
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x1e]
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x6a,0x3e]
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0x6c,0x1e]
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xfe,0x68,0x1e]
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x61,0x1e]
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x60,0x1e]
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x6c,0x1e]
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x67,0x1e]
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x6b,0x1e]
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x0e]
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x67,0x0e]
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x66,0x0e]
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x62,0x0e]
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x68,0x2e]
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xfe,0x66,0x0e]
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x62,0x0e]
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xfe,0x62,0x0e]
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4c,0x1e]
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x4e,0x1e]
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x46,0x1e]
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x49,0x1e]
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x46,0x1e]
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x4e,0x1e]
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x4c,0x1e]
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x4b,0x3e]
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x46,0x2e]
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x46,0xfe]
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x48,0x0e]
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xee,0x4a,0x2e]
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x41,0x2e]
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xfe,0x4a,0x0e]
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x47,0x0e]
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x4a,0x2e]
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xee,0x65,0x1e]
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x6e,0x1e]
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x63,0x1e]
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x62,0x1e]
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x62,0x3e]
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x60,0x3e]
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x63,0x0e]
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x69,0xae]
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xee,0x6b,0x0e]
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xfe,0x6e,0x0e]
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfe,0x6a,0x0e]
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x62,0x2e]
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4a,0x1e]
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x42,0x1e]
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x44,0x1e]
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x49,0x1e]
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x4c,0x1e]
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xfe,0x47,0x1e]
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x4a,0x0e]
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x42,0x0e]
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x41,0x0e]
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x42,0x0e]
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x60,0x0f]
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xe1,0x2f]
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0xe4,0xcf]
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0xeb,0x1f]
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x61,0x1f]
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xe7,0x1f]
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x6f,0x0f]
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0xee,0x0f]
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xee,0x6e,0x0f]
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0xee,0x1f]
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xee,0x1f]
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xef,0x5f]
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0e,0xf0,0x01,0xe8]
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x01,0xe8]
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x2a,0xf0,0x01,0xe8]
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x31,0xf0,0x01,0xe8]