diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2380,6 +2380,391 @@
 
 // end of MVE compares
 
+// start of mve_qDest_qSrc
+
+class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
+                     string ops, vpred_ops vpred, string cstr,
+                     list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix,
+          ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b111;
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+}
+
+class VQDMLADH<string iname, bit exch, string suffix, bits<2> size,
+               bit bit_0, bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = exch;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = bit_0;
+}
+
+def VQDMLADHt1xs8  : VQDMLADH<"vqdmladhx", 0b1, "s8", 0b00, 0b0, 0b0>;
+def VQDMLADHt1xs16 : VQDMLADH<"vqdmladhx", 0b1, "s16", 0b01, 0b0, 0b0>;
+def VQDMLADHt1xs32 : VQDMLADH<"vqdmladhx", 0b1, "s32", 0b10, 0b0, 0b0>;
+
+def VQDMLADHt1s8  : VQDMLADH<"vqdmladh", 0b0, "s8", 0b00, 0b0, 0b0>;
+def VQDMLADHt1s16 : VQDMLADH<"vqdmladh", 0b0, "s16", 0b01, 0b0, 0b0>;
+def VQDMLADHt1s32 : VQDMLADH<"vqdmladh", 0b0, "s32", 0b10, 0b0, 0b0>;
+
+def VQDMLADHt2xs8  : VQDMLADH<"vqrdmladhx", 0b1, "s8", 0b00, 0b1, 0b0>;
+def VQDMLADHt2xs16 : VQDMLADH<"vqrdmladhx", 0b1, "s16", 0b01, 0b1, 0b0>;
+def VQDMLADHt2xs32 : VQDMLADH<"vqrdmladhx", 0b1, "s32", 0b10, 0b1, 0b0>;
+
+def VQDMLADHt2s8  : VQDMLADH<"vqrdmladh", 0b0, "s8", 0b00, 0b1, 0b0>;
+def VQDMLADHt2s16 : VQDMLADH<"vqrdmladh", 0b0, "s16", 0b01, 0b1, 0b0>;
+def VQDMLADHt2s32 : VQDMLADH<"vqrdmladh", 0b0, "s32", 0b10, 0b1, 0b0>;
+
+def VQDMLSDHt1xs8  : VQDMLADH<"vqdmlsdhx", 0b1, "s8", 0b00, 0b0, 0b1>;
+def VQDMLSDHt1xs16 : VQDMLADH<"vqdmlsdhx", 0b1, "s16", 0b01, 0b0, 0b1>;
+def VQDMLSDHt1xs32 : VQDMLADH<"vqdmlsdhx", 0b1, "s32", 0b10, 0b0, 0b1>;
+
+def VQDMLSDHt1s8  : VQDMLADH<"vqdmlsdh", 0b0, "s8", 0b00, 0b0, 0b1>;
+def VQDMLSDHt1s16 : VQDMLADH<"vqdmlsdh", 0b0, "s16", 0b01, 0b0, 0b1>;
+def VQDMLSDHt1s32 : VQDMLADH<"vqdmlsdh", 0b0, "s32", 0b10, 0b0, 0b1>;
+
+def VQDMLSDHt2xs8  : VQDMLADH<"vqrdmlsdhx", 0b1, "s8", 0b00, 0b1, 0b1>;
+def VQDMLSDHt2xs16 : VQDMLADH<"vqrdmlsdhx", 0b1, "s16", 0b01, 0b1, 0b1>;
+def VQDMLSDHt2xs32 : VQDMLADH<"vqrdmlsdhx", 0b1, "s32", 0b10, 0b1, 0b1>;
+
+def VQDMLSDHt2s8  : VQDMLADH<"vqrdmlsdh", 0b0, "s8", 0b00, 0b1, 0b1>;
+def VQDMLSDHt2s16 : VQDMLADH<"vqrdmlsdh", 0b0, "s16", 0b01, 0b1, 0b1>;
+def VQDMLSDHt2s32 : VQDMLADH<"vqrdmlsdh", 0b0, "s32", 0b10, 0b1, 0b1>;
+
+class VCMUL<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm, vcmla_rot_imm:$rot),
+                   "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
+  bits<4> Qn;
+  bits<2> rot;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = rot{1};
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = rot{0};
+}
+
+let Predicates = [HasMVEFloat] in {
+  def VCMULt1f16 : VCMUL<"vcmul", "f16", 0b0>;
+  def VCMULt1f32 : VCMUL<"vcmul", "f32", 0b1>;
+}
+
+class VMULL<string iname, string suffix, bit U, bits<2> size, bit T,
+            list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = T;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+multiclass VMULL_half_multi<string iname, string suffix, bit U, bits<2> size> {
+  def bh : VMULL<!strconcat(iname, "b"), suffix, U, size, 0b0>;
+  def th : VMULL<!strconcat(iname, "t"), suffix, U, size, 0b1>;
+}
+
+defm VMULLt1s8  : VMULL_half_multi<"vmull", "s8", 0b0, 0b00>;
+defm VMULLt1s16 : VMULL_half_multi<"vmull", "s16", 0b0, 0b01>;
+defm VMULLt1s32 : VMULL_half_multi<"vmull", "s32", 0b0, 0b10>;
+defm VMULLt1u8  : VMULL_half_multi<"vmull", "u8", 0b1, 0b00>;
+defm VMULLt1u16 : VMULL_half_multi<"vmull", "u16", 0b1, 0b01>;
+defm VMULLt1u32 : VMULL_half_multi<"vmull", "u32", 0b1, 0b10>;
+
+class VMULLp<string iname, string suffix, bit size, bit T,
+             list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                  (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                  vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = T;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+multiclass VMULLp_half_multi<string iname, string suffix, bit size> {
+  def bh : VMULLp<!strconcat(iname, "b"), suffix, size, 0b0>;
+  def th : VMULLp<!strconcat(iname, "t"), suffix, size, 0b1>;
+}
+
+defm VMULLt1p8  : VMULLp_half_multi<"vmull", "p8", 0b0>;
+defm VMULLt1p16 : VMULLp_half_multi<"vmull", "p16", 0b1>;
+
+class VMULH<string iname, string suffix, bit U, bits<2> size,
+            bit bit_12, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b1;
+}
+
+def VMULHt1s8  : VMULH<"vmulh", "s8", 0b0, 0b00, 0b0>;
+def VMULHt1s16 : VMULH<"vmulh", "s16", 0b0, 0b01, 0b0>;
+def VMULHt1s32 : VMULH<"vmulh", "s32", 0b0, 0b10, 0b0>;
+def VMULHt1u8  : VMULH<"vmulh", "u8", 0b1, 0b00, 0b0>;
+def VMULHt1u16 : VMULH<"vmulh", "u16", 0b1, 0b01, 0b0>;
+def VMULHt1u32 : VMULH<"vmulh", "u32", 0b1, 0b10, 0b0>;
+
+def VRMULHt2s8  : VMULH<"vrmulh", "s8", 0b0, 0b00, 0b1>;
+def VRMULHt2s16 : VMULH<"vrmulh", "s16", 0b0, 0b01, 0b1>;
+def VRMULHt2s32 : VMULH<"vrmulh", "s32", 0b0, 0b10, 0b1>;
+def VRMULHt2u8  : VMULH<"vrmulh", "u8", 0b1, 0b00, 0b1>;
+def VRMULHt2u16 : VMULH<"vrmulh", "u16", 0b1, 0b01, 0b1>;
+def VRMULHt2u32 : VMULH<"vrmulh", "u32", 0b1, 0b10, 0b1>;
+
+class VQMOVN<string iname, string suffix, bit U, bits<2> size,
+             bit T, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
+                   vpred_n, "$Qd = $Qd_src", pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b00;
+  let Inst{0} = 0b1;
+}
+
+multiclass VQMOVN_half_multi<string suffix, bit U, bits<2> size> {
+  def bh : VQMOVN<!strconcat("vqmovn", "b"), suffix, U, size, 0b0>;
+  def th : VQMOVN<!strconcat("vqmovn", "t"), suffix, U, size, 0b1>;
+}
+
+defm VQMOVNt1s16 : VQMOVN_half_multi<"s16", 0b0, 0b00>;
+defm VQMOVNt1s32 : VQMOVN_half_multi<"s32", 0b0, 0b01>;
+defm VQMOVNt1u16 : VQMOVN_half_multi<"u16", 0b1, 0b00>;
+defm VQMOVNt1u32 : VQMOVN_half_multi<"u32", 0b1, 0b01>;
+
+class VCVTt1sh<string iname, string suffix, bit op, bit T,
+               list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+                   "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
+  let Inst{28} = op;
+  let Inst{21-16} = 0b111111;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b00;
+  let Inst{0} = 0b1;
+
+  let Predicates = [HasMVEFloat];
+}
+
+multiclass VCVTt1sh_half_multi<string suffix, bit op> {
+  def bh : VCVTt1sh<!strconcat("vcvt", "b"), suffix, op, 0b0>;
+  def th : VCVTt1sh<!strconcat("vcvt", "t"), suffix, op, 0b1>;
+}
+
+defm VCVTt1shf16f32 : VCVTt1sh_half_multi<"f16.f32", 0b0>;
+defm VCVTt1shf32f16 : VCVTt1sh_half_multi<"f32.f16", 0b1>;
+
+class VQMOV<string iname, string suffix, bits<2> size, bit T,
+            bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+                   "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
+  let Inst{28} = bit_28;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b01;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b01;
+  let Inst{0} = 0b1;
+}
+
+multiclass VQMOV_half_multi<string iname, string suffix, bits<2> size,
+                            bit bit_28> {
+  def bh : VQMOV<!strconcat(iname, "b"), suffix, size, 0b0, bit_28>;
+  def th : VQMOV<!strconcat(iname, "t"), suffix, size, 0b1, bit_28>;
+}
+
+defm VQMOVUNs16 : VQMOV_half_multi<"vqmovun", "s16", 0b00, 0b0>;
+defm VQMOVUNs32 : VQMOV_half_multi<"vqmovun", "s32", 0b01, 0b0>;
+
+defm VMOVNi16 : VQMOV_half_multi<"vmovn", "i16", 0b00, 0b1>;
+defm VMOVNi32 : VQMOV_half_multi<"vmovn", "i32", 0b01, 0b1>;
+
+class VMAXAVMINAt2<string iname, string suffix, bits<2> size,
+                   bit bit_12, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111010;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def VMAXAt2s8  : VMAXAVMINAt2<"vmaxa", "s8", 0b00, 0b0>;
+def VMAXAt2s16 : VMAXAVMINAt2<"vmaxa", "s16", 0b01, 0b0>;
+def VMAXAt2s32 : VMAXAVMINAt2<"vmaxa", "s32", 0b10, 0b0>;
+
+def VMINAt2s8  : VMAXAVMINAt2<"vmina", "s8", 0b00, 0b1>;
+def VMINAt2s16 : VMAXAVMINAt2<"vmina", "s16", 0b01, 0b1>;
+def VMINAt2s32 : VMAXAVMINAt2<"vmina", "s32", 0b10, 0b1>;
+
+class VMAXNMVMINNMt2<string iname, string suffix, bit size, bit bit_12,
+                     list<dag> pattern=[]>
+  : MVE_f<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = size;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-16} = 0b111111;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111010;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def VMAXNMAt2f32 : VMAXNMVMINNMt2<"vmaxnma", "f32", 0b0, 0b0>;
+def VMAXNMAt2f16 : VMAXNMVMINNMt2<"vmaxnma", "f16", 0b1, 0b0>;
+
+def VMINNMAt2f32 : VMAXNMVMINNMt2<"vminnma", "f32", 0b0, 0b1>;
+def VMINNMAt2f16 : VMAXNMVMINNMt2<"vminnma", "f16", 0b1, 0b1>;
+
+class VHCADDt1<string iname, string suffix, bits<2> size, bit bit_28,
+               list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm, vcadd_rot_imm:$rot),
+                   "$Qd, $Qn, $Qm, $rot", vpred_r, "",
+          pattern> {
+  bits<4> Qn;
+  bit rot;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = rot;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+def VHCADDt1s8  : VHCADDt1<"vhcadd", "s8", 0b00, 0b0>;
+def VHCADDt1s16 : VHCADDt1<"vhcadd", "s16", 0b01, 0b0>;
+def VHCADDt1s32 : VHCADDt1<"vhcadd", "s32", 0b10, 0b0>;
+
+def VCADDt1i8  : VHCADDt1<"vcadd", "i8", 0b00, 0b1>;
+def VCADDt1i16 : VHCADDt1<"vcadd", "i16", 0b01, 0b1>;
+def VCADDt1i32 : VHCADDt1<"vcadd", "i32", 0b10, 0b1>;
+
+class VADCt1<string iname, bit I, bit bit_28, dag iops, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
+                   !con((ins MQPR:$Qn, MQPR:$Qm), iops),
+                   "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = I;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+
+  let DecoderMethod = "DecodeMveVADCInstruction";
+}
+
+def VADCt1carry : VADCt1<"vadc", 0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
+def VADCt1nocarry : VADCt1<"vadci", 0b1, 0b0, (ins)>;
+
+def VSBCt1carry : VADCt1<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
+def VSBCt1nocarry : VADCt1<"vsbci", 0b1, 0b1, (ins)>;
+
+class VQDMULLt1<string iname, string suffix, bit size, bit T,
+                list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = T;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b1;
+}
+
+multiclass VQDMULLt1_half_multi<string suffix, bit size> {
+  def bh : VQDMULLt1<!strconcat("vqdmull", "b"), suffix, size, 0b0>;
+  def th : VQDMULLt1<!strconcat("vqdmull", "t"), suffix, size, 0b1>;
+}
+
+defm VQDMULLt1s16 : VQDMULLt1_half_multi<"s16", 0b0>;
+defm VQDMULLt1s32 : VQDMULLt1_half_multi<"s32", 0b1>;
+
+// end of mve_qDest_qSrc
+
 class t2VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6003,7 +6003,8 @@
           (Mnemonic.startswith("vnege") && !Mnemonic.startswith("vnegeq")) ||
           (Mnemonic.startswith("vmule") && !Mnemonic.startswith("vmuleq")) ||
           Mnemonic.startswith("vmult") || Mnemonic.startswith("vrintne") ||
-          Mnemonic.startswith("vnegt") || Mnemonic.startswith("vq")))) {
+          Mnemonic.startswith("vnegt") || Mnemonic.startswith("vq") ||
+          Mnemonic.startswith("vcmult") || Mnemonic.startswith("vcmule")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
@@ -6047,7 +6048,10 @@
   if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
       Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
       Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
-      Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vcvt") {
+      Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
+      Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
+      Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
+      Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
     unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
@@ -6702,6 +6706,16 @@
                       ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
       Operands.insert(Operands.begin(),
                       ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
+    } else if (Mnemonic.startswith("vmul") && PredicationCode == ARMCC::LT &&
+               !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+      // Another hack, this time to distinguish between scalar predicated vmul
+      // with 'lt' predication code and the vector instruction vmullt with
+      // vector predication code "none"
+      Operands.erase(Operands.begin() + 1);
+      Operands.erase(Operands.begin());
+      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
     }
     // For vmov and vcmp, as mentioned earlier, we did not add the vector
     // predication code, since these may contain operands that require
@@ -7563,6 +7577,31 @@
                    "list of registers must be at least 1 and at most 16");
     break;
   }
+  case ARM::VQDMULLt1s32bh:
+  case ARM::VQDMULLt1s32th:
+  case ARM::VCMULt1f32:
+  case ARM::VMULLt1s32bh:
+  case ARM::VMULLt1s32th:
+  case ARM::VMULLt1u32bh:
+  case ARM::VMULLt1u32th:
+  case ARM::VQDMLADHt1xs32:
+  case ARM::VQDMLADHt1s32:
+  case ARM::VQDMLADHt2xs32:
+  case ARM::VQDMLADHt2s32:
+  case ARM::VQDMLSDHt1xs32:
+  case ARM::VQDMLSDHt1s32:
+  case ARM::VQDMLSDHt2xs32:
+  case ARM::VQDMLSDHt2s32: {
+    if (Operands[3]->getReg() == Operands[4]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qn register can't be identical");
+    }
+    if (Operands[3]->getReg() == Operands[5]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qm register can't be identical");
+    }
+    break;
+  }
   }
 
   return false;
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -320,6 +320,8 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMveModImmInstruction(MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveVADCInstruction(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
@@ -3477,6 +3479,31 @@
   return S;
 }
 
+static DecodeStatus DecodeMveVADCInstruction(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
+  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+
+  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
+  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
+  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
+    Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+  Inst.addOperand(MCOperand::createImm(Qd));
+
+  return S;
+}
+
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
diff --git a/llvm/test/MC/ARM/mve-qdest-qsrc.s b/llvm/test/MC/ARM/mve-qdest-qsrc.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/mve-qdest-qsrc.s
@@ -0,0 +1,581 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+vcvtt.f64.f16 d0, s0
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+vcvtt.f16.f64 s1, d2
+
+# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+vcvtt.f16.f32 q1, q4
+
+# CHECK: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOFP: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+vqdmladhx.s8 q1, q6, q6
+
+# CHECK: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOFP: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+vqdmladhx.s16 q0, q1, q4
+
+# CHECK: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOFP: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+vqdmladhx.s32 q0, q3, q7
+
+# CHECK: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOFP: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+vqdmladh.s8 q0, q1, q1
+
+# CHECK: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOFP: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+vqdmladh.s16 q0, q2, q2
+
+# CHECK: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOFP: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+vqdmladh.s32 q1, q5, q7
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+vqrdmladhx.s8 q0, q7, q0
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+vqrdmladhx.s16 q0, q0, q1
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+vqrdmladhx.s32 q1, q0, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmladhx.s32 q1, q1, q0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmladhx.s32 q1, q0, q1
+
+# CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+vqrdmladh.s8 q0, q6, q2
+
+# CHECK: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOFP: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+vqrdmladh.s16 q1, q5, q4
+
+# CHECK: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+vqrdmladh.s32 q0, q2, q2
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOFP: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+vqdmlsdhx.s8 q1, q4, q7
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOFP: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+vqdmlsdhx.s16 q0, q2, q5
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOFP: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+vqdmlsdhx.s32 q3, q4, q6
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOFP: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+vqdmlsdh.s8 q0, q3, q6
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOFP: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+vqdmlsdh.s16 q0, q4, q1
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOFP: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+vqdmlsdh.s32 q2, q5, q0
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+vqrdmlsdhx.s8 q0, q3, q1
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+vqrdmlsdhx.s16 q0, q1, q4
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOFP: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+vqrdmlsdhx.s32 q1, q6, q3
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOFP: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+vqrdmlsdh.s8 q3, q3, q0
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+vqrdmlsdh.s16 q0, q7, q4
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+vqrdmlsdh.s32 q0, q6, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmlsdh.s32 q0, q0, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmlsdh.s32 q0, q6, q0
+
+# CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+# CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+vcmul.f16 q0, q1, q2, #90
+
+# CHECK: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+vcmul.f16 q6, q2, q5, #0
+
+# CHECK: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+vcmul.f16 q1, q0, q5, #90
+
+# CHECK: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+vcmul.f16 q1, q0, q5, #180
+
+# CHECK: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+vcmul.f16 q1, q0, q5, #270
+
+# CHECK: vcmul.f16 q1, q0, q1, #270  @ encoding: [0x30,0xee,0x03,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q1, #270  @ encoding: [0x30,0xee,0x03,0x3e]
+vcmul.f16 q1, q0, q1, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmul.f16 q1, q0, q5, #300
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vcmul.f32 q1, q1, q5, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vcmul.f32 q1, q5, q1, #0
+
+# CHECK: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOFP-NOT: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+vcmul.f32 q1, q7, q5, #0
+
+# CHECK: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOFP-NOT: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+vcmul.f32 q3, q4, q2, #90
+
+# CHECK: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOFP-NOT: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+vcmul.f32 q5, q1, q3, #180
+
+# CHECK: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOFP-NOT: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+vcmul.f32 q0, q7, q4, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmul.f32 q1, q0, q5, #300
+
+# CHECK: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOFP: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+vmullb.s8 q2, q6, q0
+
+# CHECK: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOFP: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+vmullb.s16 q3, q4, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vmullb.s32 q3, q4, q3
+
+# CHECK: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOFP: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+vmullb.s32 q3, q5, q6
+
+# CHECK: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+vmullt.s8 q0, q6, q2
+
+# CHECK: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+vmullt.s16 q0, q0, q2
+
+# CHECK: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOFP: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+vmullt.s32 q2, q4, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vmullt.s32 q4, q4, q2
+
+# CHECK: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOFP: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+vmullb.p8 q2, q3, q7
+
+# CHECK: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOFP: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+vmullb.p16 q0, q1, q3
+
+# CHECK: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOFP: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+vmullt.p8 q1, q1, q7
+
+# CHECK: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOFP: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+vmullt.p16 q0, q7, q7
+
+# CHECK: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOFP: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+vmulh.s8 q0, q4, q5
+
+# CHECK: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+vmulh.s16 q0, q7, q4
+
+# CHECK: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+vmulh.s32 q0, q7, q4
+
+# CHECK: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOFP: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+vmulh.u8 q3, q5, q2
+
+# CHECK: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOFP: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+vmulh.u16 q2, q7, q4
+
+# CHECK: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOFP: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+vmulh.u32 q1, q3, q2
+
+# CHECK: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+vrmulh.s8 q1, q1, q2
+
+# CHECK: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+vrmulh.s16 q1, q1, q2
+
+# CHECK: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOFP: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+vrmulh.s32 q3, q1, q0
+
+# CHECK: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOFP: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+vrmulh.u8 q1, q6, q0
+
+# CHECK: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOFP: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+vrmulh.u16 q4, q3, q6
+
+# CHECK: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOFP: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+vrmulh.u32 q1, q2, q2
+
+# CHECK: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOFP: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+vqmovnb.s16 q0, q1
+
+# CHECK: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOFP: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+vqmovnt.s16 q2, q0
+
+# CHECK: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOFP: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+vqmovnb.s32 q0, q5
+
+# CHECK: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOFP: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+vqmovnt.s32 q0, q1
+
+# CHECK: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+vqmovnb.u16 q0, q4
+
+# CHECK: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOFP: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+vqmovnt.u16 q0, q7
+
+# CHECK: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+vqmovnb.u32 q0, q4
+
+# CHECK: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOFP: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+vqmovnt.u32 q0, q2
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+vcvtt.f16.f32 q1, q4
+
+# CHECK: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOFP-NOT: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+vcvtb.f32.f16 q0, q3
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOFP: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+vqmovunb.s16 q0, q3
+
+# CHECK: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOFP: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+vqmovunt.s16 q4, q1
+
+# CHECK: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOFP: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+vqmovunb.s32 q1, q7
+
+# CHECK: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOFP: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+vqmovunt.s32 q0, q2
+
+# CHECK: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOFP: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+vmovnb.i16 q1, q5
+
+# CHECK: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOFP: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+vmovnt.i16 q0, q0
+
+# CHECK: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOFP: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+vmovnb.i32 q1, q0
+
+# CHECK: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOFP: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+vmovnt.i32 q3, q3
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOFP: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+vmaxa.s8 q0, q7
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+vmaxa.s16 q1, q0
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+vmaxa.s32 q1, q0
+
+# CHECK: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+# CHECK-NOFP-NOT: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+vmaxnma.f16 q1, q1
+
+# CHECK: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+# CHECK-NOFP-NOT: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+vmaxnma.f32 q2, q6
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOFP: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+vmina.s8 q1, q7
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOFP: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+vmina.s16 q1, q4
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOFP: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+vmina.s32 q0, q7
+
+# CHECK: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+# CHECK-NOFP-NOT: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+vminnma.f16 q0, q2
+
+# CHECK: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+# CHECK-NOFP-NOT: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+vminnma.f32 q0, q1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+vhcadd.s8 q3, q7, q5, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOFP: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+vhcadd.s16 q3, q1, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s32 q3, q4, q5, #0
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+vhcadd.s32 q3, q4, q5, #90
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOFP: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+vhcadd.s32 q6, q7, q2, #270
+
+# CHECK: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOFP: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+vadc.i32 q1, q0, q2
+
+# CHECK: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOFP: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+vadci.i32 q0, q1, q1
+
+# CHECK: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOFP: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+vcadd.i8 q1, q0, q2, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i8 q1, q0, q2, #0
+
+# CHECK: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOFP: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+vcadd.i16 q0, q2, q3, #90
+
+# CHECK: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOFP: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+vcadd.i16 q0, q5, q5, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i16 q1, q0, q2, #0
+
+# CHECK: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOFP: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+vcadd.i32 q4, q2, q5, #90
+
+# CHECK: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOFP: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+vcadd.i32 q5, q5, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i32 q4, q2, q5, #0
+
+# CHECK: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOFP: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+vsbc.i32 q3, q1, q1
+
+# CHECK: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOFP: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+vsbci.i32 q2, q6, q2
+
+# CHECK: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+vqdmullb.s16 q0, q4, q5
+
+# CHECK: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q6, q5
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+vqdmullt.s32 q0, q7, q5
+
+# CHECK: vqdmullb.s16 q0, q1, q0  @ encoding: [0x32,0xee,0x01,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, q0  @ encoding: [0x32,0xee,0x01,0x0f]
+vqdmullb.s16 q0, q1, q0
+
+# CHECK: vqdmullt.s16 q0, q0, q5  @ encoding: [0x30,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q0, q5  @ encoding: [0x30,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q0, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqdmullb.s32 q0, q1, q0
+
+vqdmullt.s16 q0, q1, q2
+# CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+
+vpste
+vqdmulltt.s32 q0, q1, q2
+vqdmullbe.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK-NOFP: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+# CHECK-NOFP: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+
+vpste
+vmulltt.p8 q0, q1, q2
+vmullbe.p16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK-NOFP: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+# CHECK-NOFP: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+
+# ----------------------------------------------------------------------
+# The following tests have to go last because of the NOFP-NOT checks inside the
+# VPT block.
+
+vpste
+vcmult.f16 q0, q1, q2, #180
+vcmule.f16 q0, q1, q2, #180
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+
+vpstet
+vcvtbt.f16.f32 q0, q1
+vcvtne.s16.f16 q0, q1
+vcvtmt.s16.f16 q0, q1
+# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
+# CHECK: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK-NOFP-NOT: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+# CHECK-NOFP-NOT: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+
+vpte.f32 lt, q3, r1
+vcvttt.f16.f32 q2, q0
+vcvtte.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvttt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK-NOFP-NOT: vcvttt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK: vcvtte.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x3e]
+
+vpte.f32 lt, q3, r1
+vcvtbt.f16.f32 q2, q0
+vcvtbe.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvtbt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK: vcvtbe.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x2e]
+# CHECK-NOFP-NOT: vcvtbe.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x2e]
+
+ite eq
+vcvtteq.f16.f32 s0, s1
+vcvttne.f16.f32 s0, s1
+# CHECK: ite eq                      @ encoding: [0x0c,0xbf]
+# CHECK: vcvtteq.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvtteq.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK: vcvttne.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvttne.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
diff --git a/llvm/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt b/llvm/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt
@@ -0,0 +1,431 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x0c,0x3e]
+
+# CHECK: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x08,0x1e]
+
+# CHECK: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xee,0x0e,0x1e]
+
+# CHECK: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xee,0x02,0x0e]
+
+# CHECK: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x04,0x0e]
+
+# CHECK: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x0e,0x2e]
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x01,0x1e]
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x03,0x1e]
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x09,0x3e]
+
+# CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x05,0x0e]
+
+# CHECK: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x09,0x2e]
+
+# CHECK: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x05,0x0e]
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x0e,0x3e]
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x0a,0x1e]
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x0c,0x7e]
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x0c,0x0e]
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x02,0x0e]
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0x4e]
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x03,0x1e]
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfe,0x09,0x1e]
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x07,0x3e]
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x01,0x6e]
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfe,0x09,0x0e]
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x0f,0x0e]
+
+# CHECK: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xee,0x0a,0xce]
+
+# CHECK: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x2e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0a,0x3e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x3e]
+
+# CHECK: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0a,0x2e]
+
+# CHECK: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x05,0x6e]
+
+# CHECK: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x06,0xbe]
+
+# CHECK: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x09,0x1e]
+
+# CHECK: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x00,0x4e]
+
+# CHECK: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x06,0x6e]
+
+# CHECK: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x0c,0x6e]
+
+# CHECK: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x29,0xee,0x08,0x5e]
+
+# CHECK: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0e,0x4e]
+
+# CHECK: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x06,0x0e]
+
+# CHECK: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x0e,0x3e]
+
+# CHECK: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x0e,0x1e]
+
+# CHECK: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x0b,0x0e]
+
+# CHECK: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x05,0x6e]
+
+# CHECK: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xfe,0x09,0x4e]
+
+# CHECK: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xfe,0x05,0x2e]
+
+# CHECK: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x01,0x7e]
+
+# CHECK: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xfe,0x01,0x3e]
+
+# CHECK: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x0d,0x9e]
+
+# CHECK: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x05,0x3e]
+
+# CHECK: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x03,0x0e]
+
+# CHECK: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x01,0x5e]
+
+# CHECK: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0b,0x0e]
+
+# CHECK: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x03,0x1e]
+
+# CHECK: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x0f,0x1e]
+
+# CHECK: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x05,0x1e]
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x3e]
+
+# CHECK: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x07,0x0e]
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb2,0xee,0xc0,0x0b]
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf3,0xee,0xc2,0x0b]
+
+# CHECK: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x87,0x0e]
+
+# CHECK: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x83,0x9e]
+
+# CHECK: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x8f,0x2e]
+
+# CHECK: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x85,0x1e]
+
+# CHECK: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x8b,0x2e]
+
+# CHECK: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x81,0x1e]
+
+# CHECK: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x81,0x2e]
+
+# CHECK: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x87,0x7e]
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x0e]
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x81,0x2e]
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x81,0x2e]
+
+# CHECK: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x83,0x2e]
+
+# CHECK: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x8d,0x4e]
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x3e]
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x89,0x3e]
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x8f,0x1e]
+
+# CHECK: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x85,0x1e]
+
+# CHECK: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x83,0x1e]
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x00,0x7f]
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xee,0x04,0xdf]
+
+# CHECK: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x04,0x2f]
+
+# CHECK: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x02,0x1f]
+
+# CHECK: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xfe,0x04,0x2f]
+
+# CHECK: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x06,0x0f]
+
+# CHECK: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x0a,0x1f]
+
+# CHECK: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x0a,0x8f]
+
+# CHECK: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0xbf]
+
+# CHECK: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x02,0x6f]
+
+# CHECK: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xfe,0x04,0x5f]
+
+# CHECK: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x0b,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xee,0x0b,0x1f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0b,0x1f]