diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3102,12 +3102,8 @@
     return None;
   }
 
-  const Function &F = MF.getFunction();
-  bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat);
   bool isSoftFloat = Subtarget.useSoftFloat();
-  assert(!(isSoftFloat && NoImplicitFloatOps) &&
-         "SSE register cannot be used when SSE is disabled!");
-  if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1())
+  if (isSoftFloat || !Subtarget.hasSSE1())
     // Kernel mode asks for SSE to be disabled, so there are no XMM argument
     // registers.
     return None;
@@ -3307,11 +3303,6 @@
     FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
   }
 
-  // Figure out if XMM registers are in use.
-  assert(!(Subtarget.useSoftFloat() &&
-           F.hasFnAttribute(Attribute::NoImplicitFloat)) &&
-         "SSE register cannot be used when SSE is disabled!");
-
   // 64-bit calling conventions support varargs and register parameters, so we
   // have to do extra work to spill them in the prologue.
   if (Is64Bit && isVarArg && MFI.hasVAStart()) {
@@ -21743,9 +21734,7 @@
 
   if (ArgMode == 2) {
     // Sanity Check: Make sure using fp_offset makes sense.
-    assert(!Subtarget.useSoftFloat() &&
-           !(MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat)) &&
-           Subtarget.hasSSE1());
+    assert(!Subtarget.useSoftFloat() && Subtarget.hasSSE1());
   }
 
   // Insert VAARG_64 node into the DAG
diff --git a/llvm/test/CodeGen/X86/noimplicitfp-varargs.ll b/llvm/test/CodeGen/X86/noimplicitfp-varargs.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/noimplicitfp-varargs.ll
@@ -0,0 +1,37 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+%struct.__va_list_tag = type { i32, i32, i8*, i8* }
+
+define i32 @testvarargs(i8* nocapture readonly, ...) local_unnamed_addr #0 {
+; CHECK-LABEL: testvarargs
+; Ensure that xmm registers are indeed spilled
+; CHECK: testb %al, %al
+; CHECK: movaps  %xmm0, {{.*}}%rsp
+; CHECK: movaps  %xmm1, {{.*}}%rsp
+; CHECK: movaps  %xmm2, {{.*}}%rsp
+; CHECK: movaps  %xmm3, {{.*}}%rsp
+; CHECK: movaps  %xmm4, {{.*}}%rsp
+; CHECK: movaps  %xmm5, {{.*}}%rsp
+; CHECK: movaps  %xmm6, {{.*}}%rsp
+; CHECK: movaps  %xmm7, {{.*}}%rsp
+
+  %2 = alloca [1 x %struct.__va_list_tag], align 16
+  %3 = bitcast [1 x %struct.__va_list_tag]* %2 to i8*
+  %4 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %2, i64 0, i64 0
+  call void @llvm.va_start(i8* nonnull %3)
+  %5 = call i32 @vprintf(i8* %0, %struct.__va_list_tag* nonnull %4) #4
+  call void @llvm.va_end(i8* nonnull %3)
+  ret i32 %5
+}
+
+declare void @llvm.va_start(i8*) #2
+
+declare i32 @vprintf(i8* nocapture readonly, %struct.__va_list_tag*) local_unnamed_addr #3
+
+declare void @llvm.va_end(i8*) #2
+
+declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
+
+attributes #0 = { noimplicitfloat nounwind ssp uwtable }
+attributes #2 = { nounwind }
+attributes #3 = { noimplicitfloat }
+attributes #4 = { noimplicitfloat }