[MIPS GlobalISel] Lower call for callee that is register

[Petar.Avramovic]

Summary

Lower call for callee that is register for MIPS32.
Register should contain callee function address.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MipsCallLowering.cpp

bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
   const MipsTargetMachine &TM =
       static_cast<const MipsTargetMachine &>(MF.getTarget());
   const MipsABIInfo &ABI = TM.getABI();
 
   MachineInstrBuilder CallSeqStart =
       MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
 
-  // FIXME: Add support for pic calling sequences, long call sequences for O32,
-  //       N32 and N64. First handle the case when Callee.isReg().
-  if (Callee.isReg())
-    return false;
-
-  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
+  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
+      Callee.isReg() ? Mips::JALRPseudo : Mips::JAL);
   MIB.addDef(Mips::SP, RegState::Implicit);
   MIB.add(Callee);
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
 
   TargetLowering::ArgListTy FuncOrigArgs;
   FuncOrigArgs.reserve(OrigArgs.size());
 
bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 
   unsigned NextStackOffset = CCInfo.getNextStackOffset();
   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
   unsigned StackAlignment = TFL->getStackAlignment();
   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
   CallSeqStart.addImm(NextStackOffset).addImm(0);
 
   MIRBuilder.insertInstr(MIB);
+  if (MIB->getOpcode() == Mips::JALRPseudo) {
+    const MipsSubtarget &STI =
+        static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
+    MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
+                         *STI.getRegBankInfo());
+  }
 
   if (OrigRet.Reg) {
 
     ArgInfos.clear();
     SmallVector<unsigned, 8> OrigRetIndices;
 
     splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
 

llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll

define i32 @g(i32 %a0, i32 %a1, i32 %x, i32 %y) {
   ; MIPS32:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
   ; MIPS32:   $v0 = COPY [[ADD]](s32)
   ; MIPS32:   RetRA implicit $v0
 entry:
   %z = call i32 @f(i32 %x, i32 %y)
   %doublez = add i32 %z, %z
   ret i32 %doublez
 }
+
+define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
+  ; MIPS32-LABEL: name: call_reg
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1, $a2
+  ; MIPS32:   [[COPY:%[0-9]+]]:gpr32(p0) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+  ; MIPS32:   $a0 = COPY [[COPY1]](s32)
+  ; MIPS32:   $a1 = COPY [[COPY2]](s32)
+  ; MIPS32:   JALRPseudo [[COPY]](p0), csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY $v0
+  ; MIPS32:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+  ; MIPS32:   $v0 = COPY [[COPY3]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %call = call i32 %f_ptr(i32 %x, i32 %y)
+  ret i32 %call
+}