Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1333,6 +1333,21 @@ // SVE floating-point convert to integer defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">; + // Non-temporal contiguous loads (vector + register) + defm LDNT1SB_ZZR_S : sve2_mem_cldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>; + defm LDNT1B_ZZR_S : sve2_mem_cldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>; + defm LDNT1SH_ZZR_S : sve2_mem_cldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>; + defm LDNT1H_ZZR_S : sve2_mem_cldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>; + defm LDNT1W_ZZR_S : sve2_mem_cldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>; + + defm LDNT1SB_ZZR_D : sve2_mem_cldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>; + defm LDNT1B_ZZR_D : sve2_mem_cldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>; + defm LDNT1SH_ZZR_D : sve2_mem_cldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>; + defm LDNT1H_ZZR_D : sve2_mem_cldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>; + defm LDNT1SW_ZZR_D : sve2_mem_cldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>; + defm LDNT1W_ZZR_D : sve2_mem_cldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>; + defm LDNT1D_ZZR_D : sve2_mem_cldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>; + // Predicated shifts defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -4974,6 +4974,46 @@ (!cast(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; } +class sve2_mem_cldnt_vs_base opc, dag iops, string asm, + RegisterOperand VecList> +: I<(outs VecList:$Zt), iops, + asm, "\t$Zt, $Pg/z, [$Zn, $Rm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rm; + bits<5> Zn; + bits<5> Zt; + let Inst{31} = 0b1; + let Inst{30} = opc{4}; + let Inst{29-25} = 0b00010; + let Inst{24-23} = opc{3-2}; + let Inst{22-21} = 0b00; + let Inst{20-16} = Rm; + let Inst{15} = 0b1; + let Inst{14-13} = opc{1-0}; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zt; + + let mayLoad = 1; +} + +multiclass sve2_mem_cldnt_vs opc, string asm, + RegisterOperand listty, ZPRRegOp zprty> { + def _REAL : sve2_mem_cldnt_vs_base; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; +} + //===----------------------------------------------------------------------===// // SVE Memory - 64-bit Gather Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE/ldnt1b-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ldnt1b-diagnostics.s +++ test/MC/AArch64/SVE/ldnt1b-diagnostics.s @@ -23,12 +23,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1b-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1b-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1b { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1b { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1b { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1b { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1b { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1b { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1b { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1b { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1b { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1b.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1b.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1b z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 84 + +ldnt1b z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 84 + +ldnt1b z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 84 + +ldnt1b z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c4 + +ldnt1b z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c4 + +ldnt1b z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c4 + +ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 84 + +ldnt1b { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 84 + +ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 84 + +ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c4 + +ldnt1b { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c4 + +ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c4 Index: test/MC/AArch64/SVE2/ldnt1d-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1d-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1d { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.s }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.s }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1d { z0.d }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1d { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1d { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1d { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1d { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1d { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1d { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1d.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1d.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1d z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c5 + +ldnt1d z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c5 + +ldnt1d z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c5 + +ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c5 + +ldnt1d { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c5 + +ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c5 Index: test/MC/AArch64/SVE2/ldnt1h-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1h-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1h { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1h { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1h { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1h { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1h { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1h { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1h { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1h { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1h { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1h { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1h.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1h.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1h z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 9f 84 + +ldnt1h z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 9f 84 + +ldnt1h z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 80 84 + +ldnt1h z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c4 + +ldnt1h z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c4 + +ldnt1h z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c4 + +ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 9f 84 + +ldnt1h { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 9f 84 + +ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 80 84 + +ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c4 + +ldnt1h { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c4 + +ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c4 Index: test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sb { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sb { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sb { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1sb { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sb { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sb { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sb { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sb { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sb { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sb { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sb.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sb z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f 84 + +ldnt1sb z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f 84 + +ldnt1sb z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 84 + +ldnt1sb z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c4 + +ldnt1sb z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c4 + +ldnt1sb z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c4 + +ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f 84 + +ldnt1sb { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f 84 + +ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 84 + +ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c4 + +ldnt1sb { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c4 + +ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c4 Index: test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sh { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sh { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sh { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1sh { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sh { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sh { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sh { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sh { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sh { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sh { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sh.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sh z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f 84 + +ldnt1sh z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f 84 + +ldnt1sh z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 84 + +ldnt1sh z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f c4 + +ldnt1sh z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f c4 + +ldnt1sh z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 c4 + +ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f 84 + +ldnt1sh { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f 84 + +ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 84 + +ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f c4 + +ldnt1sh { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f c4 + +ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 c4 Index: test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sw { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.s }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.s }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sw { z0.d }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sw { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1sw { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sw { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sw { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sw { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sw { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sw.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sw.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sw z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c5 + +ldnt1sw z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c5 + +ldnt1sw z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c5 + +ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c5 + +ldnt1sw { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c5 + +ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c5 Index: test/MC/AArch64/SVE2/ldnt1w-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1w-diagnostics.s @@ -0,0 +1,91 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1w { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1w { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1w { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +ldnt1w { z0.d }, p0/m, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.d }, p0/m, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1w { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1w { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1w { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1w { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1w { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1w { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1w.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1w.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1w z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 85 + +ldnt1w z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 85 + +ldnt1w z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 85 + +ldnt1w z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c5 + +ldnt1w z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c5 + +ldnt1w z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c5 + +ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 85 + +ldnt1w { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 85 + +ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 85 + +ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c5 + +ldnt1w { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c5 + +ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c5