Index: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1324,6 +1324,9 @@ // sve_int_rotate_imm defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">; + // SVE2 extract vector (immediate offset, constructive) + def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">; + // Predicated shifts defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; Index: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td @@ -874,6 +874,21 @@ let ElementSize = ElementSizeNone; } +class sve2_int_perm_extract_i_cons +: I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8), + asm, "\t$Zd, $Zn, $imm8", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<8> imm8; + let Inst{31-21} = 0b00000101011; + let Inst{20-16} = imm8{7-3}; + let Inst{15-13} = 0b000; + let Inst{12-10} = imm8{2-0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + //===----------------------------------------------------------------------===// // SVE Vector Select Group //===----------------------------------------------------------------------===// Index: llvm/trunk/test/MC/AArch64/SVE2/ext-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/ext-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/ext-diagnostics.s @@ -0,0 +1,84 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element widths. + +ext z0.h, { z1.h, z2.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.h, { z1.h, z2.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.s, { z1.s, z2.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.s, { z1.s, z2.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.d, { z1.d, z2.d }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.d, { z1.d, z2.d }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid immediate range. + +ext z0.b, { z1.b, z2.b }, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. +// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.b }, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. +// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ext z0.b, { }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ext z0.b, { }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { z1.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.b, z3.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { z1.b, z2.b, z3.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z31.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { v0.4b, v1.4b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +ext z31.b, { z30.b, z31.b }, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/z, z6.b +ext z31.b, { z30.b, z31.b }, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/ext.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/ext.s +++ llvm/trunk/test/MC/AArch64/SVE2/ext.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ext z0.b, { z1.b, z2.b }, #0 +// CHECK-INST: ext z0.b, { z1.b, z2.b }, #0 +// CHECK-ENCODING: [0x20,0x00,0x60,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 00 60 05 + +ext z31.b, { z30.b, z31.b }, #255 +// CHECK-INST: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-ENCODING: [0xdf,0x1f,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 1f 7f 05