Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1289,6 +1289,11 @@ // SVE2 histogram generation (vector) defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">; + // SVE2 floating-point convert precision + defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">; + defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">; + defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">; + // Predicated shifts defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -1436,6 +1436,43 @@ } //===----------------------------------------------------------------------===// +// SVE2 Floating Point Convert Group +//===----------------------------------------------------------------------===// + +class sve2_fp_convert_precision opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn), + asm, "\t$Zd, $Pg/m, $Zn", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<3> Pg; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = opc{3-2}; + let Inst{21-18} = 0b0010; + let Inst{17-16} = opc{1-0}; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_fp_convert_down_narrow { + def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>; + def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>; +} + +multiclass sve2_fp_convert_up_long { + def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>; + def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>; +} + +multiclass sve2_fp_convert_down_odd_rounding { + def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>; +} + +//===----------------------------------------------------------------------===// // SVE Stack Allocation Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE2/fcvtlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtlt-diagnostics.s @@ -0,0 +1,69 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtlt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.h, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.q, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.q, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtlt z0.s, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtlt z0.s, p8/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtlt z0.s, p8/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtlt z0.s, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtlt z0.s, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtlt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtlt z0.s, p0/m, z1.h +// CHECK-INST: fcvtlt z0.s, p0/m, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x89,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 89 64 + +fcvtlt z30.d, p7/m, z31.s +// CHECK-INST: fcvtlt z30.d, p7/m, z31.s +// CHECK-ENCODING: [0xfe,0xbf,0xcb,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf cb 64 Index: test/MC/AArch64/SVE2/fcvtnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtnt-diagnostics.s @@ -0,0 +1,69 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtnt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.b, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.d, p0/m, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtnt z0.h, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtnt z0.h, p8/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtnt z0.h, p8/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtnt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtnt z0.h, p0/m, z1.s +// CHECK-INST: fcvtnt z0.h, p0/m, z1.s +// CHECK-ENCODING: [0x20,0xa0,0x88,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 88 64 + +fcvtnt z30.s, p7/m, z31.d +// CHECK-INST: fcvtnt z30.s, p7/m, z31.d +// CHECK-ENCODING: [0xfe,0xbf,0xca,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf ca 64 Index: test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s @@ -0,0 +1,74 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtxnt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.h, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.b, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.d, p0/m, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtxnt z0.s, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtxnt z0.s, p8/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtxnt z0.s, p8/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtxnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtxnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtxnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtxnt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtxnt z0.s, p0/m, z1.d +// CHECK-INST: fcvtxnt z0.s, p0/m, z1.d +// CHECK-ENCODING: [0x20,0xa0,0x0a,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 0a 64 + +fcvtxnt z30.s, p7/m, z31.d +// CHECK-INST: fcvtxnt z30.s, p7/m, z31.d +// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf 0a 64