Index: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3207,6 +3207,12 @@
                                        FuncInfo->getForwardedMustTailRegParms();
       CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes,
                                                CC_AArch64_AAPCS);
+
+      // Conservatively forward X8, since it might be used for aggregate return.
+      if (!CCInfo.isAllocated(AArch64::X8)) {
+        unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
+        Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
+      }
     }
   }
 
Index: llvm/trunk/test/CodeGen/AArch64/vararg-tallcall.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/vararg-tallcall.ll
+++ llvm/trunk/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -28,7 +28,7 @@
 attributes #1 = { noinline optnone "thunk" }
 
 ; CHECK: mov     v16.16b, v0.16b
-; CHECK: ldr     x8, [x0]
-; CHECK: ldr     x8, [x8]
+; CHECK: ldr     x9, [x0]
+; CHECK: ldr     x9, [x9]
 ; CHECK: mov     v0.16b, v16.16b
-; CHECK: br      x8
+; CHECK: br      x9