Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
@@ -1159,11 +1159,11 @@
   // LDW Rd+1:Rd, P
   //
   // Expands to:
-  // ld Rd,   P+
-  // ld Rd+1, P
+  // ld  Rd,   P
+  // ldd Rd+1, P+1
   let Constraints = "@earlyclobber $reg" in
   def LDWRdPtr : Pseudo<(outs DREGS:$reg),
-                        (ins PTRREGS:$ptrreg),
+                        (ins PTRDISPREGS:$ptrreg),
                         "ldw\t$reg, $ptrreg",
                         [(set i16:$reg, (load i16:$ptrreg))]>,
                  Requires<[HasSRAM]>;
@@ -1230,7 +1230,7 @@
   // ldd Rd,   P+q
   // ldd Rd+1, P+q+1
   let Constraints = "@earlyclobber $dst" in
-  def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z_WORKAROUND:$dst),
+  def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst),
                           (ins memri:$memri),
                           "lddw\t$dst, $memri",
                           [(set i16:$dst, (load addr:$memri))]>,
Index: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
===================================================================
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td
@@ -165,14 +165,14 @@
 // cannot use Z; it's simply a workaround a regalloc bug.
 //
 // More information can be found in PR39553.
-def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8,
+def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8,
   (
     // Return value and arguments.
     add R25R24, R19R18, R21R20, R23R22,
     // Scratch registers.
     R27R26,
     // Callee saved registers.
-    R29R28, R17R16, R15R14, R13R12, R11R10,
+    R17R16, R15R14, R13R12, R11R10,
     R9R8, R7R6, R5R4, R3R2, R1R0
   )>;
 
Index: llvm/trunk/test/CodeGen/AVR/load.ll
===================================================================
--- llvm/trunk/test/CodeGen/AVR/load.ll
+++ llvm/trunk/test/CodeGen/AVR/load.ll
@@ -9,7 +9,7 @@
 
 define i16 @load16(i16* %x) {
 ; CHECK-LABEL: load16:
-; CHECK: ld r24,  [[PTR:[XYZ]]]
+; CHECK: ld r24,  [[PTR:[YZ]]]
 ; CHECK: ldd r25, [[PTR]]+1
   %1 = load i16, i16* %x
   ret i16 %1
@@ -45,10 +45,10 @@
 
 define i16 @load16nodisp(i16* %x) {
 ; CHECK-LABEL: load16nodisp:
-; CHECK: movw r26, r24
-; CHECK: subi r26, 192
-; CHECK: sbci r27, 255
-; CHECK: ld r24,  [[PTR:[XYZ]]]
+; CHECK: movw r30, r24
+; CHECK: subi r30, 192
+; CHECK: sbci r31, 255
+; CHECK: ld r24,  [[PTR:[YZ]]]
 ; CHECK: ldd r25, [[PTR]]+1
   %1 = getelementptr inbounds i16, i16* %x, i64 32
   %2 = load i16, i16* %1
Index: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
===================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
@@ -1,35 +0,0 @@
-# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
-
-# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
-#
-# This test ensures that the pseudo expander can correctly handle the case
-# where we are expanding a 16-bit LDD instruction where the source and
-# destination registers are the same.
-#
-# The instruction itself is earlyclobber and so ISel will never produce an
-# instruction like this, but the stack slot loading can and will.
-
---- |
-  target triple = "avr--"
-  define void @test_lddwrdptrq() {
-  entry:
-    ret void
-  }
-...
-
----
-name:            test_lddwrdptrq
-tracksRegLiveness: true
-body: |
-  bb.0.entry:
-
-    ; CHECK-LABEL: test_lddwrdptrq
-
-    ; CHECK:      ldd [[SCRATCH:r[0-9]+]], Y+10
-    ; CHECK-NEXT: push [[SCRATCH]]
-    ; CHECK-NEXT: ldd [[SCRATCH]], Y+11
-    ; CHECK-NEXT: mov r29, [[SCRATCH]]
-    ; CHECK-NEXT: pop r28
-
-    early-clobber $r29r28 = LDDWRdPtrQ undef $r29r28, 10
-...
Index: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
===================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
@@ -18,8 +18,8 @@
 
     ; CHECK-LABEL: test_lddwrdptrq
 
-    ; CHECK:      ldd     r28, Z+10
-    ; CHECK-NEXT: ldd     r29, Z+11
+    ; CHECK:      ldd     r24, Z+10
+    ; CHECK-NEXT: ldd     r25, Z+11
 
-    early-clobber $r29r28 = LDDWRdPtrQ undef $r31r30, 10
+    early-clobber $r25r24 = LDDWRdPtrQ undef $r31r30, 10
 ...