diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -54,6 +54,9 @@ std::vector &CSI, const TargetRegisterInfo *TRI) const override; + bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; + bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override; + protected: const RISCVSubtarget &STI; diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -110,8 +110,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { - assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); - MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); const RISCVRegisterInfo *RI = STI.getRegisterInfo(); @@ -217,15 +215,25 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); - DebugLoc DL = MBBI->getDebugLoc(); const RISCVInstrInfo *TII = STI.getInstrInfo(); Register FPReg = getFPReg(STI); Register SPReg = getSPReg(STI); + // Get the insert location for the epilogue. If there were no terminators in + // the block, get the last instruction. + MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); + if (MBBI == MBB.end()) + MBBI = MBB.getLastNonDebugInstr(); + DebugLoc DL = MBBI->getDebugLoc(); + + // If this is not a terminator, the actual insert location should be after the + // last instruction. + if (!MBBI->isTerminator()) + MBBI = std::next(MBBI); + // If callee-saved registers are saved via libcall, place stack adjustment // before this call. while (MBBI != MBB.begin() && @@ -599,3 +607,47 @@ return true; } + +bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MBB.getParent()->getInfo(); + + if (!RVFI->useSaveRestoreLibCalls()) + return true; + + // Inserting a call to a __riscv_save libcall requires the use of the register + // t0 (X5) to hold the return address. Therefore if this register is already + // used we can't insert the call. + + RegScavenger RS; + RS.enterBasicBlock(*TmpMBB); + return !RS.isRegUsed(RISCV::X5); +} + +bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MBB.getParent()->getInfo(); + + if (!RVFI->useSaveRestoreLibCalls()) + return true; + + // Using the __riscv_restore libcalls to restore CSRs requires a tail call. + // This means if we still need to continue executing code within this function + // the restore cannot take place in this basic block. + + if (MBB.succ_size() > 1) + return false; + + MachineBasicBlock *SuccMBB = + MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin(); + + // Doing a tail call should be safe if there are no successors, because either + // we have a returning block or the end of the block is unreachable, so the + // restore will be eliminated regardless. + if (!SuccMBB) + return true; + + // The successor can only contain a return, since we would effectively be + // replacing the successor with our own tail return at the end of our block. + return SuccMBB->isReturnBlock() && SuccMBB->size() == 1; +} diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll @@ -0,0 +1,126 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW +; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW +; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \ +; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR + + +declare void @abort() + +define void @eliminate_restore(i32 %n) nounwind { +; RV32I-NOSW-LABEL: eliminate_restore: +; RV32I-NOSW: # %bb.0: +; RV32I-NOSW-NEXT: addi sp, sp, -16 +; RV32I-NOSW-NEXT: sw ra, 12(sp) +; RV32I-NOSW-NEXT: addi a1, zero, 32 +; RV32I-NOSW-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-NOSW-NEXT: # %bb.1: # %if.end +; RV32I-NOSW-NEXT: lw ra, 12(sp) +; RV32I-NOSW-NEXT: addi sp, sp, 16 +; RV32I-NOSW-NEXT: ret +; RV32I-NOSW-NEXT: .LBB0_2: # %if.then +; RV32I-NOSW-NEXT: call abort +; +; RV32I-SW-LABEL: eliminate_restore: +; RV32I-SW: # %bb.0: +; RV32I-SW-NEXT: addi a1, zero, 32 +; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-NEXT: # %bb.1: # %if.end +; RV32I-SW-NEXT: ret +; RV32I-SW-NEXT: .LBB0_2: # %if.then +; RV32I-SW-NEXT: addi sp, sp, -16 +; RV32I-SW-NEXT: sw ra, 12(sp) +; RV32I-SW-NEXT: call abort +; +; RV32I-SW-SR-LABEL: eliminate_restore: +; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: addi a1, zero, 32 +; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-SR-NEXT: # %bb.1: # %if.end +; RV32I-SW-SR-NEXT: ret +; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then +; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 +; RV32I-SW-SR-NEXT: call abort + %cmp = icmp ule i32 %n, 32 + br i1 %cmp, label %if.then, label %if.end + +if.then: + call void @abort() + unreachable + +if.end: + ret void +} + +declare void @notdead(i8*) + +define void @conditional_alloca(i32 %n) nounwind { +; RV32I-NOSW-LABEL: conditional_alloca: +; RV32I-NOSW: # %bb.0: +; RV32I-NOSW-NEXT: addi sp, sp, -16 +; RV32I-NOSW-NEXT: sw ra, 12(sp) +; RV32I-NOSW-NEXT: sw s0, 8(sp) +; RV32I-NOSW-NEXT: addi s0, sp, 16 +; RV32I-NOSW-NEXT: addi a1, zero, 32 +; RV32I-NOSW-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-NOSW-NEXT: # %bb.1: # %if.then +; RV32I-NOSW-NEXT: addi a0, a0, 15 +; RV32I-NOSW-NEXT: andi a0, a0, -16 +; RV32I-NOSW-NEXT: sub a0, sp, a0 +; RV32I-NOSW-NEXT: mv sp, a0 +; RV32I-NOSW-NEXT: call notdead +; RV32I-NOSW-NEXT: .LBB1_2: # %if.end +; RV32I-NOSW-NEXT: addi sp, s0, -16 +; RV32I-NOSW-NEXT: lw s0, 8(sp) +; RV32I-NOSW-NEXT: lw ra, 12(sp) +; RV32I-NOSW-NEXT: addi sp, sp, 16 +; RV32I-NOSW-NEXT: ret +; +; RV32I-SW-LABEL: conditional_alloca: +; RV32I-SW: # %bb.0: +; RV32I-SW-NEXT: addi a1, zero, 32 +; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-NEXT: # %bb.1: # %if.then +; RV32I-SW-NEXT: addi sp, sp, -16 +; RV32I-SW-NEXT: sw ra, 12(sp) +; RV32I-SW-NEXT: sw s0, 8(sp) +; RV32I-SW-NEXT: addi s0, sp, 16 +; RV32I-SW-NEXT: addi a0, a0, 15 +; RV32I-SW-NEXT: andi a0, a0, -16 +; RV32I-SW-NEXT: sub a0, sp, a0 +; RV32I-SW-NEXT: mv sp, a0 +; RV32I-SW-NEXT: call notdead +; RV32I-SW-NEXT: addi sp, s0, -16 +; RV32I-SW-NEXT: lw s0, 8(sp) +; RV32I-SW-NEXT: lw ra, 12(sp) +; RV32I-SW-NEXT: addi sp, sp, 16 +; RV32I-SW-NEXT: .LBB1_2: # %if.end +; RV32I-SW-NEXT: ret +; +; RV32I-SW-SR-LABEL: conditional_alloca: +; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: addi a1, zero, 32 +; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-SR-NEXT: # %bb.1: # %if.then +; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 +; RV32I-SW-SR-NEXT: mv s0, sp +; RV32I-SW-SR-NEXT: addi a0, a0, 15 +; RV32I-SW-SR-NEXT: andi a0, a0, -16 +; RV32I-SW-SR-NEXT: sub a0, sp, a0 +; RV32I-SW-SR-NEXT: mv sp, a0 +; RV32I-SW-SR-NEXT: call notdead +; RV32I-SW-SR-NEXT: mv sp, s0 +; RV32I-SW-SR-NEXT: tail __riscv_restore_1 +; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end +; RV32I-SW-SR-NEXT: ret + %cmp = icmp ule i32 %n, 32 + br i1 %cmp, label %if.then, label %if.end + +if.then: + %addr = alloca i8, i32 %n + call void @notdead(i8* %addr) + br label %if.end + +if.end: + ret void +}