diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -875,10 +875,10 @@ defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; // Predicated shifts - defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; - defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; - defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; - defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; + defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">; + defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">; + defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">; + defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">; defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; @@ -1150,6 +1150,20 @@ defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">; defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">; + // SVE2 saturating/rounding bitwise shift left (predicated) + defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">; + defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">; + defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">; + defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">; + defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">; + defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">; + defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">; + defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">; + defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">; + defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">; + defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">; + defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">; + // SVE2 integer multiply long defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; @@ -1157,4 +1171,11 @@ defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">; defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">; defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">; + + // Predicated shifts + defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; + defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; + defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; + defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; + defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; } diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2926,9 +2926,9 @@ //===----------------------------------------------------------------------===// // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_pred_shift_imm tsz8_64, bits<3> opc, string asm, - ZPRRegOp zprty, Operand immtype, - ElementSizeEnum size> +class sve_int_bin_pred_shift_imm tsz8_64, bits<4> opc, string asm, + ZPRRegOp zprty, Operand immtype, + ElementSizeEnum size> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", "", @@ -2938,8 +2938,8 @@ bits<6> imm; let Inst{31-24} = 0b00000100; let Inst{23-22} = tsz8_64{3-2}; - let Inst{21-19} = 0b000; - let Inst{18-16} = opc; + let Inst{21-20} = 0b00; + let Inst{19-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-8} = tsz8_64{1-0}; @@ -2951,7 +2951,7 @@ let ElementSize = size; } -multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, @@ -2969,7 +2969,7 @@ } } -multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, diff --git a/llvm/test/MC/AArch64/SVE2/sqrshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqrshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqrshl-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqrshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqrshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqrshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sqrshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqrshl.s b/llvm/test/MC/AArch64/SVE2/sqrshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqrshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0a 44 + +sqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4a 44 + +sqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8a 44 + +sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ca 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 ca 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ca 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqrshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqrshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sqrshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqrshlr.s b/llvm/test/MC/AArch64/SVE2/sqrshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqrshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0e 44 + +sqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4e 44 + +sqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8e 44 + +sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ce 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 ce 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ce 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshl-diagnostics.s @@ -0,0 +1,98 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshl z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sqshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqshl.s b/llvm/test/MC/AArch64/SVE2/sqshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshl.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x08,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 08 44 + +sqshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x48,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 48 44 + +sqshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x88,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 88 44 + +sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c8 44 + +sqshl z0.b, p0/m, z0.b, #0 +// CHECK-INST: sqshl z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 06 04 + +sqshl z31.b, p0/m, z31.b, #7 +// CHECK-INST: sqshl z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 06 04 + +sqshl z0.h, p0/m, z0.h, #0 +// CHECK-INST: sqshl z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 06 04 + +sqshl z31.h, p0/m, z31.h, #15 +// CHECK-INST: sqshl z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 06 04 + +sqshl z0.s, p0/m, z0.s, #0 +// CHECK-INST: sqshl z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x46,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 46 04 + +sqshl z31.s, p0/m, z31.s, #31 +// CHECK-INST: sqshl z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x46,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 46 04 + +sqshl z0.d, p0/m, z0.d, #0 +// CHECK-INST: sqshl z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x86,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 86 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c8 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c8 44 + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 diff --git a/llvm/test/MC/AArch64/SVE2/sqshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sqshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqshlr.s b/llvm/test/MC/AArch64/SVE2/sqshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0c 44 + +sqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4c 44 + +sqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8c 44 + +sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cc 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cc 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cc 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqshlu-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqshlu-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshlu-diagnostics.s @@ -0,0 +1,78 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshlu z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshlu z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshlu z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshlu z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +sqshlu z0.b, p0/z, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqshlu z0.b, p0/z, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqshlu.s b/llvm/test/MC/AArch64/SVE2/sqshlu.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/sqshlu.s @@ -0,0 +1,83 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshlu z0.b, p0/m, z0.b, #0 +// CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 0f 04 + +sqshlu z31.b, p0/m, z31.b, #7 +// CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 0f 04 + +sqshlu z0.h, p0/m, z0.h, #0 +// CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 0f 04 + +sqshlu z31.h, p0/m, z31.h, #15 +// CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 0f 04 + +sqshlu z0.s, p0/m, z0.s, #0 +// CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x4f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 4f 04 + +sqshlu z31.s, p0/m, z31.s, #31 +// CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x4f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 4f 04 + +sqshlu z0.d, p0/m, z0.d, #0 +// CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x8f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 8f 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 diff --git a/llvm/test/MC/AArch64/SVE2/srshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/srshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshl-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +srshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/srshl.s b/llvm/test/MC/AArch64/SVE2/srshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x02,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 02 44 + +srshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x42,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 42 44 + +srshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x82,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 82 44 + +srshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c2 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c2 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c2 44 diff --git a/llvm/test/MC/AArch64/SVE2/srshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/srshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +srshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/srshlr.s b/llvm/test/MC/AArch64/SVE2/srshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x06,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 06 44 + +srshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x46,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 46 44 + +srshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x86,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 86 44 + +srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c6 44 diff --git a/llvm/test/MC/AArch64/SVE2/srshr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/srshr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshr-diagnostics.s @@ -0,0 +1,78 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +srshr z18.b, p0/m, z18.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srshr z18.b, p0/m, z18.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z1.b, p0/m, z1.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srshr z1.b, p0/m, z1.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z21.h, p0/m, z21.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srshr z21.h, p0/m, z21.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z14.h, p0/m, z14.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srshr z14.h, p0/m, z14.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z6.s, p0/m, z6.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srshr z6.s, p0/m, z6.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z23.s, p0/m, z23.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srshr z23.s, p0/m, z23.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z3.d, p0/m, z3.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srshr z3.d, p0/m, z3.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z25.d, p0/m, z25.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srshr z25.d, p0/m, z25.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srshr z0.b, p0/m, z1.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srshr z0.b, p0/m, z1.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srshr z0.b, p0/m, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshr z0.b, p0/m, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z0.d, p0/m, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshr z0.d, p0/m, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +srshr z0.b, p0/z, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srshr z0.b, p0/z, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z0.b, p8/m, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srshr z0.b, p8/m, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/srshr.s b/llvm/test/MC/AArch64/SVE2/srshr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/srshr.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshr z0.b, p0/m, z0.b, #1 +// CHECK-INST: srshr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 81 0c 04 + +srshr z31.b, p0/m, z31.b, #8 +// CHECK-INST: srshr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 81 0c 04 + +srshr z0.h, p0/m, z0.h, #1 +// CHECK-INST: srshr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 0c 04 + +srshr z31.h, p0/m, z31.h, #16 +// CHECK-INST: srshr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 82 0c 04 + +srshr z0.s, p0/m, z0.s, #1 +// CHECK-INST: srshr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x4c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 4c 04 + +srshr z31.s, p0/m, z31.s, #32 +// CHECK-INST: srshr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x4c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 4c 04 + +srshr z0.d, p0/m, z0.d, #1 +// CHECK-INST: srshr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 cc 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqrshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqrshl-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqrshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqrshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqrshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uqrshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqrshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/uqrshl.s b/llvm/test/MC/AArch64/SVE2/uqrshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqrshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0b 44 + +uqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4b 44 + +uqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8b 44 + +uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cb 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cb 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cb 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqrshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqrshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uqrshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/uqrshlr.s b/llvm/test/MC/AArch64/SVE2/uqrshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqrshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0f 44 + +uqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4f 44 + +uqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8f 44 + +uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cf 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cf 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cf 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqshl-diagnostics.s @@ -0,0 +1,98 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqshl z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uqshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/uqshl.s b/llvm/test/MC/AArch64/SVE2/uqshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqshl.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x09,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 09 44 + +uqshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x49,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 49 44 + +uqshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x89,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 89 44 + +uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c9 44 + +uqshl z0.b, p0/m, z0.b, #0 +// CHECK-INST: uqshl z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 07 04 + +uqshl z31.b, p0/m, z31.b, #7 +// CHECK-INST: uqshl z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 07 04 + +uqshl z0.h, p0/m, z0.h, #0 +// CHECK-INST: uqshl z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 07 04 + +uqshl z31.h, p0/m, z31.h, #15 +// CHECK-INST: uqshl z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 07 04 + +uqshl z0.s, p0/m, z0.s, #0 +// CHECK-INST: uqshl z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x47,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 47 04 + +uqshl z31.s, p0/m, z31.s, #31 +// CHECK-INST: uqshl z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x47,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 47 04 + +uqshl z0.d, p0/m, z0.d, #0 +// CHECK-INST: uqshl z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x87,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 87 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c9 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c9 44 + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 diff --git a/llvm/test/MC/AArch64/SVE2/uqshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/uqshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uqshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/uqshlr.s b/llvm/test/MC/AArch64/SVE2/uqshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/uqshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0d 44 + +uqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4d 44 + +uqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8d 44 + +uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cd 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cd 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cd 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/urshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshl-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +urshl z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urshl z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/urshl.s b/llvm/test/MC/AArch64/SVE2/urshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x03,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 03 44 + +urshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x43,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 43 44 + +urshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x83,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 83 44 + +urshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c3 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c3 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c3 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshlr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/urshlr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshlr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +urshlr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urshlr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/urshlr.s b/llvm/test/MC/AArch64/SVE2/urshlr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x07,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 07 44 + +urshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x47,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 47 44 + +urshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x87,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 87 44 + +urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c7 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshr-diagnostics.s b/llvm/test/MC/AArch64/SVE2/urshr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshr-diagnostics.s @@ -0,0 +1,78 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +urshr z18.b, p0/m, z18.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: urshr z18.b, p0/m, z18.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z1.b, p0/m, z1.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: urshr z1.b, p0/m, z1.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z21.h, p0/m, z21.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: urshr z21.h, p0/m, z21.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z14.h, p0/m, z14.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: urshr z14.h, p0/m, z14.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z6.s, p0/m, z6.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: urshr z6.s, p0/m, z6.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z23.s, p0/m, z23.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: urshr z23.s, p0/m, z23.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z3.d, p0/m, z3.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: urshr z3.d, p0/m, z3.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z25.d, p0/m, z25.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: urshr z25.d, p0/m, z25.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urshr z0.b, p0/m, z1.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urshr z0.b, p0/m, z1.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urshr z0.b, p0/m, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshr z0.b, p0/m, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z0.d, p0/m, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshr z0.d, p0/m, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +urshr z0.b, p0/z, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urshr z0.b, p0/z, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z0.b, p8/m, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urshr z0.b, p8/m, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/urshr.s b/llvm/test/MC/AArch64/SVE2/urshr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/urshr.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshr z0.b, p0/m, z0.b, #1 +// CHECK-INST: urshr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 81 0d 04 + +urshr z31.b, p0/m, z31.b, #8 +// CHECK-INST: urshr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 81 0d 04 + +urshr z0.h, p0/m, z0.h, #1 +// CHECK-INST: urshr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 0d 04 + +urshr z31.h, p0/m, z31.h, #16 +// CHECK-INST: urshr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 82 0d 04 + +urshr z0.s, p0/m, z0.s, #1 +// CHECK-INST: urshr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x4d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 4d 04 + +urshr z31.s, p0/m, z31.s, #32 +// CHECK-INST: urshr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x4d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 4d 04 + +urshr z0.d, p0/m, z0.d, #1 +// CHECK-INST: urshr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 cd 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04