Index: lib/Target/Mips/MipsCondMov.td =================================================================== --- lib/Target/Mips/MipsCondMov.td +++ lib/Target/Mips/MipsCondMov.td @@ -263,3 +263,31 @@ FGR_64; defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + +// For targets that don't have conditional-move instructions +// we have to match SELECT nodes with pseudo instructions. +let usesCustomInserter = 1, Predicates = [HasNotCondMov] in { + class Select_Pseudo : + PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), + [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>; + + class SelectFP_Pseudo_T : + PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), + [(set RC:$dst, (MipsSelectFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>; + + class SelectFP_Pseudo_F : + PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), + [(set RC:$dst, (MipsSelectFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>; +} + +def PseudoSELECT_I : Select_Pseudo; +def PseudoSELECT_S : Select_Pseudo; +def PseudoSELECT_D32 : Select_Pseudo; + +def PseudoSELECTFP_T_I : SelectFP_Pseudo_T; +def PseudoSELECTFP_T_S : SelectFP_Pseudo_T; +def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T; + +def PseudoSELECTFP_F_I : SelectFP_Pseudo_F; +def PseudoSELECTFP_F_S : SelectFP_Pseudo_F; +def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F; Index: lib/Target/Mips/MipsISelLowering.h =================================================================== --- lib/Target/Mips/MipsISelLowering.h +++ lib/Target/Mips/MipsISelLowering.h @@ -60,6 +60,11 @@ CMovFP_T, CMovFP_F, + // Floating Point Select + // (for targets that don't have conditional-move instructions) + SelectFP_T, + SelectFP_F, + // FP-to-int truncation node. TruncIntFP, @@ -534,6 +539,9 @@ MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const; MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, + MachineBasicBlock *BB, bool isFPCmp, + unsigned Opc) const; }; /// Create MipsTargetLowering objects. Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -125,6 +125,8 @@ case MipsISD::FPCmp: return "MipsISD::FPCmp"; case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; + case MipsISD::SelectFP_T: return "MipsISD::SelectFP_T"; + case MipsISD::SelectFP_F: return "MipsISD::SelectFP_F"; case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; case MipsISD::MFHI: return "MipsISD::MFHI"; case MipsISD::MFLO: return "MipsISD::MFLO"; @@ -525,13 +527,16 @@ // Creates and returns a CMovFPT/F node. static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, - SDValue False, SDLoc DL) { + SDValue False, SDLoc DL, unsigned hasCondMov) { ConstantSDNode *CC = cast(Cond.getOperand(2)); bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); - return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, - True.getValueType(), True, FCC0, False, Cond); + unsigned OpNode = (hasCondMov ? + (invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T) : + (invert ? MipsISD::SelectFP_F : MipsISD::SelectFP_T)); + + return DAG.getNode(OpNode, DL, True.getValueType(), True, FCC0, False, Cond); } static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, @@ -945,6 +950,19 @@ MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), true); case Mips::SEL_D: return emitSEL_D(MI, BB); + + case Mips::PseudoSELECT_I: + case Mips::PseudoSELECT_S: + case Mips::PseudoSELECT_D32: + return emitPseudoSELECT(MI, BB, false, Mips::BNE); + case Mips::PseudoSELECTFP_F_I: + case Mips::PseudoSELECTFP_F_S: + case Mips::PseudoSELECTFP_F_D32: + return emitPseudoSELECT(MI, BB, true, Mips::BC1T); + case Mips::PseudoSELECTFP_T_I: + case Mips::PseudoSELECTFP_T_S: + case Mips::PseudoSELECTFP_T_D32: + return emitPseudoSELECT(MI, BB, true, Mips::BC1F); } } @@ -1543,8 +1561,8 @@ if (Cond.getOpcode() != MipsISD::FPCmp) return Op; - return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), - SDLoc(Op)); + return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), SDLoc(Op), + Subtarget.hasCondMov()); } SDValue MipsTargetLowering:: @@ -1571,7 +1589,8 @@ SDValue True = DAG.getConstant(1, MVT::i32); SDValue False = DAG.getConstant(0, MVT::i32); - return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); + return createCMovFP(DAG, Cond, True, False, SDLoc(Op), + Subtarget.hasCondMov()); } SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, @@ -3716,3 +3735,80 @@ State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); } + +MachineBasicBlock * +MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB, + bool isFPCmp, unsigned Opc) const { + assert(!Subtarget.hasCondMov() && + "Subtarget already supports SELECT nodes with the use of" + "conditional-move instructions."); + + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); + DebugLoc DL = MI->getDebugLoc(); + + // To "insert" a SELECT instruction, we actually have to insert the + // diamond control-flow pattern. The incoming instruction knows the + // destination vreg to set, the condition code register to branch on, the + // true/false values to select between, and a branch opcode to use. + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = BB; + ++It; + + // thisMBB: + // ... + // TrueVal = ... + // setcc r1, r2, r3 + // bNE r1, r0, copy1MBB + // fallthrough --> copy0MBB + MachineBasicBlock *thisMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); + + // Transfer the remainder of BB and its successor edges to sinkMBB. + sinkMBB->splice(sinkMBB->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + sinkMBB->transferSuccessorsAndUpdatePHIs(BB); + + // Next, add the true and fallthrough blocks as its successors. + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + + if (isFPCmp) { + // bc1[tf] cc, sinkMBB + BuildMI(BB, DL, TII->get(Opc)) + .addReg(MI->getOperand(1).getReg()) + .addMBB(sinkMBB); + } else { + // bne rs, $0, sinkMBB + BuildMI(BB, DL, TII->get(Opc)) + .addReg(MI->getOperand(1).getReg()) + .addReg(Mips::ZERO) + .addMBB(sinkMBB); + } + + // copy0MBB: + // %FalseValue = ... + // # fallthrough to sinkMBB + BB = copy0MBB; + + // Update machine-CFG edges + BB->addSuccessor(sinkMBB); + + // sinkMBB: + // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] + // ... + BB = sinkMBB; + + BuildMI(*BB, BB->begin(), DL, + TII->get(Mips::PHI), MI->getOperand(0).getReg()) + .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) + .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + + return BB; +} Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -42,6 +42,10 @@ def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; +def MipsSelectFP_T : SDNode<"MipsISD::SelectFP_T", + SDT_MipsCMovFP, [SDNPInGlue]>; +def MipsSelectFP_F : SDNode<"MipsISD::SelectFP_F", + SDT_MipsCMovFP, [SDNPInGlue]>; def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, [SDNPHasChain, SDNPOptInGlue]>; def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -186,6 +186,7 @@ AssemblerPredicate<"FeatureMips16">; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, AssemblerPredicate<"FeatureCnMips">; +def HasNotCondMov : Predicate<"!Subtarget->hasCondMov()">; def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, AssemblerPredicate<"FeatureMips32">; def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, Index: lib/Target/Mips/MipsSubtarget.h =================================================================== --- lib/Target/Mips/MipsSubtarget.h +++ lib/Target/Mips/MipsSubtarget.h @@ -196,6 +196,10 @@ bool hasCnMips() const { return HasCnMips; } + bool hasCondMov() const { + return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3; + }; + bool isLittle() const { return IsLittle; } bool isABICalls() const { return !NoABICalls; } bool isFPXX() const { return IsFPXX; } Index: test/CodeGen/Mips/llvm-ir/select.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/llvm-ir/select.ll @@ -0,0 +1,582 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 + +define signext i1 @tst_select_i1_i1(i1 signext %s, + i1 signext %x, i1 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i1: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: move $5, $6 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T0]], $5, $[[T0]] + ; SEL: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i1 %x, i1 %y + ret i1 %r +} + +define signext i8 @tst_select_i1_i8(i1 signext %s, + i8 signext %x, i8 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i8: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: move $5, $6 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T0]], $5, $[[T0]] + ; SEL: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i8 %x, i8 %y + ret i8 %r +} + +define signext i32 @tst_select_i1_i32(i1 signext %s, + i32 signext %x, i32 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i32: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: move $5, $6 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T0]], $5, $[[T0]] + ; SEL: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i32 %x, i32 %y + ret i32 %r +} + +define signext i64 @tst_select_i1_i64(i1 signext %s, + i64 signext %x, i64 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i64: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T1:[0-9]+]], {{[0-9]+}}($sp) + ; M2: $[[BB0]]: + ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T2:[0-9]+]], {{[0-9]+}}($sp) + ; M2: $[[BB1]]: + ; M2: move $2, $[[T1]] + ; M2: jr $ra + ; M2: move $3, $[[T2]] + + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: lw $2, {{[0-9]+}}($sp) + ; CMOV-32: movn $2, $6, $[[T0]] + ; CMOV-32: lw $3, {{[0-9]+}}($sp) + ; CMOV-32: movn $3, $7, $[[T0]] + + ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-32: lw $[[T2:[0-9]+]], {{[0-9]+}}($sp) + ; SEL-32: seleqz $[[T2]], $[[T2]], $[[T0]] + ; SEL-32: or $2, $[[T1]], $[[T2]] + ; SEL-32: selnez $[[T3:[0-9]+]], $7, $[[T0]] + ; SEL-32: lw $[[T4:[0-9]+]], {{[0-9]+}}($sp) + ; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; SEL-32: or $3, $[[T3]], $[[T5]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn $6, $5, $[[T0]] + ; CMOV-64: move $2, $6 + + ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-64: sll $[[T0]], $[[T0]], 0 + ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-64: selnez $[[T0]], $5, $[[T0]] + ; SEL-64: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i64 %x, i64 %y + ret i64 %r +} + +define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_i1_float: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: jr $ra + ; M2: mtc1 $6, $f0 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mtc1 $5, $f0 + + ; CMOV-32: mtc1 $6, $f0 + ; CMOV-32: mtc1 $5, $f1 + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: movn.s $f0, $f1, $[[T0]] + + ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] + ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.s $f14, $f13, $[[T0]] + ; CMOV-64: mov.s $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.s $f0, $f14, $f13 + %r = select i1 %s, float %x, float %y + ret float %r +} + +define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_i1_double: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: ldc1 $f0, {{[0-9]+}}($sp) + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: + ; M2: mtc1 $7, $f0 + ; M2: jr $ra + ; M2: mtc1 $6, $f1 + + ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] + ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} + ; CMOV-32R2 mthc1 $6, $[[F0]] + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: ldc1 $f0, {{[0-9]+}}($sp) + ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.d $f14, $f13, $[[T0]] + ; CMOV-64: mov.d $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.d $f0, $f14, $f13 + %r = select i1 %s, double %x, double %y + ret double %r +} + +define float @tst_select_fcmp_olt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_float: + + ; M2: c.olt.s $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.olt.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.olt.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp olt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ole_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_float: + + ; M2: c.ole.s $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.ole.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ole.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ole float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ogt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_float: + + ; M2: c.ule.s $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.ule.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ule.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ogt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oge_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_float: + + ; M2: c.ult.s $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.ult.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ult.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oge float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + + +define float @tst_select_fcmp_oeq_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_float: + + ; M2: c.eq.s $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.eq.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.eq.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.eq.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.eq.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oeq float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_one_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_float: + + ; M2: c.ueq.s $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.s $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.s $f0, $f12 + + ; CMOV-32: c.ueq.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.ueq.s $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ueq.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.ueq.s $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + %s = fcmp one float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + + +define double @tst_select_fcmp_olt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_double: + + ; M2: c.olt.d $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.olt.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.olt.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp olt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ole_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_double: + + ; M2: c.ole.d $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.ole.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ole.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ole double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ogt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_double: + + ; M2: c.ule.d $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.ule.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ule.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ogt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oge_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_double: + + ; M2: c.ult.d $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.ult.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ult.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oge double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + + +define double @tst_select_fcmp_oeq_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_double: + + ; M2: c.eq.d $f12, $f14 + ; M2: bc1f $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.eq.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.eq.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.eq.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.eq.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oeq double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_one_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_double: + + ; M2: c.ueq.d $f12, $f14 + ; M2: bc1t $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: c.ueq.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.ueq.d $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ueq.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.ueq.d $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + + %s = fcmp one double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +}