Index: llvm/include/llvm/Target/TargetSelectionDAG.td
===================================================================
--- llvm/include/llvm/Target/TargetSelectionDAG.td
+++ llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -452,6 +452,8 @@
 
 def lround     : SDNode<"ISD::LROUND"     , SDTFPToIntOp>;
 def llround    : SDNode<"ISD::LLROUND"    , SDTFPToIntOp>;
+def lrint      : SDNode<"ISD::LRINT"      , SDTFPToIntOp>;
+def llrint     : SDNode<"ISD::LLRINT"     , SDTFPToIntOp>;
 
 def fpround    : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fpextend   : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -459,6 +459,8 @@
     setOperationAction(ISD::FMAXIMUM, Ty, Legal);
     setOperationAction(ISD::LROUND, Ty, Legal);
     setOperationAction(ISD::LLROUND, Ty, Legal);
+    setOperationAction(ISD::LRINT, Ty, Legal);
+    setOperationAction(ISD::LLRINT, Ty, Legal);
   }
 
   if (Subtarget->hasFullFP16()) {
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3156,6 +3156,15 @@
   defm FRINT64X : FRIntNNT<0b11, "frint64x">;
 } // HasFRInt3264
 
+def : Pat<(i64 (lrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (lrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (llrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (llrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+
 //===----------------------------------------------------------------------===//
 // Floating point two operand instructions.
 //===----------------------------------------------------------------------===//
Index: llvm/test/CodeGen/AArch64/llrint-conv.ll
===================================================================
--- llvm/test/CodeGen/AArch64/llrint-conv.ll
+++ llvm/test/CodeGen/AArch64/llrint-conv.ll
@@ -1,7 +1,9 @@
 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -10,7 +12,9 @@
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -18,7 +22,9 @@
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
@@ -27,7 +33,9 @@
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-nEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
Index: llvm/test/CodeGen/AArch64/lrint-conv.ll
===================================================================
--- llvm/test/CodeGen/AArch64/lrint-conv.ll
+++ llvm/test/CodeGen/AArch64/lrint-conv.ll
@@ -1,7 +1,9 @@
 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -10,7 +12,9 @@
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -18,7 +22,9 @@
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
@@ -27,7 +33,9 @@
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)