Index: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1113,6 +1113,16 @@ defm SQDMLALBT_ZZZ : sve2_int_mla_long<0b00010, "sqdmlalbt">; defm SQDMLSLBT_ZZZ : sve2_int_mla_long<0b00011, "sqdmlslbt">; + // SVE2 integer halving add/subtract (predicated) + defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd">; + defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd">; + defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub">; + defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub">; + defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd">; + defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd">; + defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr">; + defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr">; + // SVE2 integer multiply long defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; Index: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td @@ -2058,6 +2058,39 @@ } //===----------------------------------------------------------------------===// +// SVE2 Integer - Predicated Group +//===----------------------------------------------------------------------===// + +class sve2_int_arith_pred sz, bits<6> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { + bits<3> Pg; + bits<5> Zm; + bits<5> Zdn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21-20} = 0b01; + let Inst{20-16} = opc{5-1}; + let Inst{15-14} = 0b10; + let Inst{13} = opc{0}; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = zprty.ElementSize; +} + +multiclass sve2_int_arith_pred opc, string asm> { + def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>; + def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>; + def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>; + def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// // SVE2 Widening Integer Arithmetic Group //===----------------------------------------------------------------------===// Index: llvm/trunk/test/MC/AArch64/SVE2/shadd-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shadd-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/shadd-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +shadd z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: shadd z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/shadd.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shadd.s +++ llvm/trunk/test/MC/AArch64/SVE2/shadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x10,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 10 44 + +shadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x50,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 50 44 + +shadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x90,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 90 44 + +shadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d0 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 44 Index: llvm/trunk/test/MC/AArch64/SVE2/shsub-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shsub-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/shsub-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +shsub z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: shsub z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/shsub.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shsub.s +++ llvm/trunk/test/MC/AArch64/SVE2/shsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x12,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 12 44 + +shsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x52,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 52 44 + +shsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x92,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 92 44 + +shsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d2 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d2 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d2 44 Index: llvm/trunk/test/MC/AArch64/SVE2/shsubr-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shsubr-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/shsubr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +shsubr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: shsubr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/shsubr.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/shsubr.s +++ llvm/trunk/test/MC/AArch64/SVE2/shsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x16,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 16 44 + +shsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x56,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 56 44 + +shsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x96,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 96 44 + +shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 44 Index: llvm/trunk/test/MC/AArch64/SVE2/srhadd-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/srhadd-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/srhadd-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +srhadd z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srhadd z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/srhadd.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/srhadd.s +++ llvm/trunk/test/MC/AArch64/SVE2/srhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x14,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 14 44 + +srhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x54,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 54 44 + +srhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x94,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 94 44 + +srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d4 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 44 Index: llvm/trunk/test/MC/AArch64/SVE2/uhadd-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhadd-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhadd-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uhadd z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uhadd z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/uhadd.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhadd.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 11 44 + +uhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 51 44 + +uhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 91 44 + +uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d1 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d1 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d1 44 Index: llvm/trunk/test/MC/AArch64/SVE2/uhsub-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhsub-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhsub-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uhsub z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uhsub z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/uhsub.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhsub.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x13,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 13 44 + +uhsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x53,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 53 44 + +uhsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x93,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 93 44 + +uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d3 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d3 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d3 44 Index: llvm/trunk/test/MC/AArch64/SVE2/uhsubr-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhsubr-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhsubr-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +uhsubr z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uhsubr z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/uhsubr.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/uhsubr.s +++ llvm/trunk/test/MC/AArch64/SVE2/uhsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x17,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 17 44 + +uhsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x57,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 57 44 + +uhsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x97,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 97 44 + +uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 44 Index: llvm/trunk/test/MC/AArch64/SVE2/urhadd-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/urhadd-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE2/urhadd-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate + +urhadd z0.b, p0/z, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urhadd z0.b, p0/z, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE2/urhadd.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE2/urhadd.s +++ llvm/trunk/test/MC/AArch64/SVE2/urhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x15,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 15 44 + +urhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x55,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 55 44 + +urhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x95,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 95 44 + +urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d5 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 44