Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -37,6 +37,8 @@ // different. bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; } + Optional getFixupKind(StringRef Name) const override; + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -46,12 +46,19 @@ }; } // end anonymous namespace +Optional ARMAsmBackend::getFixupKind(StringRef Name) const { + if (Name == "R_ARM_NONE") + return (MCFixupKind)ARM::fixup_arm_NONE; + return MCAsmBackend::getFixupKind(Name); +} + const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { // This table *must* be in the order that the fixup_* kinds are defined in // ARMFixupKinds.h. // // Name Offset (bits) Size (bits) Flags + {"fixup_arm_NONE", 0, 0, 0}, {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | @@ -103,6 +110,7 @@ // ARMFixupKinds.h. // // Name Offset (bits) Size (bits) Flags + {"fixup_arm_NONE", 0, 0, 0}, {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | @@ -383,6 +391,7 @@ default: Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type"); return 0; + case ARM::fixup_arm_NONE: case FK_Data_1: case FK_Data_2: case FK_Data_4: @@ -761,7 +770,9 @@ const MCSymbolRefExpr *A = Target.getSymA(); const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; const unsigned FixupKind = Fixup.getKind() ; - if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { + if (FixupKind == ARM::fixup_arm_NONE) + return true; + if (FixupKind == ARM::fixup_arm_thumb_bl) { assert(Sym && "How did we resolve this?"); // If the symbol is external the linker will handle it. @@ -803,6 +814,9 @@ default: llvm_unreachable("Unknown fixup kind!"); + case ARM::fixup_arm_NONE: + return 0; + case FK_Data_1: case ARM::fixup_arm_thumb_bcc: case ARM::fixup_arm_thumb_cp: @@ -857,6 +871,9 @@ default: llvm_unreachable("Unknown fixup kind!"); + case ARM::fixup_arm_NONE: + return 0; + case FK_Data_1: return 1; case FK_Data_2: Index: lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -196,6 +196,8 @@ case MCSymbolRefExpr::VK_ARM_TLSDESCSEQ: return ELF::R_ARM_TLS_DESCSEQ; } + case ARM::fixup_arm_NONE: + return ELF::R_ARM_NONE; case ARM::fixup_arm_condbranch: case ARM::fixup_arm_uncondbranch: return ELF::R_ARM_JUMP24; Index: lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h +++ lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h @@ -14,8 +14,11 @@ namespace llvm { namespace ARM { enum Fixups { + // Fixup resulting in R_ARM_NONE. + fixup_arm_NONE = FirstTargetFixupKind, + // 12-bit PC relative relocation for symbol addresses - fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind, + fixup_arm_ldst_pcrel_12, // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered. fixup_t2_ldst_pcrel_12, Index: test/MC/ARM/reloc-directive.s =================================================================== --- /dev/null +++ test/MC/ARM/reloc-directive.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc -triple=armv7-linux-gnueabi %s | FileCheck --check-prefix=PRINT %s +# RUN: llvm-mc -triple=armv7eb-linux-gnueabi %s | FileCheck --check-prefix=PRINT %s + +# RUN: llvm-mc -filetype=obj -triple=armv7-linux-gnueabi %s -o %t +# RUN: llvm-readobj -r %t | FileCheck %s +# RUN: llvm-readelf -x .data %t | FileCheck --check-prefix=HEX %s + +# RUN: llvm-mc -filetype=obj -triple=armv7eb-linux-gnueabi %s -o %t +# RUN: llvm-readobj -r %t | FileCheck %s +# RUN: llvm-readelf -x .data %t | FileCheck --check-prefix=HEX %s + +.text + bx lr + nop + nop + .reloc 8, R_ARM_NONE, .data + .reloc 4, R_ARM_NONE, foo+4 + .reloc 0, R_ARM_NONE, 8 + +.data +.globl foo +foo: + .word 0 + .word 0 + .word 0 + +# PRINT: .reloc 8, R_ARM_NONE, .data +# PRINT: .reloc 4, R_ARM_NONE, foo+4 +# PRINT: .reloc 0, R_ARM_NONE, 8 + +# ARM relocations use the Elf32_Rela format. Addends are neither stored in the +# relocation entries nor applied in the referenced locations. +# CHECK: 0x8 R_ARM_NONE .data 0x0 +# CHECK-NEXT: 0x4 R_ARM_NONE foo 0x0 +# CHECK-NEXT: 0x0 R_ARM_NONE - 0x0 + +# HEX: 0x00000000 00000000 00000000