Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -41,12 +41,15 @@
     return AArch64::NumTargetFixupKinds;
   }
 
+  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
+
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
         // This table *must* be in the order that the fixup_* kinds are defined
         // in AArch64FixupKinds.h.
         //
         // Name                           Offset (bits) Size (bits)     Flags
+        {"fixup_aarch64_NONE", 0, 0, 0},
         {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
         {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
         {"fixup_aarch64_add_imm12", 10, 12, 0},
@@ -103,6 +106,7 @@
   default:
     llvm_unreachable("Unknown fixup kind!");
 
+  case AArch64::fixup_aarch64_NONE:
   case AArch64::fixup_aarch64_tlsdesc_call:
     return 0;
 
@@ -304,6 +308,7 @@
     if (Value & 0x3)
       Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
     return (Value >> 2) & 0x3ffffff;
+  case AArch64::fixup_aarch64_NONE:
   case FK_Data_1:
   case FK_Data_2:
   case FK_Data_4:
@@ -314,6 +319,12 @@
   }
 }
 
+Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
+  if (Name == "R_AARCH64_NONE")
+    return (MCFixupKind)AArch64::fixup_aarch64_NONE;
+  return MCAsmBackend::getFixupKind(Name);
+}
+
 /// getFixupKindContainereSizeInBytes - The number of bytes of the
 /// container involved in big endian or 0 if the item is little endian
 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
@@ -445,6 +456,10 @@
 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
                                               const MCFixup &Fixup,
                                               const MCValue &Target) {
+  unsigned Kind = Fixup.getKind();
+  if (Kind == AArch64::fixup_aarch64_NONE)
+    return true;
+
   // The ADRP instruction adds some multiple of 0x1000 to the current PC &
   // ~0xfff. This means that the required offset to reach a symbol can vary by
   // up to one step depending on where the ADRP is in memory. For example:
@@ -457,14 +472,14 @@
   // same page as the ADRP and the instruction should encode 0x0. Assuming the
   // section isn't 0x1000-aligned, we therefore need to delegate this decision
   // to the linker -- a relocation!
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
+  if (Kind == AArch64::fixup_aarch64_pcrel_adrp_imm21)
     return true;
 
   AArch64MCExpr::VariantKind RefKind =
       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   // LDR GOT relocations need a relocation
-  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
+  if (Kind == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
       SymLoc == AArch64MCExpr::VK_GOT)
     return true;
   return false;
Index: lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -200,6 +200,8 @@
         return ELF::R_AARCH64_NONE;
       } else
         return ELF::R_AARCH64_ABS64;
+    case AArch64::fixup_aarch64_NONE:
+      return ELF::R_AARCH64_NONE;
     case AArch64::fixup_aarch64_add_imm12:
       if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
         return R_CLS(TLSLD_ADD_DTPREL_HI12);
Index: lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
+++ lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
@@ -15,8 +15,11 @@
 namespace AArch64 {
 
 enum Fixups {
+  // Fixups resulting in R_AARCH64_NONE.
+  fixup_aarch64_NONE = FirstTargetFixupKind,
+
   // A 21-bit pc-relative immediate inserted into an ADR instruction.
-  fixup_aarch64_pcrel_adr_imm21 = FirstTargetFixupKind,
+  fixup_aarch64_pcrel_adr_imm21,
 
   // A 21-bit pc-relative immediate inserted into an ADRP instruction.
   fixup_aarch64_pcrel_adrp_imm21,
Index: test/MC/AArch64/reloc-directive.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/reloc-directive.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -filetype=obj -triple=aarch64 %s | llvm-readobj -r | FileCheck %s
+
+.data
+  .reloc 8, R_AARCH64_NONE, .data
+  .reloc 4, R_AARCH64_NONE, .data+4
+  .reloc 0, R_AARCH64_NONE, 8
+  .word 0
+  .word 0
+  .word 0
+
+# CHECK:      0x8 R_AARCH64_NONE .data 0x0
+# CHECK-NEXT: 0x4 R_AARCH64_NONE .data 0x4
+# CHECK-NEXT: 0x0 R_AARCH64_NONE - 0x8