Index: lib/Analysis/ScalarEvolutionExpander.cpp =================================================================== --- lib/Analysis/ScalarEvolutionExpander.cpp +++ lib/Analysis/ScalarEvolutionExpander.cpp @@ -750,6 +750,15 @@ } } + // Add wrapping flags. + if (isa(Sum) && !isa(Sum)) { + auto *I = cast(Sum); + if (S->hasNoUnsignedWrap()) + I->setHasNoUnsignedWrap(); + if (S->hasNoSignedWrap()) + I->setHasNoSignedWrap(); + } + return Sum; } Index: test/Transforms/IRCE/bad_expander.ll =================================================================== --- test/Transforms/IRCE/bad_expander.ll +++ test/Transforms/IRCE/bad_expander.ll @@ -89,7 +89,7 @@ ; CHECK: entry: ; CHECK-NEXT: %num = load i64, i64* %p1, align 4 ; CHECK-NEXT: [[DIV:%[^ ]+]] = udiv i64 %num, 13 -; CHECK-NEXT: [[DIV_MINUS_1:%[^ ]+]] = add i64 [[DIV]], -1 +; CHECK-NEXT: [[DIV_MINUS_1:%[^ ]+]] = add nsw i64 [[DIV]], -1 ; CHECK-NEXT: [[COMP1:%[^ ]+]] = icmp sgt i64 [[DIV_MINUS_1]], 0 ; CHECK-NEXT: %exit.mainloop.at = select i1 [[COMP1]], i64 [[DIV_MINUS_1]], i64 0 ; CHECK-NEXT: [[COMP2:%[^ ]+]] = icmp slt i64 0, %exit.mainloop.at Index: test/Transforms/IRCE/conjunctive-checks.ll =================================================================== --- test/Transforms/IRCE/conjunctive-checks.ll +++ test/Transforms/IRCE/conjunctive-checks.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: @f_0( ; CHECK: loop.preheader: -; CHECK: [[len_sub:[^ ]+]] = add i32 %len, -4 +; CHECK: [[len_sub:[^ ]+]] = add nsw i32 %len, -4 ; CHECK: [[exit_main_loop_at_hiclamp_cmp:[^ ]+]] = icmp slt i32 %n, [[len_sub]] ; CHECK: [[exit_main_loop_at_hiclamp:[^ ]+]] = select i1 [[exit_main_loop_at_hiclamp_cmp]], i32 %n, i32 [[len_sub]] ; CHECK: [[exit_main_loop_at_loclamp_cmp:[^ ]+]] = icmp sgt i32 [[exit_main_loop_at_hiclamp]], 0 Index: test/Transforms/IRCE/decrementing-loop.ll =================================================================== --- test/Transforms/IRCE/decrementing-loop.ll +++ test/Transforms/IRCE/decrementing-loop.ll @@ -33,7 +33,7 @@ ; CHECK: [[len_hiclamp:[^ ]+]] = select i1 [[len_hiclamp_cmp]], i32 %len, i32 %n ; CHECK: [[not_exit_preloop_at_cmp:[^ ]+]] = icmp sgt i32 [[len_hiclamp]], 0 ; CHECK: [[not_exit_preloop_at:[^ ]+]] = select i1 [[not_exit_preloop_at_cmp]], i32 [[len_hiclamp]], i32 0 -; CHECK: %exit.preloop.at = add i32 [[not_exit_preloop_at]], -1 +; CHECK: %exit.preloop.at = add nsw i32 [[not_exit_preloop_at]], -1 } ; Make sure that we can eliminate the range check when the loop looks like: Index: test/Transforms/IRCE/ranges_of_different_types.ll =================================================================== --- test/Transforms/IRCE/ranges_of_different_types.ll +++ test/Transforms/IRCE/ranges_of_different_types.ll @@ -23,7 +23,7 @@ ; CHECK-NOT: preloop ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = add i32 %len, -13 +; CHECK-NEXT: [[SUB1:%[^ ]+]] = add nsw i32 %len, -13 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp slt i32 [[SUB1]], 101 ; CHECK-NEXT: [[SMAX:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp sgt i32 [[SMAX]], 0 @@ -79,10 +79,10 @@ ; CHECK-LABEL: test_02( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[LEN_MINUS_SMAX:%[^ ]+]] = add i32 %len, -2147483647 +; CHECK-NEXT: [[LEN_MINUS_SMAX:%[^ ]+]] = add nuw nsw i32 %len, -2147483647 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[LEN_MINUS_SMAX]], -13 ; CHECK-NEXT: [[SMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[LEN_MINUS_SMAX]], i32 -13 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 %len, [[SMAX1]] +; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub nuw nsw i32 %len, [[SMAX1]] ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp slt i32 [[SUB1]], 101 ; CHECK-NEXT: [[SMAX2:%[^ ]+]] = select i1 [[CMP2]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: [[CMP3:%[^ ]+]] = icmp sgt i32 [[SMAX2]], 0 @@ -202,7 +202,7 @@ ; CHECK-LABEL: test_04( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = add i32 %len, 13 +; CHECK-NEXT: [[SUB1:%[^ ]+]] = add nuw i32 %len, 13 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp ult i32 [[SUB1]], 101 ; CHECK-NEXT: %exit.mainloop.at = select i1 [[CMP1]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: br i1 true, label %loop.preloop.preheader @@ -245,7 +245,7 @@ ; CHECK-NOT: preloop ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = add i32 %len, -13 +; CHECK-NEXT: [[SUB1:%[^ ]+]] = add nsw i32 %len, -13 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp slt i32 [[SUB1]], 101 ; CHECK-NEXT: [[SMAX:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp sgt i32 [[SMAX]], 0 @@ -286,10 +286,10 @@ ; CHECK-LABEL: test_06( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[LEN_MINUS_SMAX:%[^ ]+]] = add i32 %len, -2147483647 +; CHECK-NEXT: [[LEN_MINUS_SMAX:%[^ ]+]] = add nuw nsw i32 %len, -2147483647 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[LEN_MINUS_SMAX]], -13 ; CHECK-NEXT: [[SMAX1:%[^ ]+]] = select i1 [[CMP1]], i32 [[LEN_MINUS_SMAX]], i32 -13 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 %len, [[SMAX1]] +; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub nuw nsw i32 %len, [[SMAX1]] ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp slt i32 [[SUB1]], 101 ; CHECK-NEXT: [[SMAX2:%[^ ]+]] = select i1 [[CMP2]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: [[CMP3:%[^ ]+]] = icmp sgt i32 [[SMAX2]], 0 @@ -375,7 +375,7 @@ ; CHECK-LABEL: test_08( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 -; CHECK-NEXT: [[SUB1:%[^ ]+]] = add i32 %len, 13 +; CHECK-NEXT: [[SUB1:%[^ ]+]] = add nuw i32 %len, 13 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp ult i32 [[SUB1]], 101 ; CHECK-NEXT: %exit.mainloop.at = select i1 [[CMP1]], i32 [[SUB1]], i32 101 ; CHECK-NEXT: br i1 true, label %loop.preloop.preheader Index: test/Transforms/IRCE/rc-negative-bound.ll =================================================================== --- test/Transforms/IRCE/rc-negative-bound.ll +++ test/Transforms/IRCE/rc-negative-bound.ll @@ -115,7 +115,7 @@ ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[BOUND:%.*]], -2147483647 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 0 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[BOUND]], [[SMIN]] +; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 [[BOUND]], [[SMIN]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[BOUND]], 0 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP3]], i32 [[BOUND]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[SMAX]], -1 @@ -403,7 +403,7 @@ ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[BOUND:%.*]], -2147483647 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 0 ; CHECK-NEXT: [[SMIN:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[BOUND]], [[SMIN]] +; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 [[BOUND]], [[SMIN]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[BOUND]], 0 ; CHECK-NEXT: [[SMAX:%.*]] = select i1 [[TMP3]], i32 [[BOUND]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[SMAX]], -1 Index: test/Transforms/IRCE/single-access-no-preloop.ll =================================================================== --- test/Transforms/IRCE/single-access-no-preloop.ll +++ test/Transforms/IRCE/single-access-no-preloop.ll @@ -86,7 +86,7 @@ ; CHECK-LABEL: @single_access_no_preloop_with_offset( ; CHECK: loop.preheader: -; CHECK: [[safe_range_end:[^ ]+]] = add i32 %len, -4 +; CHECK: [[safe_range_end:[^ ]+]] = add nsw i32 %len, -4 ; CHECK: [[exit_main_loop_at_hiclamp_cmp:[^ ]+]] = icmp slt i32 %n, [[safe_range_end]] ; CHECK: [[exit_main_loop_at_hiclamp:[^ ]+]] = select i1 [[exit_main_loop_at_hiclamp_cmp]], i32 %n, i32 [[safe_range_end]] ; CHECK: [[exit_main_loop_at_loclamp_cmp:[^ ]+]] = icmp sgt i32 [[exit_main_loop_at_hiclamp]], 0 Index: test/Transforms/IRCE/single-access-with-preloop.ll =================================================================== --- test/Transforms/IRCE/single-access-with-preloop.ll +++ test/Transforms/IRCE/single-access-with-preloop.ll @@ -41,16 +41,16 @@ ; CHECK: [[exit_preloop_at:[^ ]+]] = select i1 [[exit_preloop_at_cond]], i32 [[exit_preloop_at_loclamp]], i32 0 -; CHECK: [[len_minus_sint_max:[^ ]+]] = add i32 %len, -2147483647 +; CHECK: [[len_minus_sint_max:[^ ]+]] = add nuw nsw i32 %len, -2147483647 ; CHECK: [[check_len_min_sint_offset:[^ ]+]] = icmp sgt i32 %offset, [[len_minus_sint_max]] ; CHECK: [[safe_offset_mainloop:[^ ]+]] = select i1 [[check_len_min_sint_offset]], i32 %offset, i32 [[len_minus_sint_max]] ; If Offset was a SINT_MIN, we could have an overflow here. That is why we calculated its safe version. -; CHECK: [[safe_upper_end:[^ ]+]] = sub i32 %len, [[safe_offset_mainloop]] +; CHECK: [[safe_upper_end:[^ ]+]] = sub nsw i32 %len, [[safe_offset_mainloop]] ; CHECK: [[exit_mainloop_at_cond_loclamp:[^ ]+]] = icmp slt i32 %n, [[safe_upper_end]] ; CHECK: [[exit_mainloop_at_loclamp:[^ ]+]] = select i1 [[exit_mainloop_at_cond_loclamp]], i32 %n, i32 [[safe_upper_end]] ; CHECK: [[check_offset_mainloop_2:[^ ]+]] = icmp sgt i32 %offset, 0 ; CHECK: [[safe_offset_mainloop_2:[^ ]+]] = select i1 [[check_offset_mainloop_2]], i32 %offset, i32 0 -; CHECK: [[safe_lower_end:[^ ]+]] = sub i32 2147483647, [[safe_offset_mainloop_2]] +; CHECK: [[safe_lower_end:[^ ]+]] = sub nsw i32 2147483647, [[safe_offset_mainloop_2]] ; CHECK: [[exit_mainloop_at_cond_hiclamp:[^ ]+]] = icmp slt i32 [[exit_mainloop_at_loclamp]], [[safe_lower_end]] ; CHECK: [[exit_mainloop_at_hiclamp:[^ ]+]] = select i1 [[exit_mainloop_at_cond_hiclamp]], i32 [[exit_mainloop_at_loclamp]], i32 [[safe_lower_end]] ; CHECK: [[exit_mainloop_at_cmp:[^ ]+]] = icmp sgt i32 [[exit_mainloop_at_hiclamp]], 0 Index: test/Transforms/IRCE/stride_more_than_1.ll =================================================================== --- test/Transforms/IRCE/stride_more_than_1.ll +++ test/Transforms/IRCE/stride_more_than_1.ll @@ -254,7 +254,7 @@ ; CHECK: @test_05( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr -; CHECK-NEXT: %exit.preloop.at = add i32 %len, -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 %len, -1 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp sgt i32 100, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: loop.preloop.preheader: @@ -320,7 +320,7 @@ ; CHECK: @test_06( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr -; CHECK-NEXT: %exit.preloop.at = add i32 %len, -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 %len, -1 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 2147483640, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: loop.preloop.preheader: @@ -415,7 +415,7 @@ ; CHECK: @test_08( ; CHECK: entry: ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr -; CHECK-NEXT: %exit.preloop.at = add i32 %len, -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 %len, -1 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 2147483647, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: loop.preloop.preheader: Index: test/Transforms/IRCE/unsigned_comparisons_ugt.ll =================================================================== --- test/Transforms/IRCE/unsigned_comparisons_ugt.ll +++ test/Transforms/IRCE/unsigned_comparisons_ugt.ll @@ -59,7 +59,7 @@ ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1 ; CHECK-NEXT: [[UMIN:%[^ ]+]] = select i1 [[COND1]], i32 %len, i32 1 -; CHECK-NEXT: %exit.preloop.at = add i32 [[UMIN]], -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 [[UMIN]], -1 ; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ugt i32 100, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND2]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: mainloop: @@ -150,7 +150,7 @@ ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1 ; CHECK-NEXT: [[UMIN:%[^ ]+]] = select i1 [[COND1]], i32 %len, i32 1 -; CHECK-NEXT: %exit.preloop.at = add i32 [[UMIN]], -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 [[UMIN]], -1 ; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ugt i32 -2147483648, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND2]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: mainloop: Index: test/Transforms/IRCE/unsigned_comparisons_ult.ll =================================================================== --- test/Transforms/IRCE/unsigned_comparisons_ult.ll +++ test/Transforms/IRCE/unsigned_comparisons_ult.ll @@ -62,7 +62,7 @@ ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1 ; CHECK-NEXT: [[UMIN:%[^ ]+]] = select i1 [[COND1]], i32 %len, i32 1 -; CHECK-NEXT: %exit.preloop.at = add i32 [[UMIN]], -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 [[UMIN]], -1 ; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ugt i32 100, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND2]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: mainloop: @@ -195,7 +195,7 @@ ; CHECK-NEXT: %len = load i32, i32* %a_len_ptr, !range !0 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1 ; CHECK-NEXT: [[UMIN:%[^ ]+]] = select i1 [[COND1]], i32 %len, i32 1 -; CHECK-NEXT: %exit.preloop.at = add i32 [[UMIN]], -1 +; CHECK-NEXT: %exit.preloop.at = add nsw i32 [[UMIN]], -1 ; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ugt i32 -2147483648, %exit.preloop.at ; CHECK-NEXT: br i1 [[COND2]], label %loop.preloop.preheader, label %preloop.pseudo.exit ; CHECK: mainloop: Index: test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll =================================================================== --- test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll +++ test/Transforms/IndVarSimplify/lftr-udiv-tripcount.ll @@ -15,7 +15,7 @@ ; CHECK: loop.preheader: ; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[N]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[TMP0]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i8 [[TMP1]], 1 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[I1:%.*]] = phi i8 [ [[I1_INC:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ] Index: test/Transforms/IndVarSimplify/loop_evaluate_1.ll =================================================================== --- test/Transforms/IndVarSimplify/loop_evaluate_1.ll +++ test/Transforms/IndVarSimplify/loop_evaluate_1.ll @@ -25,7 +25,7 @@ ; CHECK-LABEL: @test2 ; CHECK: [[VAR1:%.+]] = add i32 %arg, -11 ; CHECK: [[VAR2:%.+]] = lshr i32 [[VAR1]], 1 -; CHECK: [[VAR3:%.+]] = add i32 [[VAR2]], 1 +; CHECK: [[VAR3:%.+]] = add nuw i32 [[VAR2]], 1 ; CHECK: [[VAR4:%.+]] = phi i32 [ 0, %bb ], [ [[VAR3]], %bb1.preheader ] ; CHECK: ret i32 [[VAR4]] define i32 @test2(i32 %arg) { Index: test/Transforms/LoopStrengthReduce/X86/nested-loop.ll =================================================================== --- test/Transforms/LoopStrengthReduce/X86/nested-loop.ll +++ test/Transforms/LoopStrengthReduce/X86/nested-loop.ll @@ -14,7 +14,7 @@ ; CHECK-NEXT: [[CMP215:%.*]] = icmp sgt i32 [[SIZE:%.*]], 1 ; CHECK-NEXT: [[T0:%.*]] = zext i32 [[SIZE]] to i64 ; CHECK-NEXT: [[T1:%.*]] = sext i32 [[NSTEPS:%.*]] to i64 -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[T0]], -1 +; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[T0]], -1 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[FOR_INC:%.*]] ], [ 1, [[ENTRY:%.*]] ] Index: test/Transforms/LoopVectorize/AArch64/pr36032.ll =================================================================== --- test/Transforms/LoopVectorize/AArch64/pr36032.ll +++ test/Transforms/LoopVectorize/AArch64/pr36032.ll @@ -29,7 +29,7 @@ ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] ; CHECK: vector.scevcheck: -; CHECK-NEXT: [[TMP2:%.*]] = sub i64 3, [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i64 3, [[TMP0]] ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[G_0]], [[CONV]] ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 [[TMP4]]) Index: test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll =================================================================== --- test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll +++ test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll @@ -27,7 +27,7 @@ ; CHECK: for.body3.lr.ph.us.preheader: ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[M]], -1 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[K:%.*]] to i64 ; CHECK-NEXT: br label [[FOR_BODY3_LR_PH_US:%.*]] ; CHECK: for.end.us: