Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -437,9 +437,6 @@
   switch (MI->getOpcode()) {
   default: break;
 
-  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
@@ -670,10 +667,6 @@
   default: break;
 
   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
-  case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
-
   case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
   case AMDGPU::V_CNDMASK_B32_e32_vi:
     if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
Index: lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP2Instructions.td
+++ lib/Target/AMDGPU/VOP2Instructions.td
@@ -190,16 +190,16 @@
   }
 }
 
-class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
-                      string OpName, string opnd> :
-  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
+class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst, string OpName> :
+  InstAlias <OpName#" "#!subst(", vcc", "", ps.Pfl.Asm32),
              (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
                    ps.Pfl.Src1RC32:$src1)>,
   PredicateControl {
 }
 
+// Make vcc operands optional
 multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
-    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
+  def : VOP2bInstAlias<ps, inst, OpName>;
 }
 
 multiclass VOP2eInst <string opName,
@@ -852,7 +852,7 @@
       VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
       VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
         VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
-        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
+        let AsmString = asmName # Ps.AsmOperands;
       }
     def _e64_gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
@@ -1340,13 +1340,18 @@
 
 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
 
+} // End SubtargetPredicate = isGFX8GFX9
+
+let SubtargetPredicate = isGFX9Only in {
+
 defm : VOP2bInstAliases<V_ADD_I32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
 defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
 defm : VOP2bInstAliases<V_SUB_I32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
 defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
 defm : VOP2bInstAliases<V_SUBREV_I32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
 defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
-} // End SubtargetPredicate = isGFX8GFX9
+
+} // End SubtargetPredicate = isGFX9Only
 
 let SubtargetPredicate = HasDLInsts in {
 
Index: test/MC/AMDGPU/vop3-gfx9.s
===================================================================
--- test/MC/AMDGPU/vop3-gfx9.s
+++ test/MC/AMDGPU/vop3-gfx9.s
@@ -491,6 +491,57 @@
 // GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00]
 // NOVI: error:
 
+v_addc_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38]
+// NOVI: error: instruction not supported on this GPU
+
+v_subb_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a]
+// NOVI: error: instruction not supported on this GPU
+
+v_subbrev_co_u32 v84, vcc, v13, v31, vcc
+// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c]
+// NOVI: error: instruction not supported on this GPU
+
+v_add_co_u32 v84, vcc, v13, v31
+// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32]
+// NOVI: error: instruction not supported on this GPU
+
+v_sub_co_u32 v84, vcc, v13, v31
+// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34]
+// NOVI: error: instruction not supported on this GPU
+
+v_subrev_co_u32 v84, vcc, v13, v31
+// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
+// NOVI: error: instruction not supported on this GPU
+
+// vcc operands may be omitted
+
+v_addc_co_u32 v84, v13, v31
+// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38]
+// NOVI: error: instruction not supported on this GPU
+
+v_subb_co_u32 v84, v13, v31
+// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a]
+// NOVI: error: instruction not supported on this GPU
+
+v_subbrev_co_u32 v84, v13, v31
+// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c]
+// NOVI: error: instruction not supported on this GPU
+
+v_add_co_u32 v84, v13, v31
+// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32]
+// NOVI: error: instruction not supported on this GPU
+
+v_sub_co_u32 v84, v13, v31
+// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34]
+// NOVI: error: instruction not supported on this GPU
+
+v_subrev_co_u32 v84, v13, v31
+// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
+// NOVI: error: instruction not supported on this GPU
+
+
 //===----------------------------------------------------------------------===//
 // Validate register size checks (bug 37943)
 //===----------------------------------------------------------------------===//