Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1034,4 +1034,21 @@ // SVE2 saturating multiply-add high (vectors, unpredicated) defm SQRDMLAH_ZZZ : sve2_int_mla<0b0, "sqrdmlah">; defm SQRDMLSH_ZZZ : sve2_int_mla<0b1, "sqrdmlsh">; + + // SVE2 integer multiply (indexed) + defm MUL_ZZZI : sve2_int_mul_by_indexed_elem<0b1110, "mul">; + + // SVE2 saturating multiply high (indexed) + defm SQDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1100, "sqdmulh">; + defm SQRDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1101, "sqrdmulh">; + + // SVE2 signed saturating doubling multiply high (unpredicated) + defm SQDMULH_ZZZ : sve2_int_mul<0b100, "sqdmulh">; + defm SQRDMULH_ZZZ : sve2_int_mul<0b101, "sqrdmulh">; + + // SVE2 integer multiply vectors (unpredicated) + defm MUL_ZZZ : sve2_int_mul<0b000, "mul">; + defm SMULH_ZZZ : sve2_int_mul<0b010, "smulh">; + defm UMULH_ZZZ : sve2_int_mul<0b011, "umulh">; + def PMUL_ZZZ_B : sve2_int_mul<0b00, 0b001, "pmul", ZPR8>; } Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -1838,6 +1838,75 @@ } //===----------------------------------------------------------------------===// +// SVE2 Integer Multiply - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve2_int_mul sz, bits<3> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b011; + let Inst{12-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_mul opc, string asm> { + def _B : sve2_int_mul<0b00, opc, asm, ZPR8>; + def _H : sve2_int_mul<0b01, opc, asm, ZPR16>; + def _S : sve2_int_mul<0b10, opc, asm, ZPR32>; + def _D : sve2_int_mul<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer Multiply - Indexed Group +//===----------------------------------------------------------------------===// + +class sve2_int_mul_by_indexed_elem sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + ZPRRegOp zprty3, Operand itype> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop), + asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-14} = 0b11; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_mul_by_indexed_elem opc, string asm> { + def _H : sve2_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{22} = iop{2}; + let Inst{20-19} = iop{1-0}; + let Inst{18-16} = Zm; + } + def _S : sve2_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve2_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { + bits<4> Zm; + bit iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Unary Predicated Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE2/mul-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mul-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mul z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mul z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mul z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mul z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mul z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mul z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mul z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mul z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +mul z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mul.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mul.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mul z0.b, z1.b, z2.b +// CHECK-INST: mul z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x60,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 22 04 + +mul z0.h, z1.h, z2.h +// CHECK-INST: mul z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x60,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 62 04 + +mul z29.s, z30.s, z31.s +// CHECK-INST: mul z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x63,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 63 bf 04 + +mul z31.d, z31.d, z31.d +// CHECK-INST: mul z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x63,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 63 ff 04 + +mul z0.h, z1.h, z7.h[7] +// CHECK-INST: mul z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf8,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 7f 44 + +mul z0.s, z1.s, z7.s[3] +// CHECK-INST: mul z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 bf 44 + +mul z0.d, z1.d, z15.d[1] +// CHECK-INST: mul z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf8,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 ff 44 Index: test/MC/AArch64/SVE2/pmul-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmul-diagnostics.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmul z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmul z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmul z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +pmul z0.b, z1.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmul z0.b, z1.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +pmul z0.b, z1.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmul z0.b, z1.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmul.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmul.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pmul z0.b, z1.b, z2.b +// CHECK-INST: pmul z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x64,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 22 04 + +pmul z29.b, z30.b, z31.b +// CHECK-INST: pmul z29.b, z30.b, z31.b +// CHECK-ENCODING: [0xdd,0x67,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 67 3f 04 Index: test/MC/AArch64/SVE2/smulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smulh-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +smulh z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +smulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smulh.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +smulh z0.b, z1.b, z2.b +// CHECK-INST: smulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x68,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 22 04 + +smulh z0.h, z1.h, z2.h +// CHECK-INST: smulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x68,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 62 04 + +smulh z29.s, z30.s, z31.s +// CHECK-INST: smulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x6b,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 6b bf 04 + +smulh z31.d, z31.d, z31.d +// CHECK-INST: smulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6b,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6b ff 04 Index: test/MC/AArch64/SVE2/sqdmulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmulh-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmulh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqdmulh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmulh z0.b, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.b, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.h, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.h, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +sqdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmulh.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqdmulh z0.b, z1.b, z2.b +// CHECK-INST: sqdmulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x70,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 22 04 + +sqdmulh z0.h, z1.h, z2.h +// CHECK-INST: sqdmulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x70,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 62 04 + +sqdmulh z29.s, z30.s, z31.s +// CHECK-INST: sqdmulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x73,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 73 bf 04 + +sqdmulh z31.d, z31.d, z31.d +// CHECK-INST: sqdmulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x73,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 73 ff 04 + +sqdmulh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqdmulh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf0,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 7f 44 + +sqdmulh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqdmulh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf0,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 bf 44 + +sqdmulh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqdmulh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf0,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 ff 44 Index: test/MC/AArch64/SVE2/sqrdmulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmulh-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmulh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmulh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqrdmulh z0.b, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.b, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.h, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.h, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqrdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqrdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmulh.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrdmulh z0.b, z1.b, z2.b +// CHECK-INST: sqrdmulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x74,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 22 04 + +sqrdmulh z0.h, z1.h, z2.h +// CHECK-INST: sqrdmulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x74,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 62 04 + +sqrdmulh z29.s, z30.s, z31.s +// CHECK-INST: sqrdmulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x77,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 77 bf 04 + +sqrdmulh z31.d, z31.d, z31.d +// CHECK-INST: sqrdmulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x77,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 77 ff 04 + +sqrdmulh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmulh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf4,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 7f 44 + +sqrdmulh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmulh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf4,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 bf 44 + +sqrdmulh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmulh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf4,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 ff 44 Index: test/MC/AArch64/SVE2/umulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umulh-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +umulh z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +umulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umulh.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +umulh z0.b, z1.b, z2.b +// CHECK-INST: umulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x6c,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 22 04 + +umulh z0.h, z1.h, z2.h +// CHECK-INST: umulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x6c,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 62 04 + +umulh z29.s, z30.s, z31.s +// CHECK-INST: umulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 6f bf 04 + +umulh z31.d, z31.d, z31.d +// CHECK-INST: umulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6f,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6f ff 04