Index: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td +++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td @@ -560,7 +560,9 @@ if (!Operands[i]->isDivergent() && !isInlineImmediate(Operands[i].getNode())) { ConstantBusUses++; - if (ConstantBusUses >= 2) + // This uses AMDGPU::V_ADD3_U32, but all three operand instructions + // have the same constant bus limit. + if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32)) return false; } } @@ -625,6 +627,7 @@ let SubtargetPredicate = isGFX10Plus in { def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile>; + def : ThreeOp_i32_Pats; } // End SubtargetPredicate = isGFX10Plus //===----------------------------------------------------------------------===// Index: llvm/trunk/test/CodeGen/AMDGPU/add3.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/add3.ll +++ llvm/trunk/test/CodeGen/AMDGPU/add3.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_ADD3_U32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -36,6 +42,12 @@ ; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4 ; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: mad_no_add3: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4 +; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0 +; GFX10-NEXT: ; return to shader part epilog %a0 = shl i32 %a, 8 %a1 = lshr i32 %a0, 8 %b0 = shl i32 %b, 8 @@ -69,6 +81,11 @@ ; GFX9-NEXT: s_add_i32 s3, s3, s2 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_vgpr_b: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -86,6 +103,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_vgpr_all2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %b, %c %result = add i32 %a, %x %bc = bitcast i32 %result to float @@ -103,6 +125,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_vgpr_bc: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -120,6 +147,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, 16 %bc = bitcast i32 %result to float @@ -139,6 +171,12 @@ ; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_multiuse_outer: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2 +; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 +; GFX10-NEXT: ; return to shader part epilog %inner = add i32 %a, %b %outer = add i32 %inner, %c %x1 = mul i32 %outer, %x @@ -160,6 +198,12 @@ ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v0, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_multiuse_inner: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2 +; GFX10-NEXT: ; return to shader part epilog %inner = add i32 %a, %b %outer = add i32 %inner, %c %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0 @@ -190,6 +234,15 @@ ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add3_uniform_vgpr: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0 +; GFX10-NEXT: v_add_f32_e64 v2, s2, 1.0 +; GFX10-NEXT: v_add_f32_e64 v0, 0x40400000, s4 +; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v0 +; GFX10-NEXT: ; return to shader part epilog %a1 = fadd float %a, 1.0 %b2 = fadd float %b, 2.0 %c3 = fadd float %c, 3.0 Index: llvm/trunk/test/CodeGen/AMDGPU/add_shl.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/add_shl.ll +++ llvm/trunk/test/CodeGen/AMDGPU/add_shl.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_ADD_LSHL_U32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -35,6 +41,11 @@ ; GFX9-NEXT: s_add_i32 s2, s2, s3 ; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl_vgpr_c: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -52,6 +63,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl_vgpr_ac: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -69,6 +85,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -87,6 +108,11 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl_vgpr_const_inline_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, 1012 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -108,6 +134,11 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, 0x600 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: add_shl_vgpr_inline_const_x2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600 +; GFX10-NEXT: ; return to shader part epilog %x = add i32 %a, 3 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float Index: llvm/trunk/test/CodeGen/AMDGPU/and_or.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/and_or.ll +++ llvm/trunk/test/CodeGen/AMDGPU/and_or.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_AND_OR_B32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -36,6 +42,11 @@ ; GFX9-NEXT: v_and_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_or_b32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or_vgpr_b: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -53,6 +64,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or_vgpr_ab: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -70,6 +86,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 4, %a %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -88,6 +109,11 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, 0x808 ; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or_vgpr_const_inline_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 20, %a %result = or i32 %x, 2056 %bc = bitcast i32 %result to float @@ -105,6 +131,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: and_or_vgpr_inline_const_x2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1 +; GFX10-NEXT: ; return to shader part epilog %x = and i32 4, %a %result = or i32 %x, 1 %bc = bitcast i32 %result to float Index: llvm/trunk/test/CodeGen/AMDGPU/or3.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/or3.ll +++ llvm/trunk/test/CodeGen/AMDGPU/or3.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_OR3_B32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: or3: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -37,6 +43,11 @@ ; GFX9-NEXT: v_or_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_or_b32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: or3_vgpr_a: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -54,6 +65,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: or3_vgpr_all2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 +; GFX10-NEXT: ; return to shader part epilog %x = or i32 %b, %c %result = or i32 %a, %x %bc = bitcast i32 %result to float @@ -71,6 +87,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_or3_b32 v0, s2, v0, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: or3_vgpr_bc: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1 +; GFX10-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -88,6 +109,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: or3_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64 +; GFX10-NEXT: ; return to shader part epilog %x = or i32 64, %b %result = or i32 %x, %a %bc = bitcast i32 %result to float Index: llvm/trunk/test/CodeGen/AMDGPU/shl_add.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/shl_add.ll +++ llvm/trunk/test/CodeGen/AMDGPU/shl_add.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_LSHL_ADD_U32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_add: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -36,6 +42,11 @@ ; GFX9-NEXT: v_lshlrev_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_add_vgpr_a: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -53,6 +64,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_add_vgpr_all: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -70,6 +86,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_add_vgpr_ab: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -87,6 +108,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_add_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, 3 %result = add i32 %x, %b %bc = bitcast i32 %result to float Index: llvm/trunk/test/CodeGen/AMDGPU/shl_or.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/shl_or.ll +++ llvm/trunk/test/CodeGen/AMDGPU/shl_or.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_LSHL_OR_B32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -35,6 +41,11 @@ ; GFX9-NEXT: s_lshl_b32 s0, s2, s3 ; GFX9-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_c: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, s2, s3, v0 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -52,6 +63,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_all2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %c, %x %bc = bitcast i32 %result to float @@ -69,6 +85,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, s2, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_ac: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, s2, v1 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -86,6 +107,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, 6 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, 6 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, 6 %bc = bitcast i32 %result to float @@ -103,6 +129,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_const2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, v1 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -120,6 +151,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, s2, 6, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_const_scalar1: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, s2, 6, v0 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -137,6 +173,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, s2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: shl_or_vgpr_const_scalar2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, s2 +; GFX10-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float Index: llvm/trunk/test/CodeGen/AMDGPU/xor3.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/xor3.ll +++ llvm/trunk/test/CodeGen/AMDGPU/xor3.ll @@ -0,0 +1,167 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s + +; =================================================================================== +; V_XOR3_B32 +; =================================================================================== + +define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) { +; GFX9-LABEL: xor3: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog + %x = xor i32 %a, %b + %result = xor i32 %x, %c + %bc = bitcast i32 %result to float + ret float %bc +} + +define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { +; GFX9-LABEL: xor3_vgpr_b: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 +; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_vgpr_b: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, s2, v0, s3 +; GFX10-NEXT: ; return to shader part epilog + %x = xor i32 %a, %b + %result = xor i32 %x, %c + %bc = bitcast i32 %result to float + ret float %bc +} + +define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) { +; GFX9-LABEL: xor3_vgpr_all2: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_vgpr_all2: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v0 +; GFX10-NEXT: ; return to shader part epilog + %x = xor i32 %b, %c + %result = xor i32 %a, %x + %bc = bitcast i32 %result to float + ret float %bc +} + +define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { +; GFX9-LABEL: xor3_vgpr_bc: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_vgpr_bc: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v1 +; GFX10-NEXT: ; return to shader part epilog + %x = xor i32 %a, %b + %result = xor i32 %x, %c + %bc = bitcast i32 %result to float + ret float %bc +} + +define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) { +; GFX9-LABEL: xor3_vgpr_const: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v0, 16, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 16 +; GFX10-NEXT: ; return to shader part epilog + %x = xor i32 %a, %b + %result = xor i32 %x, 16 + %bc = bitcast i32 %result to float + ret float %bc +} + +define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) { +; GFX9-LABEL: xor3_multiuse_outer: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_multiuse_outer: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 +; GFX10-NEXT: ; return to shader part epilog + %inner = xor i32 %a, %b + %outer = xor i32 %inner, %c + %x1 = mul i32 %outer, %x + %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0 + %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1 + %bc = bitcast <2 x i32> %r0 to <2 x float> + ret <2 x float> %bc +} + +define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) { +; GFX9-LABEL: xor3_multiuse_inner: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_multiuse_inner: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2 +; GFX10-NEXT: ; return to shader part epilog + %inner = xor i32 %a, %b + %outer = xor i32 %inner, %c + %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0 + %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1 + %bc = bitcast <2 x i32> %r0 to <2 x float> + ret <2 x float> %bc +} + +; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here, +; but we don't. +define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) { +; GFX9-LABEL: xor3_uniform_vgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000 +; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0 +; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0 +; GFX9-NEXT: v_add_f32_e32 v2, s4, v2 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor3_uniform_vgpr: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0 +; GFX10-NEXT: v_add_f32_e64 v2, s2, 1.0 +; GFX10-NEXT: v_add_f32_e64 v0, 0x40400000, s4 +; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1 +; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 +; GFX10-NEXT: ; return to shader part epilog + %a1 = fadd float %a, 1.0 + %b2 = fadd float %b, 2.0 + %c3 = fadd float %c, 3.0 + %bc.a = bitcast float %a1 to i32 + %bc.b = bitcast float %b2 to i32 + %bc.c = bitcast float %c3 to i32 + %x = xor i32 %bc.a, %bc.b + %result = xor i32 %x, %bc.c + %bc = bitcast i32 %result to float + ret float %bc +} Index: llvm/trunk/test/CodeGen/AMDGPU/xor_add.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/xor_add.ll +++ llvm/trunk/test/CodeGen/AMDGPU/xor_add.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s +; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_XAD_U32 @@ -17,6 +18,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor_add: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -36,6 +42,11 @@ ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor_add_vgpr_a: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xad_u32 v0, v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -53,6 +64,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor_add_vgpr_all: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 +; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -70,6 +86,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, s2 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor_add_vgpr_ab: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xad_u32 v0, v0, v1, s2 +; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -87,6 +108,11 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, 3, v1 ; GFX9-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: xor_add_vgpr_const: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xad_u32 v0, v0, 3, v1 +; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, 3 %result = add i32 %x, %b %bc = bitcast i32 %result to float