Index: clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c +++ clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c @@ -315,7 +315,7 @@ } // CHECK-LABEL: test_vnegh_f16 -// CHECK: [[NEG:%.*]] = fsub half 0xH8000, %a +// CHECK: [[NEG:%.*]] = fneg half %a // CHECK: ret half [[NEG]] float16_t test_vnegh_f16(float16_t a) { return vnegh_f16(a); Index: clang/test/CodeGen/avx512f-builtins.c =================================================================== --- clang/test/CodeGen/avx512f-builtins.c +++ clang/test/CodeGen/avx512f-builtins.c @@ -888,7 +888,7 @@ __m512d test_mm512_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> return _mm512_fmaddsub_pd(__A, __B, __C); @@ -896,7 +896,7 @@ __m512d test_mm512_mask_fmaddsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -906,7 +906,7 @@ __m512d test_mm512_mask3_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -916,7 +916,7 @@ __m512d test_mm512_maskz_fmaddsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -1002,7 +1002,7 @@ __m512 test_mm512_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> return _mm512_fmaddsub_ps(__A, __B, __C); @@ -1010,7 +1010,7 @@ __m512 test_mm512_mask_fmaddsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1020,7 +1020,7 @@ __m512 test_mm512_mask3_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1030,7 +1030,7 @@ __m512 test_mm512_maskz_fmaddsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1067,7 +1067,7 @@ } __m512d test_mm512_mask3_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1075,7 +1075,7 @@ } __m512d test_mm512_mask3_fmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1083,7 +1083,7 @@ } __m512 test_mm512_mask3_fmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1091,7 +1091,7 @@ } __m512 test_mm512_mask3_fmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1099,7 +1099,7 @@ } __m512d test_mm512_mask3_fmsubadd_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_round_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1107,7 +1107,7 @@ } __m512d test_mm512_mask3_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: shufflevector <8 x double> [[ADD]], <8 x double> [[SUB]], <8 x i32> @@ -1117,7 +1117,7 @@ } __m512 test_mm512_mask3_fmsubadd_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1125,7 +1125,7 @@ } __m512 test_mm512_mask3_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: shufflevector <16 x float> [[ADD]], <16 x float> [[SUB]], <16 x i32> @@ -1177,7 +1177,7 @@ __m512d test_mm512_mask3_fnmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_round_pd // CHECK: fsub <8 x double> - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1195,7 +1195,7 @@ __m512d test_mm512_mask3_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_pd // CHECK: fsub <8 x double> , %{{.*}} - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1213,7 +1213,7 @@ __m512 test_mm512_mask3_fnmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_round_ps // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1231,7 +1231,7 @@ __m512 test_mm512_mask3_fnmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_ps // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -7582,7 +7582,7 @@ __m128 test_mm_mask3_fmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7597,7 +7597,7 @@ __m128 test_mm_mask3_fmsub_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7780,7 +7780,7 @@ __m128 test_mm_mask3_fnmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_ss // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG2:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7796,7 +7796,7 @@ __m128 test_mm_mask3_fnmsub_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_round_ss // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG2:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7966,7 +7966,7 @@ __m128d test_mm_mask3_fmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7981,7 +7981,7 @@ __m128d test_mm_mask3_fmsub_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -8164,7 +8164,7 @@ __m128d test_mm_mask3_fnmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_sd // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG2:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8180,7 +8180,7 @@ __m128d test_mm_mask3_fnmsub_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_round_sd // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG2:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 Index: clang/test/CodeGen/avx512vl-builtins.c =================================================================== --- clang/test/CodeGen/avx512vl-builtins.c +++ clang/test/CodeGen/avx512vl-builtins.c @@ -3142,7 +3142,7 @@ __m128d test_mm_mask_fmaddsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3166,7 +3166,7 @@ __m128d test_mm_mask3_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3178,7 +3178,7 @@ __m128d test_mm_maskz_fmaddsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3202,7 +3202,7 @@ __m256d test_mm256_mask_fmaddsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3226,7 +3226,7 @@ __m256d test_mm256_mask3_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3238,7 +3238,7 @@ __m256d test_mm256_maskz_fmaddsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3262,7 +3262,7 @@ __m128 test_mm_mask_fmaddsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3286,7 +3286,7 @@ __m128 test_mm_mask3_fmaddsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3298,7 +3298,7 @@ __m128 test_mm_maskz_fmaddsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3322,7 +3322,7 @@ __m256 test_mm256_mask_fmaddsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3344,7 +3344,7 @@ __m256 test_mm256_mask3_fmaddsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3355,7 +3355,7 @@ __m256 test_mm256_maskz_fmaddsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> Index: clang/test/CodeGen/complex-math.c =================================================================== --- clang/test/CodeGen/complex-math.c +++ clang/test/CodeGen/complex-math.c @@ -54,7 +54,7 @@ float _Complex sub_float_rc(float a, float _Complex b) { // X86-LABEL: @sub_float_rc( // X86: fsub - // X86: fsub float -0.{{0+}}e+00, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; @@ -232,7 +232,7 @@ double _Complex sub_double_rc(double a, double _Complex b) { // X86-LABEL: @sub_double_rc( // X86: fsub - // X86: fsub double -0.{{0+}}e+00, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; @@ -410,7 +410,7 @@ long double _Complex sub_long_double_rc(long double a, long double _Complex b) { // X86-LABEL: @sub_long_double_rc( // X86: fsub - // X86: fsub x86_fp80 0xK8{{0+}}, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; Index: clang/test/CodeGen/fma-builtins.c =================================================================== --- clang/test/CodeGen/fma-builtins.c +++ clang/test/CodeGen/fma-builtins.c @@ -150,7 +150,7 @@ __m128 test_mm_fmaddsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> return _mm_fmaddsub_ps(a, b, c); @@ -159,7 +159,7 @@ __m128d test_mm_fmaddsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> return _mm_fmaddsub_pd(a, b, c); @@ -242,7 +242,7 @@ __m256 test_mm256_fmaddsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> return _mm256_fmaddsub_ps(a, b, c); @@ -251,7 +251,7 @@ __m256d test_mm256_fmaddsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> return _mm256_fmaddsub_pd(a, b, c); Index: clang/test/CodeGen/fma4-builtins.c =================================================================== --- clang/test/CodeGen/fma4-builtins.c +++ clang/test/CodeGen/fma4-builtins.c @@ -150,7 +150,7 @@ __m128 test_mm_maddsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_maddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> return _mm_maddsub_ps(a, b, c); @@ -159,7 +159,7 @@ __m128d test_mm_maddsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_maddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> return _mm_maddsub_pd(a, b, c); @@ -242,7 +242,7 @@ __m256 test_mm256_maddsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_maddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> return _mm256_maddsub_ps(a, b, c); @@ -251,7 +251,7 @@ __m256d test_mm256_maddsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_maddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> return _mm256_maddsub_pd(a, b, c); @@ -268,7 +268,7 @@ __m256d test_mm256_msubadd_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_msubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fsub <4 x double> , {{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> Index: llvm/include/llvm/IR/IRBuilder.h =================================================================== --- llvm/include/llvm/IR/IRBuilder.h +++ llvm/include/llvm/IR/IRBuilder.h @@ -1362,7 +1362,7 @@ MDNode *FPMathTag = nullptr) { if (auto *VC = dyn_cast(V)) return Insert(Folder.CreateFNeg(VC), Name); - return Insert(setFPAttrs(BinaryOperator::CreateFNeg(V), FPMathTag, FMF), + return Insert(setFPAttrs(UnaryOperator::CreateFNeg(V), FPMathTag, FMF), Name); } Index: llvm/include/llvm/IR/InstrTypes.h =================================================================== --- llvm/include/llvm/IR/InstrTypes.h +++ llvm/include/llvm/IR/InstrTypes.h @@ -77,7 +77,8 @@ // Methods for support type inquiry through isa, cast, and dyn_cast: static bool classof(const Instruction *I) { - return I->getOpcode() == Instruction::Alloca || + return I->isUnaryOp() || + I->getOpcode() == Instruction::Alloca || I->getOpcode() == Instruction::Load || I->getOpcode() == Instruction::VAArg || I->getOpcode() == Instruction::ExtractValue || @@ -156,6 +157,14 @@ UnaryOps getOpcode() const { return static_cast(Instruction::getOpcode()); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static bool classof(const Instruction *I) { + return I->isUnaryOp(); + } + static bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } }; //===----------------------------------------------------------------------===// Index: llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -227,7 +227,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -254,7 +254,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -286,7 +286,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -317,7 +317,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -347,7 +347,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -374,7 +374,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -406,7 +406,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -437,7 +437,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1265,7 +1265,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1285,7 +1285,7 @@ ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -1305,7 +1305,7 @@ ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -1325,7 +1325,7 @@ ; CHECK-NEXT: [[TMP67:%.*]] = fdiv fast float 1.000000e+00, [[TMP66]] ; CHECK-NEXT: [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]] ; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]]) -; CHECK-NEXT: [[TMP70:%.*]] = fsub fast float -0.000000e+00, [[TMP69]] +; CHECK-NEXT: [[TMP70:%.*]] = fneg fast float [[TMP69]] ; CHECK-NEXT: [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]]) ; CHECK-NEXT: [[TMP72:%.*]] = fptoui float [[TMP69]] to i32 ; CHECK-NEXT: [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]]) @@ -1355,7 +1355,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1377,7 +1377,7 @@ ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -1399,7 +1399,7 @@ ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -1421,7 +1421,7 @@ ; CHECK-NEXT: [[TMP73:%.*]] = fdiv fast float 1.000000e+00, [[TMP72]] ; CHECK-NEXT: [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]] ; CHECK-NEXT: [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]]) -; CHECK-NEXT: [[TMP76:%.*]] = fsub fast float -0.000000e+00, [[TMP75]] +; CHECK-NEXT: [[TMP76:%.*]] = fneg fast float [[TMP75]] ; CHECK-NEXT: [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]]) ; CHECK-NEXT: [[TMP78:%.*]] = fptoui float [[TMP75]] to i32 ; CHECK-NEXT: [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]]) @@ -1456,7 +1456,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1480,7 +1480,7 @@ ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -1504,7 +1504,7 @@ ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -1528,7 +1528,7 @@ ; CHECK-NEXT: [[TMP82:%.*]] = fdiv fast float 1.000000e+00, [[TMP81]] ; CHECK-NEXT: [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]] ; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]]) -; CHECK-NEXT: [[TMP85:%.*]] = fsub fast float -0.000000e+00, [[TMP84]] +; CHECK-NEXT: [[TMP85:%.*]] = fneg fast float [[TMP84]] ; CHECK-NEXT: [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]]) ; CHECK-NEXT: [[TMP87:%.*]] = fptosi float [[TMP84]] to i32 ; CHECK-NEXT: [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]]) @@ -1562,7 +1562,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1588,7 +1588,7 @@ ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -1614,7 +1614,7 @@ ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) @@ -1640,7 +1640,7 @@ ; CHECK-NEXT: [[TMP88:%.*]] = fdiv fast float 1.000000e+00, [[TMP87]] ; CHECK-NEXT: [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]] ; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]]) -; CHECK-NEXT: [[TMP91:%.*]] = fsub fast float -0.000000e+00, [[TMP90]] +; CHECK-NEXT: [[TMP91:%.*]] = fneg fast float [[TMP90]] ; CHECK-NEXT: [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]]) ; CHECK-NEXT: [[TMP93:%.*]] = fptosi float [[TMP90]] to i32 ; CHECK-NEXT: [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]]) @@ -1671,7 +1671,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -1698,7 +1698,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -1730,7 +1730,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1761,7 +1761,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1793,7 +1793,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1813,7 +1813,7 @@ ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -1833,7 +1833,7 @@ ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -1863,7 +1863,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1885,7 +1885,7 @@ ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -1907,7 +1907,7 @@ ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -1942,7 +1942,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1966,7 +1966,7 @@ ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -1990,7 +1990,7 @@ ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -2024,7 +2024,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2050,7 +2050,7 @@ ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -2076,7 +2076,7 @@ ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) @@ -2109,7 +2109,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -2129,7 +2129,7 @@ ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -2149,7 +2149,7 @@ ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -2179,7 +2179,7 @@ ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -2201,7 +2201,7 @@ ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -2223,7 +2223,7 @@ ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -2258,7 +2258,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2282,7 +2282,7 @@ ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -2306,7 +2306,7 @@ ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -2340,7 +2340,7 @@ ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2366,7 +2366,7 @@ ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -2392,7 +2392,7 @@ ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) Index: llvm/test/CodeGen/AMDGPU/divrem24-assume.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/divrem24-assume.ll +++ llvm/test/CodeGen/AMDGPU/divrem24-assume.ll @@ -12,7 +12,7 @@ ; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]]) -; CHECK-NEXT: [[TMP5:%.*]] = fsub fast float -0.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP5]], float [[TMP1]], float [[TMP0]]) ; CHECK-NEXT: [[TMP7:%.*]] = fptoui float [[TMP4]] to i32 ; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]]) Index: llvm/test/Transforms/InstCombine/cos-1.ll =================================================================== --- llvm/test/Transforms/InstCombine/cos-1.ll +++ llvm/test/Transforms/InstCombine/cos-1.ll @@ -54,7 +54,7 @@ define double @sin_negated_arg(double %x) { ; ANY-LABEL: @sin_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @sin(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fsub double -0.0, %x @@ -65,7 +65,7 @@ define float @sinf_negated_arg(float %x) { ; ANY-LABEL: @sinf_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fsub float -0.0, %x @@ -76,7 +76,7 @@ define float @sinf_negated_arg_FMF(float %x) { ; ANY-LABEL: @sinf_negated_arg_FMF( ; ANY-NEXT: [[TMP1:%.*]] = call nnan afn float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub nnan afn float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg nnan afn float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fsub ninf float -0.0, %x @@ -118,7 +118,7 @@ define double @tan_negated_arg(double %x) { ; ANY-LABEL: @tan_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @tan(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fsub double -0.0, %x @@ -131,7 +131,7 @@ define fp128 @tanl_negated_arg(fp128 %x) { ; ANY-LABEL: @tanl_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call fp128 @tanl(fp128 [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub fp128 0xL00000000000000008000000000000000, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg fp128 [[TMP1]] ; ANY-NEXT: ret fp128 [[TMP2]] ; %neg = fsub fp128 0xL00000000000000008000000000000000, %x Index: llvm/test/Transforms/InstCombine/fast-math.ll =================================================================== --- llvm/test/Transforms/InstCombine/fast-math.ll +++ llvm/test/Transforms/InstCombine/fast-math.ll @@ -504,7 +504,7 @@ define float @fold16(float %x, float %y) { ; CHECK-LABEL: @fold16( ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = fsub float -0.000000e+00, [[Y]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg float [[Y]] ; CHECK-NEXT: [[R_P:%.*]] = select i1 [[CMP]], float [[Y]], float [[TMP1]] ; CHECK-NEXT: [[R:%.*]] = fadd float [[R_P]], [[X]] ; CHECK-NEXT: ret float [[R]] Index: llvm/test/Transforms/InstCombine/select-crash.ll =================================================================== --- llvm/test/Transforms/InstCombine/select-crash.ll +++ llvm/test/Transforms/InstCombine/select-crash.ll @@ -4,7 +4,7 @@ define fastcc double @gimp_operation_color_balance_map(float %value, double %highlights) nounwind readnone inlinehint { entry: ; CHECK: gimp_operation_color_balance_map -; CHECK: fsub double -0.000000 +; CHECK: fneg double %conv = fpext float %value to double %div = fdiv double %conv, 1.600000e+01 %add = fadd double %div, 1.000000e+00 @@ -22,7 +22,7 @@ ; PR10180: same crash, but with vectors define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) { ; CHECK-LABEL: @foo( -; CHECK: fsub <4 x float> +; CHECK: fneg <4 x float> ; CHECK: select ; CHECK: fadd <4 x float> %a = fadd <4 x float> %x, %y Index: llvm/unittests/IR/InstructionsTest.cpp =================================================================== --- llvm/unittests/IR/InstructionsTest.cpp +++ llvm/unittests/IR/InstructionsTest.cpp @@ -1002,5 +1002,20 @@ I->deleteValue(); } +TEST(InstructionsTest, UnaryOperator) { + LLVMContext Context; + IRBuilder<> Builder(Context); + Instruction *I = Builder.CreatePHI(Builder.getDoubleTy(), 0); + Value *F = Builder.CreateFNeg(I); + + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_FALSE(isa(F)); + + F->deleteValue(); +} + } // end anonymous namespace } // end namespace llvm