Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1026,4 +1026,12 @@ // SVE2 integer multiply-add (indexed) defm MLA_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b0, "mla">; defm MLS_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b1, "mls">; + + // SVE2 saturating multiply-add high (indexed) + defm SQRDMLAH_ZZZI : sve2_int_mla_by_indexed_elem<0b10, 0b0, "sqrdmlah">; + defm SQRDMLSH_ZZZI : sve2_int_mla_by_indexed_elem<0b10, 0b1, "sqrdmlsh">; + + // SVE2 saturating multiply-add high (vectors, unpredicated) + defm SQRDMLAH_ZZZ : sve2_int_mla<0b0, "sqrdmlah">; + defm SQRDMLSH_ZZZ : sve2_int_mla<0b1, "sqrdmlsh">; } Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -1691,6 +1691,38 @@ } //===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve2_int_mla sz, bits<5> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_mla { + def _B : sve2_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>; + def _H : sve2_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>; + def _S : sve2_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>; + def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>; +} + +//===----------------------------------------------------------------------===// // SVE2 Integer Multiply-Add - Indexed Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s @@ -0,0 +1,70 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmlah z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmlah z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqrdmlah z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqrdmlah z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmlah.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlah.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqrdmlah z0.b, z1.b, z31.b +// CHECK-INST: sqrdmlah z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x70,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 1f 44 + +sqrdmlah z0.h, z1.h, z31.h +// CHECK-INST: sqrdmlah z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x70,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 5f 44 + +sqrdmlah z0.s, z1.s, z31.s +// CHECK-INST: sqrdmlah z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x70,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 9f 44 + +sqrdmlah z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x70,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 df 44 + +sqrdmlah z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmlah z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x10,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 7f 44 + +sqrdmlah z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmlah z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x10,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 bf 44 + +sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x10,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlah z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x70,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 df 44 + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x10,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 ff 44 Index: test/MC/AArch64/SVE2/sqrdmlsh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlsh-diagnostics.s @@ -0,0 +1,70 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmlsh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmlsh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqrdmlsh z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqrdmlsh z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmlsh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlsh.s @@ -0,0 +1,78 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrdmlsh z0.b, z1.b, z31.b +// CHECK-INST: sqrdmlsh z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x74,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 1f 44 + +sqrdmlsh z0.h, z1.h, z31.h +// CHECK-INST: sqrdmlsh z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x74,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 5f 44 + +sqrdmlsh z0.s, z1.s, z31.s +// CHECK-INST: sqrdmlsh z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x74,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 9f 44 + +sqrdmlsh z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x74,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 df 44 + +sqrdmlsh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmlsh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x14,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 7f 44 + +sqrdmlsh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmlsh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x14,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 bf 44 + +sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x14,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlsh z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x74,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 df 44 + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x14,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 ff 44