Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1021,3 +1021,9 @@ def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; } + +let Predicates = [HasSVE2] in { + // SVE2 integer multiply-add (indexed) + defm MLA_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b0, "mla">; + defm MLS_ZZZI : sve2_int_mla_by_indexed_elem<0b01, 0b1, "mls">; +} Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -1691,6 +1691,51 @@ } //===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +class sve2_int_mla_by_indexed_elem sz, bits<6> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + ZPRRegOp zprty3, Operand itype> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), + asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_mla_by_indexed_elem opc, bit S, string asm> { + def _H : sve2_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{22} = iop{2}; + let Inst{20-19} = iop{1-0}; + let Inst{18-16} = Zm; + } + def _S : sve2_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve2_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { + bits<4> Zm; + bit iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// // SVE Integer Dot Product Group //===----------------------------------------------------------------------===// Index: test/MC/AArch64/SVE2/mla-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mla-diagnostics.s @@ -0,0 +1,64 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mla z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: mla z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: mla z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: mla z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mla z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mla z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mla z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mla z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mla z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mla z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mla z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mla z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mla z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mla.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mla.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mla z0.h, z1.h, z7.h[7] +// CHECK-INST: mla z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x08,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 7f 44 + +mla z0.s, z1.s, z7.s[3] +// CHECK-INST: mla z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x08,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 bf 44 + +mla z0.d, z1.d, z7.d[1] +// CHECK-INST: mla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 f7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +mla z0.d, z1.d, z7.d[1] +// CHECK-INST: mla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 f7 44 Index: test/MC/AArch64/SVE2/mls-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mls-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mls z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: mls z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: mls z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: mls z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mls z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mls z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mls z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mls z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mls z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mls z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mls z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mls z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mls z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mls.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mls.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mls z0.h, z1.h, z7.h[7] +// CHECK-INST: mls z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x0c,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c 7f 44 + +mls z0.s, z1.s, z7.s[3] +// CHECK-INST: mls z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x0c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c bf 44 + +mls z0.d, z1.d, z7.d[1] +// CHECK-INST: mls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c f7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +mls z0.d, z1.d, z7.d[1] +// CHECK-INST: mls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c f7 44