Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp @@ -43890,6 +43890,18 @@ RC.hasSuperClassEq(&X86::VR512RegClass); } +/// Check if \p RC is a mask register class. +/// I.e., VK* or one of their variant. +static bool isVKClass(const TargetRegisterClass &RC) { + return RC.hasSuperClassEq(&X86::VK1RegClass) || + RC.hasSuperClassEq(&X86::VK2RegClass) || + RC.hasSuperClassEq(&X86::VK4RegClass) || + RC.hasSuperClassEq(&X86::VK8RegClass) || + RC.hasSuperClassEq(&X86::VK16RegClass) || + RC.hasSuperClassEq(&X86::VK32RegClass) || + RC.hasSuperClassEq(&X86::VK64RegClass); +} + std::pair X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, @@ -44204,6 +44216,22 @@ Res.first = 0; Res.second = nullptr; } + } else if (isVKClass(*Class)) { + if (VT == MVT::i1) + Res.second = &X86::VK1RegClass; + else if (VT == MVT::i8) + Res.second = &X86::VK8RegClass; + else if (VT == MVT::i16) + Res.second = &X86::VK16RegClass; + else if (VT == MVT::i32) + Res.second = &X86::VK32RegClass; + else if (VT == MVT::i64) + Res.second = &X86::VK64RegClass; + else { + // Type mismatch and not a clobber: Return an error; + Res.first = 0; + Res.second = nullptr; + } } return Res; Index: llvm/trunk/test/CodeGen/X86/pr41678.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/pr41678.ll +++ llvm/trunk/test/CodeGen/X86/pr41678.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -O0 -mtriple=i386-pc-linux-gnu -mattr=avx512f | FileCheck %s + +define void @a() { +; CHECK-LABEL: a: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subl $2, %esp +; CHECK-NEXT: .cfi_def_cfa_offset 6 +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: kmovw %k6, %eax +; CHECK-NEXT: movw %ax, %cx +; CHECK-NEXT: movw %cx, (%esp) +; CHECK-NEXT: addl $2, %esp +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: retl +entry: + %b = alloca i16, align 2 + %0 = call i16 asm "", "={k6},~{dirflag},~{fpsr},~{flags}"() #1 + store i16 %0, i16* %b, align 2 + ret void +}