Index: lib/Transforms/Utils/SimplifyCFG.cpp
===================================================================
--- lib/Transforms/Utils/SimplifyCFG.cpp
+++ lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4205,10 +4205,13 @@
           Changed = true;
         }
       } else {
+        Value* Cond = BI->getCondition();
         if (BI->getSuccessor(0) == BB) {
+          Builder.CreateAssumption(Builder.CreateNot(Cond));
           Builder.CreateBr(BI->getSuccessor(1));
           EraseTerminatorAndDCECond(BI);
         } else if (BI->getSuccessor(1) == BB) {
+          Builder.CreateAssumption(Cond);
           Builder.CreateBr(BI->getSuccessor(0));
           EraseTerminatorAndDCECond(BI);
           Changed = true;
Index: test/Analysis/ValueTracking/select-pattern.ll
===================================================================
--- test/Analysis/ValueTracking/select-pattern.ll
+++ test/Analysis/ValueTracking/select-pattern.ll
@@ -8,6 +8,8 @@
 define void @PR36045(i1 %t, i32* %b) {
 ; CHECK-LABEL: @PR36045(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[T:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
Index: test/CodeGen/ARM/crash-greedy.ll
===================================================================
--- test/CodeGen/ARM/crash-greedy.ll
+++ test/CodeGen/ARM/crash-greedy.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all -verify-machineinstrs | FileCheck %s
 ;
 ; ARM tests that crash or fail with the greedy register allocator.
@@ -30,7 +31,6 @@
   %call85 = tail call double @exp(double %mul84) nounwind
   %mul86 = fmul double %conv78, %call85
   %add88 = fadd double 0.000000e+00, %mul86
-; CHECK: bl _exp
   %call100 = tail call double @exp(double %mul84) nounwind
   %mul101 = fmul double undef, %call100
   %add103 = fadd double %add46, %mul101
@@ -49,7 +49,6 @@
   %sub143 = fsub double %mul139, %div142
 ; %lambda is passed on the stack, and the stack slot load is rematerialized.
 ; The rematted load of a float constrains the D register used for the mul.
-; CHECK: vldr
   %mul146 = fmul float %lambda, %lambda
   %conv147 = fpext float %mul146 to double
   %div148 = fdiv double 1.000000e+00, %conv147
Index: test/Transforms/CallSiteSplitting/split-loop.ll
===================================================================
--- test/Transforms/CallSiteSplitting/split-loop.ll
+++ test/Transforms/CallSiteSplitting/split-loop.ll
@@ -5,6 +5,9 @@
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 undef, i16 1, i16 0
+; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[SPEC_SELECT]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
 ; CHECK:       for.cond12:
 ; CHECK-NEXT:    call void @callee(i16 [[SPEC_SELECT]])
@@ -27,6 +30,9 @@
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[S:%.*]] = select i1 undef, i16 1, i16 0
+; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[S]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
 ; CHECK:       for.cond12:
 ; CHECK-NEXT:    call void @callee(i16 [[S]])
@@ -53,6 +59,9 @@
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[S:%.*]] = select i1 undef, i16 1, i16 0
+; CHECK-NEXT:    [[TOBOOL18:%.*]] = icmp ne i16 [[S]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[TOBOOL18]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOR_COND12:%.*]]
 ; CHECK:       for.cond12:
 ; CHECK-NEXT:    call void @callee(i16 [[S]])
Index: test/Transforms/LoopVectorize/if-pred-stores.ll
===================================================================
--- test/Transforms/LoopVectorize/if-pred-stores.ll
+++ test/Transforms/LoopVectorize/if-pred-stores.ll
@@ -197,21 +197,7 @@
 define void @bug18724() {
 ; UNROLL-LABEL: @bug18724(
 ; UNROLL-NEXT:  entry:
-; UNROLL-NEXT:    br label [[FOR_BODY14:%.*]]
-; UNROLL:       for.body14:
-; UNROLL-NEXT:    [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
-; UNROLL-NEXT:    [[INEWCHUNKS_120:%.*]] = phi i32 [ [[INEWCHUNKS_2:%.*]], [[FOR_INC23]] ], [ undef, [[ENTRY]] ]
-; UNROLL-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDVARS_IV3]]
-; UNROLL-NEXT:    [[TMP:%.*]] = load i32, i32* [[ARRAYIDX16]], align 4
-; UNROLL-NEXT:    br i1 undef, label [[IF_THEN18:%.*]], label [[FOR_INC23]]
-; UNROLL:       if.then18:
-; UNROLL-NEXT:    store i32 2, i32* [[ARRAYIDX16]], align 4
-; UNROLL-NEXT:    [[INC21:%.*]] = add nsw i32 [[INEWCHUNKS_120]], 1
-; UNROLL-NEXT:    br label [[FOR_INC23]]
-; UNROLL:       for.inc23:
-; UNROLL-NEXT:    [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
-; UNROLL-NEXT:    [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
-; UNROLL-NEXT:    br label [[FOR_BODY14]]
+; UNROLL-NEXT:    unreachable
 ;
 ; UNROLL-NOSIMPLIFY-LABEL: @bug18724(
 ; UNROLL-NOSIMPLIFY-NEXT:  entry:
@@ -287,21 +273,7 @@
 ;
 ; VEC-LABEL: @bug18724(
 ; VEC-NEXT:  entry:
-; VEC-NEXT:    br label [[FOR_BODY14:%.*]]
-; VEC:       for.body14:
-; VEC-NEXT:    [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ]
-; VEC-NEXT:    [[INEWCHUNKS_120:%.*]] = phi i32 [ [[INEWCHUNKS_2:%.*]], [[FOR_INC23]] ], [ undef, [[ENTRY]] ]
-; VEC-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [768 x i32], [768 x i32]* undef, i64 0, i64 [[INDVARS_IV3]]
-; VEC-NEXT:    [[TMP:%.*]] = load i32, i32* [[ARRAYIDX16]], align 4
-; VEC-NEXT:    br i1 undef, label [[IF_THEN18:%.*]], label [[FOR_INC23]]
-; VEC:       if.then18:
-; VEC-NEXT:    store i32 2, i32* [[ARRAYIDX16]], align 4
-; VEC-NEXT:    [[INC21:%.*]] = add nsw i32 [[INEWCHUNKS_120]], 1
-; VEC-NEXT:    br label [[FOR_INC23]]
-; VEC:       for.inc23:
-; VEC-NEXT:    [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ]
-; VEC-NEXT:    [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1
-; VEC-NEXT:    br label [[FOR_BODY14]]
+; VEC-NEXT:    unreachable
 ;
 entry:
   br label %for.body9
Index: test/Transforms/SimplifyCFG/PR30210.ll
===================================================================
--- test/Transforms/SimplifyCFG/PR30210.ll
+++ test/Transforms/SimplifyCFG/PR30210.ll
@@ -10,6 +10,8 @@
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND_US:%.*]]
 ; CHECK:       for.cond.us:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[B:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    br label [[FOR_COND_US]]
 ;
 entry:
@@ -35,4 +37,4 @@
 for.end:                                          ; preds = %for.cond5
   %load = load i32, i32* %call, align 4
   br label %for.cond4
-}
\ No newline at end of file
+}
Index: test/Transforms/SimplifyCFG/UnreachableEliminate.ll
===================================================================
--- test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+++ test/Transforms/SimplifyCFG/UnreachableEliminate.ll
@@ -4,6 +4,8 @@
 define void @test1(i1 %C, i1* %BP) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -62,6 +64,8 @@
 define void @test5(i1 %cond, i8* %ptr) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    store i8 2, i8* [[PTR:%.*]], align 8
 ; CHECK-NEXT:    ret void
 ;
@@ -107,6 +111,8 @@
 define void @test6(i1 %cond, i8* %ptr) {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[COND:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    store i8 2, i8* [[PTR:%.*]], align 8
 ; CHECK-NEXT:    ret void
 ;
@@ -145,6 +151,8 @@
 define i32 @test7(i1 %X) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[X:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
@@ -162,6 +170,8 @@
 define void @test8(i1 %X, void ()* %Y) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = xor i1 [[X:%.*]], true
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP0]])
 ; CHECK-NEXT:    call void [[Y:%.*]]()
 ; CHECK-NEXT:    ret void
 ;
@@ -196,4 +206,4 @@
   ret void
 }
 
-attributes #0 = { "null-pointer-is-valid"="true" }
\ No newline at end of file
+attributes #0 = { "null-pointer-is-valid"="true" }
Index: test/Transforms/SimplifyCFG/unreachable_assume.ll
===================================================================
--- test/Transforms/SimplifyCFG/unreachable_assume.ll
+++ test/Transforms/SimplifyCFG/unreachable_assume.ll
@@ -1,14 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -simplifycfg -instcombine -S | FileCheck %s
 
-; TODO: ABS call should be optimized away
 define i32 @assume1(i32 %p) {
 ; CHECK-LABEL: @assume1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i32 [[P:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[P]]
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[TMP0]], i32 [[NEG]], i32 [[P]]
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[P:%.*]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    ret i32 [[P]]
 ;
 entry:
   %cmp = icmp sle i32 %p, 0
@@ -26,10 +24,9 @@
 define i32 @assume2(i32 %p) {
 ; CHECK-LABEL: @assume2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i32 [[P:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[P]]
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[TMP0]], i32 [[NEG]], i32 [[P]]
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[P:%.*]], 0
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    ret i32 [[P]]
 ;
 entry:
   %cmp = icmp sgt i32 %p, 0