Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -533,6 +533,13 @@
 def BC2T : MMRel, BC1F_FT<"bc2t", brtarget, IIBranch, MIPS_BRANCH_T>,
            BC2F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
+let DecoderNamespace = "COP3_" in {
+  def BC3F : MMRel, BC0F_FT<"bc3f", brtarget, IIBranch>,
+             BC3F_FM<0, 0>, ISA_MIPS1_ONLY;
+  def BC3T : MMRel, BC0F_FT<"bc3t", brtarget, IIBranch>,
+             BC3F_FM<0, 1>, ISA_MIPS1_ONLY;
+}
+
 //===----------------------------------------------------------------------===//
 // Floating Point Flag Conditions
 //===----------------------------------------------------------------------===//
Index: lib/Target/Mips/MipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MipsInstrFormats.td
+++ lib/Target/Mips/MipsInstrFormats.td
@@ -792,6 +792,20 @@
   let Inst{15-0} = offset;
 }
 
+class BC3F_FM<bit HasDelaySlot, bit tf> : StdArch {
+  bits<3>  fcc;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x13;
+  let Inst{25-21} = 0x8;
+  let Inst{20-18} = 0x0;
+  let Inst{17} = HasDelaySlot;
+  let Inst{16} = tf;
+  let Inst{15-0} = offset;
+}
+
 class CEQS_FM<bits<5> fmt> : StdArch {
   bits<5> fs;
   bits<5> ft;
Index: test/MC/Disassembler/Mips/mips1.txt
===================================================================
--- test/MC/Disassembler/Mips/mips1.txt
+++ test/MC/Disassembler/Mips/mips1.txt
@@ -6,3 +6,9 @@
 # CHECK: bc0t 1332
 0x41 0x01 0x01 0x4d
 
+# CHECK: bc3f 1332
+0x4d 0x00 0x01 0x4d
+
+# CHECK: bc3t 1332
+0x4d 0x01 0x01 0x4d
+
Index: test/MC/Mips/mips1/valid.s
===================================================================
--- test/MC/Mips/mips1/valid.s
+++ test/MC/Mips/mips1/valid.s
@@ -26,6 +26,8 @@
         bc2f      4                    # CHECK: bc2f 4        # encoding: [0x49,0x00,0x00,0x01] 
         bc2t      $fcc0, 4             # CHECK: bc2t 4        # encoding: [0x49,0x01,0x00,0x01]
         bc2t      4                    # CHECK: bc2t 4        # encoding: [0x49,0x01,0x00,0x01]
+        bc3f      4                    # CHECK: bc3f 4        # encoding: [0x4d,0x00,0x00,0x01]
+        bc3t      4                    # CHECK: bc3t 4        # encoding: [0x4d,0x01,0x00,0x01]
         bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
         bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
Index: test/MC/Mips/mips2/invalid-mips1.s
===================================================================
--- test/MC/Mips/mips2/invalid-mips1.s
+++ test/MC/Mips/mips2/invalid-mips1.s
@@ -7,4 +7,6 @@
         .set noat
         bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc3f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc3t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         
Index: test/MC/Mips/mips32/invalid-mips1.s
===================================================================
--- test/MC/Mips/mips32/invalid-mips1.s
+++ test/MC/Mips/mips32/invalid-mips1.s
@@ -7,4 +7,6 @@
         .set noat
         bc0f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bc0t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc3f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bc3t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled