Index: lib/Transforms/Utils/SimplifyCFG.cpp =================================================================== --- lib/Transforms/Utils/SimplifyCFG.cpp +++ lib/Transforms/Utils/SimplifyCFG.cpp @@ -5293,9 +5293,9 @@ for (SwitchInst::CaseIt E = SI->case_end(); CI != E; ++CI) { ConstantInt *CaseVal = CI->getCaseValue(); - if (CaseVal->getValue().slt(MinCaseVal->getValue())) + if (CaseVal->getValue().ult(MinCaseVal->getValue())) MinCaseVal = CaseVal; - if (CaseVal->getValue().sgt(MaxCaseVal->getValue())) + if (CaseVal->getValue().ugt(MaxCaseVal->getValue())) MaxCaseVal = CaseVal; // Resulting value at phi nodes for this case value. @@ -5321,8 +5321,7 @@ } uint64_t NumResults = ResultLists[PHIs[0]].size(); - APInt RangeSpread = MaxCaseVal->getValue() - MinCaseVal->getValue(); - uint64_t TableSize = RangeSpread.getLimitedValue() + 1; + uint64_t TableSize = MaxCaseVal->getValue().getLimitedValue() + 1; bool TableHasHoles = (NumResults < TableSize); // If the table has holes, we need a constant result for the default case @@ -5357,12 +5356,7 @@ // Compute the table index value. Builder.SetInsertPoint(SI); - Value *TableIndex; - if (MinCaseVal->isNullValue()) - TableIndex = SI->getCondition(); - else - TableIndex = Builder.CreateSub(SI->getCondition(), MinCaseVal, - "switch.tableidx"); + Value *TableIndex = SI->getCondition(); // Compute the maximum table size representable by the integer type we are // switching upon. @@ -5402,6 +5396,9 @@ LookupBB = BasicBlock::Create(Mod.getContext(), "switch.lookup", CommonDest->getParent(), CommonDest); + // When doing the register-sized hole-check, unconditionally use a subtraction. + TableIndex = Builder.CreateSub(TableIndex, MinCaseVal); + // Make the mask's bitwidth at least 8-bit and a power-of-2 to avoid // unnecessary illegal types. uint64_t TableSizePowOf2 = NextPowerOf2(std::max(7ULL, TableSize - 1ULL)); @@ -5445,8 +5442,9 @@ // If using a bitmask, use any value to fill the lookup table holes. Constant *DV = NeedMask ? ResultLists[PHI][0].second : DefaultResults[PHI]; StringRef FuncName = Fn->getName(); - SwitchLookupTable Table(Mod, TableSize, MinCaseVal, ResultList, DV, DL, - FuncName); + SwitchLookupTable Table(Mod, TableSize, NeedMask ? MinCaseVal : + ConstantInt::get(MinCaseVal->getContext(), APInt(CaseSize, 0)), + ResultList, DV, DL, FuncName); Value *Result = Table.BuildLookup(TableIndex, Builder); @@ -5491,17 +5489,6 @@ return true; } -static bool isSwitchDense(ArrayRef Values) { - // See also SelectionDAGBuilder::isDense(), which this function was based on. - uint64_t Diff = (uint64_t)Values.back() - (uint64_t)Values.front(); - uint64_t Range = Diff + 1; - uint64_t NumCases = Values.size(); - // 40% is the default density for building a jump table in optsize/minsize mode. - uint64_t MinDensity = 40; - - return NumCases * 100 >= Range * MinDensity; -} - /// Try to transform a switch that has "holes" in it to a contiguous sequence /// of cases. /// @@ -5513,32 +5500,47 @@ static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder, const DataLayout &DL, const TargetTransformInfo &TTI) { + // The number of cases that need to be removed by a subtraction operation + // to make it worth using. + const unsigned SubThreshold = (SI->getFunction()->hasOptSize() ? 2 : 8); auto *CondTy = cast(SI->getCondition()->getType()); - if (CondTy->getIntegerBitWidth() > 64 || - !DL.fitsInLegalInteger(CondTy->getIntegerBitWidth())) + unsigned BitWidth = CondTy->getIntegerBitWidth(); + if (BitWidth > 64 || + !DL.fitsInLegalInteger(BitWidth)) return false; // Only bother with this optimization if there are more than 3 switch cases; // SDAG will only bother creating jump tables for 4 or more cases. + // This is also useful when using the LowerSwitch transform, but not with + // so few cases. if (SI->getNumCases() < 4) return false; - // This transform is agnostic to the signedness of the input or case values. We - // can treat the case values as signed or unsigned. We can optimize more common - // cases such as a sequence crossing zero {-4,0,4,8} if we interpret case values - // as signed. - SmallVector Values; + // We organize the range to start from 0, if it is not already close. + SmallVector Values; for (auto &C : SI->cases()) - Values.push_back(C.getCaseValue()->getValue().getSExtValue()); + Values.push_back(C.getCaseValue()->getValue().getLimitedValue()); llvm::sort(Values); - // If the switch is already dense, there's nothing useful to do here. - if (isSwitchDense(Values)) - return false; - - // First, transform the values such that they start at zero and ascend. - int64_t Base = Values[0]; - for (auto &V : Values) - V -= (uint64_t)(Base); + bool MadeChanges = false; + // We must first look find the best start point, for example if we have a series + // that crosses zero: -2, -1, 0, 1, 2. + uint64_t BestDistance = APInt::getMaxValue(CondTy->getIntegerBitWidth()).getLimitedValue() - + Values.back() + Values.front() + 1; + unsigned BestIndex = 0; + for (unsigned I = 1;I != Values.size();I++) { + if (Values[I] - Values[I-1] > BestDistance) { + BestIndex = I; + BestDistance = Values[I] - Values[I-1]; + } + } + uint64_t Base = 0; + // Now transform the values such that they start at zero and ascend. + if (Values[BestIndex] >= SubThreshold) { + Base = Values[BestIndex]; + MadeChanges = true; + for (auto &V : Values) + V = (APInt(BitWidth, V) - Base).getLimitedValue(); + } // Now we have signed numbers that have been shifted so that, given enough // precision, there are no negative values. Since the rest of the transform @@ -5558,12 +5560,14 @@ unsigned Shift = 64; for (auto &V : Values) Shift = std::min(Shift, countTrailingZeros((uint64_t)V)); - if (Shift > 0) + if (Shift > 0) { + MadeChanges = true; for (auto &V : Values) - V = (int64_t)((uint64_t)V >> Shift); + V >>= Shift; + } - if (!isSwitchDense(Values)) - // Transform didn't create a dense switch. + if (!MadeChanges) + // We didn't do anything. return false; // The obvious transform is to shift the switch condition right and emit a @@ -5634,6 +5638,9 @@ if (Options.ForwardSwitchCondToPhi && ForwardSwitchConditionToPHI(SI)) return requestResimplify(); + if (ReduceSwitchRange(SI, Builder, DL, TTI)) + return requestResimplify(); + // The conversion from switch to lookup tables results in difficult-to-analyze // code and makes pruning branches much harder. This is a problem if the // switch expression itself can still be restricted as a result of inlining or @@ -5643,9 +5650,6 @@ SwitchToLookupTable(SI, Builder, DL, TTI)) return requestResimplify(); - if (ReduceSwitchRange(SI, Builder, DL, TTI)) - return requestResimplify(); - return false; } Index: test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll =================================================================== --- test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll +++ test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll @@ -2,6 +2,7 @@ ; RUN: opt < %s -simplifycfg -switch-to-lookup -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: opt < %s -passes='simplify-cfg' -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; In the presence of "-no-jump-tables"="true", simplifycfg should not convert switches to lookup tables. ; CHECK: @switch.table.bar = private unnamed_addr constant [4 x i32] [i32 55, i32 123, i32 0, i32 -1] @@ -11,11 +12,12 @@ define i32 @foo(i32 %c) "no-jump-tables"="true" { ; CHECK-LABEL: @foo( ; CHECK-NEXT: entry: -; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [ -; CHECK-NEXT: i32 42, label [[RETURN:%.*]] -; CHECK-NEXT: i32 43, label [[SW_BB1:%.*]] -; CHECK-NEXT: i32 44, label [[SW_BB2:%.*]] -; CHECK-NEXT: i32 45, label [[SW_BB3:%.*]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 42 +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[SW_DEFAULT:%.*]] [ +; CHECK-NEXT: i32 0, label [[RETURN:%.*]] +; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]] +; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]] +; CHECK-NEXT: i32 3, label [[SW_BB3:%.*]] ; CHECK-NEXT: ] ; CHECK: sw.bb1: ; CHECK-NEXT: br label [[RETURN]] @@ -50,11 +52,11 @@ define i32 @bar(i32 %c) { ; CHECK-LABEL: @bar( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 42 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 4 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.bar, i32 0, i32 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.bar, i32 0, i32 [[SWITCH_RANGEREDUCE]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; CHECK: return: Index: test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll =================================================================== --- test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll +++ test/Transforms/SimplifyCFG/X86/switch-covered-bug.ll @@ -9,11 +9,16 @@ define i64 @test(i3 %arg) { ; CHECK-LABEL: @test( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[ARG:%.*]], -4 -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i3 [[ARG:%.*]], -1 +; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[DEFAULT:%.*]] +; CHECK: switch.lookup: +; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[ARG]] to i4 +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i64], [7 x i64]* @switch.table.test, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]] -; CHECK-NEXT: [[V3:%.*]] = add i64 [[SWITCH_LOAD]], 0 +; CHECK-NEXT: br label [[DEFAULT]] +; CHECK: Default: +; CHECK-NEXT: [[V1:%.*]] = phi i64 [ 8, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ] +; CHECK-NEXT: [[V3:%.*]] = add i64 [[V1]], 0 ; CHECK-NEXT: ret i64 [[V3]] ; entry: Index: test/Transforms/SimplifyCFG/X86/switch-table-bug.ll =================================================================== --- test/Transforms/SimplifyCFG/X86/switch-table-bug.ll +++ test/Transforms/SimplifyCFG/X86/switch-table-bug.ll @@ -9,11 +9,8 @@ define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) { ; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i2 [[TMP0:%.*]], -2 -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i2 [[SWITCH_TABLEIDX]] to i3 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], [4 x i64]* @switch.table._TFO6reduce1E5toRawfS0_FT_Si, i32 0, i3 [[SWITCH_TABLEIDX_ZEXT]] -; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]] -; CHECK-NEXT: ret i64 [[SWITCH_LOAD]] +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i2 [[TMP0:%.*]] to i64 +; CHECK-NEXT: ret i64 [[SWITCH_IDX_CAST]] ; entry: switch i2 %0, label %1 [ Index: test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll =================================================================== --- test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll +++ test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll @@ -36,11 +36,11 @@ define i32 @f(i32 %c) { ; CHECK-LABEL: @f( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 42 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 7 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i32 0, i32 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i32 0, i32 [[SWITCH_RANGEREDUCE]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; CHECK: return: @@ -75,11 +75,11 @@ define i8 @char(i32 %c) { ; CHECK-LABEL: @char( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 9 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 42 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 9 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i8], [9 x i8]* @switch.table.char, i32 0, i32 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i8], [9 x i8]* @switch.table.char, i32 0, i32 [[SWITCH_RANGEREDUCE]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i8, i8* [[SWITCH_GEP]] ; CHECK-NEXT: ret i8 [[SWITCH_LOAD]] ; CHECK: return: @@ -245,11 +245,11 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33 ; CHECK-NEXT: br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]] ; CHECK: switch.early.test: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C]], 34 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 59 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i8 [[C]], 34 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_RANGEREDUCE]], 59 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[LOR_END]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i59 +; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_RANGEREDUCE]] to i59 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul i59 [[SWITCH_CAST]], 1 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i59 -288230375765830623, [[SWITCH_SHIFTAMT]] ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i59 [[SWITCH_DOWNSHIFT]] to i1 @@ -300,11 +300,12 @@ define i32 @overflow(i32 %type) { ; CHECK-LABEL: @overflow( ; CHECK-NEXT: entry: -; CHECK-NEXT: switch i32 [[TYPE:%.*]], label [[IF_END:%.*]] [ -; CHECK-NEXT: i32 3, label [[SW_BB3:%.*]] -; CHECK-NEXT: i32 -2147483645, label [[SW_BB3]] -; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]] -; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[TYPE:%.*]], -2147483645 +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[IF_END:%.*]] [ +; CHECK-NEXT: i32 -2147483648, label [[SW_BB3:%.*]] +; CHECK-NEXT: i32 0, label [[SW_BB3]] +; CHECK-NEXT: i32 2147483646, label [[SW_BB1:%.*]] +; CHECK-NEXT: i32 2147483647, label [[SW_BB2:%.*]] ; CHECK-NEXT: ] ; CHECK: sw.bb1: ; CHECK-NEXT: br label [[IF_END]] @@ -379,11 +380,10 @@ ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X]], -10 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[MUL]], i32 [[X]] -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[SPEC_SELECT]], 1 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 199 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SPEC_SELECT]], 200 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [199 x i32], [199 x i32]* @switch.table.large, i32 0, i32 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [200 x i32], [200 x i32]* @switch.table.large, i32 0, i32 [[SPEC_SELECT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; CHECK: return: @@ -809,11 +809,10 @@ define i32 @cprop(i32 %x, i32 %y) { ; CHECK-LABEL: @cprop( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[X:%.*]], 1 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 8 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.cprop, i32 0, i32 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.cprop, i32 0, i32 [[X]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; CHECK: return: @@ -924,12 +923,13 @@ define i96 @illegaltype(i32 %c) { ; CHECK-LABEL: @illegaltype( ; CHECK-NEXT: entry: -; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [ -; CHECK-NEXT: i32 42, label [[RETURN:%.*]] -; CHECK-NEXT: i32 43, label [[SW_BB1:%.*]] -; CHECK-NEXT: i32 44, label [[SW_BB2:%.*]] -; CHECK-NEXT: i32 45, label [[SW_BB3:%.*]] -; CHECK-NEXT: i32 46, label [[SW_BB4:%.*]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 42 +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[SW_DEFAULT:%.*]] [ +; CHECK-NEXT: i32 0, label [[RETURN:%.*]] +; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]] +; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]] +; CHECK-NEXT: i32 3, label [[SW_BB3:%.*]] +; CHECK-NEXT: i32 4, label [[SW_BB4:%.*]] ; CHECK-NEXT: ] ; CHECK: sw.bb1: ; CHECK-NEXT: br label [[RETURN]] @@ -1009,12 +1009,13 @@ ; CHECK-NEXT: call void @exit(i32 1) ; CHECK-NEXT: unreachable ; CHECK: switch.hole_check: -; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = trunc i32 [[C]] to i8 +; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[C]], 0 +; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = trunc i32 [[TMP1]] to i8 ; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 47, [[SWITCH_MASKINDEX]] ; CHECK-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1 ; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[SW_DEFAULT]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.nodefaultwithholes, i32 0, i32 [[C]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.nodefaultwithholes, i32 0, i32 [[TMP1]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; @@ -1213,11 +1214,11 @@ define i8 @linearmap1(i32 %c) { ; CHECK-LABEL: @linearmap1( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 4 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8 +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_RANGEREDUCE]] to i8 ; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], -5 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i8 [[SWITCH_IDX_MULT]], 18 ; CHECK-NEXT: ret i8 [[SWITCH_OFFSET]] @@ -1244,11 +1245,11 @@ define i32 @linearmap2(i8 %c) { ; CHECK-LABEL: @linearmap2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C:%.*]], -13 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i8 [[C:%.*]], -13 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_RANGEREDUCE]], 4 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i32 +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i8 [[SWITCH_RANGEREDUCE]] to i32 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[SWITCH_IDX_CAST]], 18 ; CHECK-NEXT: ret i32 [[SWITCH_OFFSET]] ; CHECK: return: @@ -1274,11 +1275,11 @@ define i8 @linearmap3(i32 %c) { ; CHECK-LABEL: @linearmap3( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 4 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8 +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_RANGEREDUCE]] to i8 ; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], 100 ; CHECK-NEXT: ret i8 [[SWITCH_IDX_MULT]] ; CHECK: return: @@ -1304,11 +1305,11 @@ define i8 @linearmap4(i32 %c) { ; CHECK-LABEL: @linearmap4( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], -2 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[C:%.*]], -2 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_RANGEREDUCE]], 4 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8 +; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_RANGEREDUCE]] to i8 ; CHECK-NEXT: ret i8 [[SWITCH_IDX_CAST]] ; CHECK: return: ; CHECK-NEXT: ret i8 3 @@ -1547,18 +1548,21 @@ define i32 @covered_switch_with_bit_tests(i3) { ; CHECK-LABEL: @covered_switch_with_bit_tests( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[TMP0:%.*]], -4 -; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i8 -; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 -61, [[SWITCH_MASKINDEX]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i3 [[TMP0:%.*]], -2 +; CHECK-NEXT: br i1 [[TMP1]], label [[SWITCH_HOLE_CHECK:%.*]], label [[L6:%.*]] +; CHECK: switch.hole_check: +; CHECK-NEXT: [[TMP2:%.*]] = sub i3 [[TMP0]], 2 +; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = zext i3 [[TMP2]] to i8 +; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 15, [[SWITCH_MASKINDEX]] ; CHECK-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1 -; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[L6:%.*]] +; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[L6]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4 -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.covered_switch_with_bit_tests, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] +; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[TMP2]] to i4 +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.covered_switch_with_bit_tests, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]] ; CHECK-NEXT: br label [[L6]] ; CHECK: l6: -; CHECK-NEXT: [[R:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ] +; CHECK-NEXT: [[R:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 0, [[SWITCH_HOLE_CHECK]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ] ; CHECK-NEXT: ret i32 [[R]] ; entry: Index: test/Transforms/SimplifyCFG/rangereduce.ll =================================================================== --- test/Transforms/SimplifyCFG/rangereduce.ll +++ test/Transforms/SimplifyCFG/rangereduce.ll @@ -79,7 +79,7 @@ ret i128 99783 } -; Optimization shouldn't trigger; no holes present +; Optimization shouldn't trigger; too few cases define i32 @test3(i32 %a) { ; CHECK-LABEL: @test3( ; CHECK-NEXT: switch i32 [[A:%.*]], label [[DEF:%.*]] [ @@ -114,14 +114,14 @@ ret i32 99783 } -; Optimization shouldn't trigger; not an arithmetic progression define i32 @test4(i32 %a) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: switch i32 [[A:%.*]], label [[DEF:%.*]] [ -; CHECK-NEXT: i32 97, label [[ONE:%.*]] -; CHECK-NEXT: i32 102, label [[TWO:%.*]] -; CHECK-NEXT: i32 105, label [[THREE:%.*]] -; CHECK-NEXT: i32 109, label [[THREE]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[A:%.*]], 97 +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[DEF:%.*]] [ +; CHECK-NEXT: i32 0, label [[ONE:%.*]] +; CHECK-NEXT: i32 5, label [[TWO:%.*]] +; CHECK-NEXT: i32 8, label [[THREE:%.*]] +; CHECK-NEXT: i32 12, label [[THREE]] ; CHECK-NEXT: ] ; CHECK: def: ; CHECK-NEXT: [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ] @@ -151,14 +151,14 @@ ret i32 99783 } -; Optimization shouldn't trigger; not a power of two define i32 @test5(i32 %a) { ; CHECK-LABEL: @test5( -; CHECK-NEXT: switch i32 [[A:%.*]], label [[DEF:%.*]] [ -; CHECK-NEXT: i32 97, label [[ONE:%.*]] -; CHECK-NEXT: i32 102, label [[TWO:%.*]] -; CHECK-NEXT: i32 107, label [[THREE:%.*]] -; CHECK-NEXT: i32 112, label [[THREE]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[A:%.*]], 97 +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[DEF:%.*]] [ +; CHECK-NEXT: i32 0, label [[ONE:%.*]] +; CHECK-NEXT: i32 5, label [[TWO:%.*]] +; CHECK-NEXT: i32 10, label [[THREE:%.*]] +; CHECK-NEXT: i32 15, label [[THREE]] ; CHECK-NEXT: ] ; CHECK: def: ; CHECK-NEXT: [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ] @@ -190,8 +190,9 @@ define i32 @test6(i32 %a) optsize { ; CHECK-LABEL: @test6( -; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = call i32 @llvm.fshr.i32(i32 [[A:%.*]], i32 [[A]], i32 2) -; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[DEF:%.*]] [ +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[A:%.*]], -109 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE1:%.*]] = call i32 @llvm.fshr.i32(i32 [[SWITCH_RANGEREDUCE]], i32 [[SWITCH_RANGEREDUCE]], i32 2) +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE1]], label [[DEF:%.*]] [ ; CHECK-NEXT: i32 3, label [[ONE:%.*]] ; CHECK-NEXT: i32 2, label [[TWO:%.*]] ; CHECK-NEXT: i32 1, label [[THREE:%.*]] @@ -227,11 +228,12 @@ define i8 @test7(i8 %a) optsize { ; CHECK-LABEL: @test7( -; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = call i8 @llvm.fshr.i8(i8 [[A:%.*]], i8 [[A]], i8 2) -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[SWITCH_RANGEREDUCE]], 4 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i8 [[A:%.*]], -36 +; CHECK-NEXT: [[SWITCH_RANGEREDUCE1:%.*]] = call i8 @llvm.fshr.i8(i8 [[SWITCH_RANGEREDUCE]], i8 [[SWITCH_RANGEREDUCE]], i8 2) +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[SWITCH_RANGEREDUCE1]], 4 ; CHECK-NEXT: br i1 [[TMP1]], label [[SWITCH_LOOKUP:%.*]], label [[DEF:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_RANGEREDUCE]] to i32 +; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_RANGEREDUCE1]] to i32 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul i32 [[SWITCH_CAST]], 8 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 -943228976, [[SWITCH_SHIFTAMT]] ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8 @@ -297,13 +299,12 @@ define i32 @test9(i32 %a) { ; CHECK-LABEL: @test9( -; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i32 [[A:%.*]], 6 -; CHECK-NEXT: [[SWITCH_RANGEREDUCE1:%.*]] = call i32 @llvm.fshr.i32(i32 [[SWITCH_RANGEREDUCE]], i32 [[SWITCH_RANGEREDUCE]], i32 1) -; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE1]], label [[DEF:%.*]] [ -; CHECK-NEXT: i32 6, label [[ONE:%.*]] -; CHECK-NEXT: i32 7, label [[TWO:%.*]] -; CHECK-NEXT: i32 0, label [[THREE:%.*]] -; CHECK-NEXT: i32 2, label [[THREE]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = call i32 @llvm.fshr.i32(i32 [[A:%.*]], i32 [[A]], i32 1) +; CHECK-NEXT: switch i32 [[SWITCH_RANGEREDUCE]], label [[DEF:%.*]] [ +; CHECK-NEXT: i32 9, label [[ONE:%.*]] +; CHECK-NEXT: i32 10, label [[TWO:%.*]] +; CHECK-NEXT: i32 3, label [[THREE:%.*]] +; CHECK-NEXT: i32 5, label [[THREE]] ; CHECK-NEXT: ] ; CHECK: def: ; CHECK-NEXT: [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ] Index: test/Transforms/SimplifyCFG/switch-genfori8.ll =================================================================== --- test/Transforms/SimplifyCFG/switch-genfori8.ll +++ test/Transforms/SimplifyCFG/switch-genfori8.ll @@ -14,23 +14,24 @@ ; Function Attrs: norecurse nounwind readnone uwtable define dso_local zeroext i8 @char_to_digit(i8 zeroext) local_unnamed_addr #0 { ; CHECK-LABEL: @char_to_digit( -; CHECK-NEXT: switch i8 [[TMP0:%.*]], label [[TMP17:%.*]] [ -; CHECK-NEXT: i8 48, label [[TMP18:%.*]] -; CHECK-NEXT: i8 49, label [[TMP2:%.*]] -; CHECK-NEXT: i8 50, label [[TMP3:%.*]] -; CHECK-NEXT: i8 51, label [[TMP4:%.*]] -; CHECK-NEXT: i8 52, label [[TMP5:%.*]] -; CHECK-NEXT: i8 53, label [[TMP6:%.*]] -; CHECK-NEXT: i8 54, label [[TMP7:%.*]] -; CHECK-NEXT: i8 55, label [[TMP8:%.*]] -; CHECK-NEXT: i8 56, label [[TMP9:%.*]] -; CHECK-NEXT: i8 57, label [[TMP10:%.*]] -; CHECK-NEXT: i8 97, label [[TMP11:%.*]] -; CHECK-NEXT: i8 98, label [[TMP12:%.*]] -; CHECK-NEXT: i8 99, label [[TMP13:%.*]] -; CHECK-NEXT: i8 100, label [[TMP14:%.*]] -; CHECK-NEXT: i8 101, label [[TMP15:%.*]] -; CHECK-NEXT: i8 102, label [[TMP16:%.*]] +; CHECK-NEXT: [[SWITCH_RANGEREDUCE:%.*]] = sub i8 [[TMP0:%.*]], 48 +; CHECK-NEXT: switch i8 [[SWITCH_RANGEREDUCE]], label [[TMP17:%.*]] [ +; CHECK-NEXT: i8 0, label [[TMP18:%.*]] +; CHECK-NEXT: i8 1, label [[TMP2:%.*]] +; CHECK-NEXT: i8 2, label [[TMP3:%.*]] +; CHECK-NEXT: i8 3, label [[TMP4:%.*]] +; CHECK-NEXT: i8 4, label [[TMP5:%.*]] +; CHECK-NEXT: i8 5, label [[TMP6:%.*]] +; CHECK-NEXT: i8 6, label [[TMP7:%.*]] +; CHECK-NEXT: i8 7, label [[TMP8:%.*]] +; CHECK-NEXT: i8 8, label [[TMP9:%.*]] +; CHECK-NEXT: i8 9, label [[TMP10:%.*]] +; CHECK-NEXT: i8 49, label [[TMP11:%.*]] +; CHECK-NEXT: i8 50, label [[TMP12:%.*]] +; CHECK-NEXT: i8 51, label [[TMP13:%.*]] +; CHECK-NEXT: i8 52, label [[TMP14:%.*]] +; CHECK-NEXT: i8 53, label [[TMP15:%.*]] +; CHECK-NEXT: i8 54, label [[TMP16:%.*]] ; CHECK-NEXT: ] ; CHECK: 2: ; CHECK-NEXT: br label [[TMP18]] Index: test/Transforms/SimplifyCFG/switch-simplify-range.ll =================================================================== --- test/Transforms/SimplifyCFG/switch-simplify-range.ll +++ test/Transforms/SimplifyCFG/switch-simplify-range.ll @@ -8,26 +8,16 @@ define i64 @switch_common_right_bits(i8 %a) #0 { ; CHECK-LABEL: @switch_common_right_bits( ; CHECK-NEXT: Entry: -; CHECK-NEXT: switch i8 [[A:%.*]], label [[SWITCHELSE:%.*]] [ -; CHECK-NEXT: i8 123, label [[SWITCHPRONG:%.*]] -; CHECK-NEXT: i8 125, label [[SWITCHPRONG1:%.*]] -; CHECK-NEXT: i8 127, label [[SWITCHPRONG2:%.*]] -; CHECK-NEXT: i8 -127, label [[SWITCHPRONG3:%.*]] -; CHECK-NEXT: i8 -125, label [[SWITCHPRONG4:%.*]] -; CHECK-NEXT: ] +; CHECK-NEXT: [[TMP0:%.*]] = sub i8 [[A:%.*]], 123 +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.fshr.i8(i8 [[TMP0]], i8 [[TMP0]], i8 1) +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 5 +; CHECK-NEXT: br i1 [[TMP2]], label [[SWITCH_LOOKUP:%.*]], label [[SWITCHELSE:%.*]] +; CHECK: switch.lookup: +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* @switch.table.switch_common_right_bits, i32 0, i8 [[TMP1]] +; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, i64* [[SWITCH_GEP]] +; CHECK-NEXT: ret i64 [[SWITCH_LOAD]] ; CHECK: SwitchElse: -; CHECK-NEXT: [[MERGE:%.*]] = phi i64 [ 10, [[ENTRY:%.*]] ], [ 6, [[SWITCHPRONG]] ], [ 3, [[SWITCHPRONG1]] ], [ 4, [[SWITCHPRONG2]] ], [ 2, [[SWITCHPRONG3]] ], [ 1, [[SWITCHPRONG4]] ] -; CHECK-NEXT: ret i64 [[MERGE]] -; CHECK: SwitchProng: -; CHECK-NEXT: br label [[SWITCHELSE]] -; CHECK: SwitchProng1: -; CHECK-NEXT: br label [[SWITCHELSE]] -; CHECK: SwitchProng2: -; CHECK-NEXT: br label [[SWITCHELSE]] -; CHECK: SwitchProng3: -; CHECK-NEXT: br label [[SWITCHELSE]] -; CHECK: SwitchProng4: -; CHECK-NEXT: br label [[SWITCHELSE]] +; CHECK-NEXT: ret i64 10 ; Entry: switch i8 %a, label %SwitchElse [ @@ -166,11 +156,10 @@ define i16 @switch_not_normalized_to_start_at_zero(i8 %a) #0 { ; CHECK-LABEL: @switch_not_normalized_to_start_at_zero( ; CHECK-NEXT: Entry: -; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[A:%.*]], 1 -; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 5 +; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[A:%.*]], 6 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SWITCHELSE:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i16], [5 x i16]* @switch.table.switch_not_normalized_to_start_at_zero, i32 0, i8 [[SWITCH_TABLEIDX]] +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i16], [6 x i16]* @switch.table.switch_not_normalized_to_start_at_zero, i32 0, i8 [[A]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i16, i16* [[SWITCH_GEP]] ; CHECK-NEXT: ret i16 [[SWITCH_LOAD]] ; CHECK: SwitchElse: