Index: test/Transforms/SimplifyCFG/switch-dead-default.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch-dead-default.ll
+++ test/Transforms/SimplifyCFG/switch-dead-default.ll
@@ -1,11 +1,20 @@
-; RUN: opt %s -S -simplifycfg | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -S -simplifycfg -O3 | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 declare void @foo(i32)
 
 define void @test(i1 %a) {
-; CHECK-LABEL: @test
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    br i1 [[A:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   switch i1 %a, label %default [i1 1, label %true
-                                i1 0, label %false]
+  i1 0, label %false]
 true:
   call void @foo(i32 1)
   ret void
@@ -15,14 +24,35 @@
 default:
   call void @foo(i32 2)
   ret void
-}  
+}
 
 define void @test2(i2 %a) {
-; CHECK-LABEL: @test2
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT1:%.*]] [
+; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
+; CHECK-NEXT:    i2 -1, label [[CASE3:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       case2:
+; CHECK-NEXT:    tail call void @foo(i32 2)
+; CHECK-NEXT:    ret void
+; CHECK:       case3:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+; CHECK:       default1:
+; CHECK-NEXT:    unreachable
+;
   switch i2 %a, label %default [i2 0, label %case0
-                                i2 1, label %case1
-                                i2 2, label %case2
-                                i2 3, label %case3]
+  i2 1, label %case1
+  i2 2, label %case2
+  i2 3, label %case3]
 case0:
   call void @foo(i32 0)
   ret void
@@ -36,19 +66,35 @@
   call void @foo(i32 3)
   ret void
 default:
-; CHECK-LABEL: default1:
-; CHECK-NEXT: unreachable
   call void @foo(i32 4)
   ret void
-}  
+}
 
 ; This one is a negative test - we know the value of the default,
 ; but that's about it
 define void @test3(i2 %a) {
-; CHECK-LABEL: @test3
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       case2:
+; CHECK-NEXT:    tail call void @foo(i32 2)
+; CHECK-NEXT:    ret void
+; CHECK:       default:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+;
   switch i2 %a, label %default [i2 0, label %case0
-                                i2 1, label %case1
-                                i2 2, label %case2]
+  i2 1, label %case1
+  i2 2, label %case2]
 
 case0:
   call void @foo(i32 0)
@@ -60,18 +106,30 @@
   call void @foo(i32 2)
   ret void
 default:
-; CHECK-LABEL: default:
-; CHECK-NEXT: call void @foo
   call void @foo(i32 0)
   ret void
-}  
+}
 
 ; Negative test - check for possible overflow when computing
 ; number of possible cases.
 define void @test4(i128 %a) {
-; CHECK-LABEL: @test4
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i128 0, label [[CASE0:%.*]]
+; CHECK-NEXT:    i128 1, label [[CASE1:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       case0:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+; CHECK:       case1:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       default:
+; CHECK-NEXT:    tail call void @foo(i32 0)
+; CHECK-NEXT:    ret void
+;
   switch i128 %a, label %default [i128 0, label %case0
-                                  i128 1, label %case1]
+  i128 1, label %case1]
 
 case0:
   call void @foo(i32 0)
@@ -80,20 +138,28 @@
   call void @foo(i32 1)
   ret void
 default:
-; CHECK-LABEL: default:
-; CHECK-NEXT: call void @foo
   call void @foo(i32 0)
   ret void
-}  
+}
 
 ; All but one bit known zero
 define void @test5(i8 %a) {
-; CHECK-LABEL: @test5
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
-  %cmp = icmp ult i8 %a, 2 
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], 1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
+  %cmp = icmp ult i8 %a, 2
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 1, label %true
-                                i8 0, label %false]
+  i8 0, label %false]
 true:
   call void @foo(i32 1)
   ret void
@@ -103,18 +169,27 @@
 default:
   call void @foo(i32 2)
   ret void
-} 
+}
 
 ;; All but one bit known one
 define void @test6(i8 %a) {
-; CHECK-LABEL: @test6
-; CHECK: @llvm.assume
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[A:%.*]], -3
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], -1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   %and = and i8 %a, 254
-  %cmp = icmp eq i8 %and, 254 
+  %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false]
+  i8 254, label %false]
 true:
   call void @foo(i32 1)
   ret void
@@ -129,15 +204,24 @@
 ; Check that we can eliminate both dead cases and dead defaults
 ; within a single run of simplify-cfg
 define void @test7(i8 %a) {
-; CHECK-LABEL: @test7
-; CHECK: @llvm.assume
-; CHECK: br i1 [[IGNORE:%.*]], label %true, label %false
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[A:%.*]], -3
+; CHECK-NEXT:    tail call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp eq i8 [[A]], -1
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK:       true:
+; CHECK-NEXT:    tail call void @foo(i32 1)
+; CHECK-NEXT:    ret void
+; CHECK:       false:
+; CHECK-NEXT:    tail call void @foo(i32 3)
+; CHECK-NEXT:    ret void
+;
   %and = and i8 %a, 254
-  %cmp = icmp eq i8 %and, 254 
+  %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false
-                                i8 0, label %also_dead]
+  i8 254, label %false
+  i8 0, label %also_dead]
 true:
   call void @foo(i32 1)
   ret void
@@ -154,17 +238,18 @@
 
 ;; All but one bit known undef
 ;; Note: This is currently testing an optimization which doesn't trigger. The
-;; case this is protecting against is that a bit could be assumed both zero 
+;; case this is protecting against is that a bit could be assumed both zero
 ;; *or* one given we know it's undef.  ValueTracking doesn't do this today,
 ;; but it doesn't hurt to confirm.
 define void @test8(i8 %a) {
 ; CHECK-LABEL: @test8(
-; CHECK: switch i8
+; CHECK-NEXT:    unreachable
+;
   %and = and i8 %a, 254
   %cmp = icmp eq i8 %and, undef
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
-                                i8 254, label %false]
+  i8 254, label %false]
 true:
   call void @foo(i32 1)
   ret void
Index: test/Transforms/SimplifyCFG/switch-genfori8.ll
===================================================================
--- /dev/null
+++ test/Transforms/SimplifyCFG/switch-genfori8.ll
@@ -0,0 +1,149 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s | FileCheck %s
+; Using a Zig driver https://gist.github.com/shawnl/8137f62f7dbcfd539f6cf1925387cd38
+;after-patch, covered lookup table: 509.8MiB/sec
+;lookup table, not covered, only valid digits to prime the branch predictor: 437.8MiB/sec
+;lookup table, not covered, random bytes: 242.0MiB/sec
+;before-patch, no lookup table: 205.4MiB/sec
+
+; ModuleID = 'chartodigit.c'
+source_filename = "chartodigit.c"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+; Function Attrs: norecurse nounwind readnone uwtable
+define dso_local zeroext i8 @char_to_digit(i8 zeroext) local_unnamed_addr #0 {
+; CHECK-LABEL: @char_to_digit(
+; CHECK-NEXT:    switch i8 [[TMP0:%.*]], label [[TMP17:%.*]] [
+; CHECK-NEXT:    i8 48, label [[TMP18:%.*]]
+; CHECK-NEXT:    i8 49, label [[TMP2:%.*]]
+; CHECK-NEXT:    i8 50, label [[TMP3:%.*]]
+; CHECK-NEXT:    i8 51, label [[TMP4:%.*]]
+; CHECK-NEXT:    i8 52, label [[TMP5:%.*]]
+; CHECK-NEXT:    i8 53, label [[TMP6:%.*]]
+; CHECK-NEXT:    i8 54, label [[TMP7:%.*]]
+; CHECK-NEXT:    i8 55, label [[TMP8:%.*]]
+; CHECK-NEXT:    i8 56, label [[TMP9:%.*]]
+; CHECK-NEXT:    i8 57, label [[TMP10:%.*]]
+; CHECK-NEXT:    i8 97, label [[TMP11:%.*]]
+; CHECK-NEXT:    i8 98, label [[TMP12:%.*]]
+; CHECK-NEXT:    i8 99, label [[TMP13:%.*]]
+; CHECK-NEXT:    i8 100, label [[TMP14:%.*]]
+; CHECK-NEXT:    i8 101, label [[TMP15:%.*]]
+; CHECK-NEXT:    i8 102, label [[TMP16:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       2:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       3:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       4:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       5:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       6:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       7:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       8:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       9:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       10:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       11:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       12:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       13:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       14:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       15:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       16:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       17:
+; CHECK-NEXT:    br label [[TMP18]]
+; CHECK:       18:
+; CHECK-NEXT:    [[TMP19:%.*]] = phi i8 [ -1, [[TMP17]] ], [ 15, [[TMP16]] ], [ 14, [[TMP15]] ], [ 13, [[TMP14]] ], [ 12, [[TMP13]] ], [ 11, [[TMP12]] ], [ 10, [[TMP11]] ], [ 9, [[TMP10]] ], [ 8, [[TMP9]] ], [ 7, [[TMP8]] ], [ 6, [[TMP7]] ], [ 5, [[TMP6]] ], [ 4, [[TMP5]] ], [ 3, [[TMP4]] ], [ 2, [[TMP3]] ], [ 1, [[TMP2]] ], [ 0, [[TMP1:%.*]] ]
+; CHECK-NEXT:    ret i8 [[TMP19]]
+;
+  switch i8 %0, label %17 [
+  i8 48, label %18
+  i8 49, label %2
+  i8 50, label %3
+  i8 51, label %4
+  i8 52, label %5
+  i8 53, label %6
+  i8 54, label %7
+  i8 55, label %8
+  i8 56, label %9
+  i8 57, label %10
+  i8 97, label %11
+  i8 98, label %12
+  i8 99, label %13
+  i8 100, label %14
+  i8 101, label %15
+  i8 102, label %16
+  ]
+
+; <label>:2:                                      ; preds = %1
+  br label %18
+
+; <label>:3:                                      ; preds = %1
+  br label %18
+
+; <label>:4:                                      ; preds = %1
+  br label %18
+
+; <label>:5:                                      ; preds = %1
+  br label %18
+
+; <label>:6:                                      ; preds = %1
+  br label %18
+
+; <label>:7:                                      ; preds = %1
+  br label %18
+
+; <label>:8:                                      ; preds = %1
+  br label %18
+
+; <label>:9:                                      ; preds = %1
+  br label %18
+
+; <label>:10:                                     ; preds = %1
+  br label %18
+
+; <label>:11:                                     ; preds = %1
+  br label %18
+
+; <label>:12:                                     ; preds = %1
+  br label %18
+
+; <label>:13:                                     ; preds = %1
+  br label %18
+
+; <label>:14:                                     ; preds = %1
+  br label %18
+
+; <label>:15:                                     ; preds = %1
+  br label %18
+
+; <label>:16:                                     ; preds = %1
+  br label %18
+
+; <label>:17:                                     ; preds = %1
+  br label %18
+
+; <label>:18:                                     ; preds = %1, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5, %4, %3, %2
+  %19 = phi i8 [ -1, %17 ], [ 15, %16 ], [ 14, %15 ], [ 13, %14 ], [ 12, %13 ], [ 11, %12 ], [ 10, %11 ], [ 9, %10 ], [ 8, %9 ], [ 7, %8 ], [ 6, %7 ], [ 5, %6 ], [ 4, %5 ], [ 3, %4 ], [ 2, %3 ], [ 1, %2 ], [ 0, %1 ]
+  ret i8 %19
+}
+
+attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 8.0.0-3 (tags/RELEASE_800/final)"}
Index: test/Transforms/SimplifyCFG/switch-masked-bits.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch-masked-bits.ll
+++ test/Transforms/SimplifyCFG/switch-masked-bits.ll
@@ -4,10 +4,10 @@
 define i32 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  a:
-; CHECK-NEXT:    [[I:%.*]] = shl i32 %x, 1
+; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
-; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0
-; CHECK-NEXT:    ret i32 [[DOT]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 5, i32 0
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ;
   %i = shl i32 %x, 1
   switch i32 %i, label %a [
@@ -48,12 +48,19 @@
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
-; CHECK:         switch i32
-; CHECK-DAG:     i32 -128, label %a
-; CHECK-DAG:     i32 -1, label %a
-; CHECK-DAG:     i32  0, label %a
-; CHECK-DAG:     i32  127, label %a
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[A:%.*]]
+; CHECK-NEXT:    i32 127, label [[A]]
+; CHECK-NEXT:    i32 -128, label [[A]]
+; CHECK-NEXT:    i32 -1, label [[A]]
 ; CHECK-NEXT:    ]
+; CHECK:       a:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
+; CHECK-NEXT:    ret i1 [[MERGE]]
+; CHECK:       default:
+; CHECK-NEXT:    br label [[A]]
 ;
 entry:
   %sext = sext i8 %condition to i32
Index: test/Transforms/SimplifyCFG/switch-on-const-select.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch-on-const-select.ll
+++ test/Transforms/SimplifyCFG/switch-on-const-select.ll
@@ -1,136 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -S | FileCheck -enable-var-scope %s
 
 ; Test basic folding to a conditional branch.
 define i32 @foo(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]]
+; CHECK:       switch:
+; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
+; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B]]
+; CHECK:       a:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret i32 1
+; CHECK:       b:
+; CHECK-NEXT:    [[RETVAL:%.*]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    tail call void @bees.b() #0
+; CHECK-NEXT:    ret i32 [[RETVAL]]
+;
 entry:
-    %eq = icmp eq i64 %x, %y
-    br i1 %eq, label %b, label %switch
+  %eq = icmp eq i64 %x, %y
+  br i1 %eq, label %b, label %switch
 switch:
-    %lt = icmp slt i64 %x, %y
-; CHECK: br i1 %lt, label %a, label %b
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %b
-        i32 2, label %b
-    ]
+  %lt = icmp slt i64 %x, %y
+  %qux = select i1 %lt, i32 0, i32 2
+  switch i32 %qux, label %bees [
+  i32 0, label %a
+  i32 1, label %b
+  i32 2, label %b
+  ]
 a:
-    tail call void @bees.a() nounwind
-    ret i32 1
-; CHECK: b:
-; CHECK-NEXT: %retval = phi i32 [ 0, %switch ], [ 2, %entry ]
+  tail call void @bees.a() nounwind
+  ret i32 1
 b:
-    %retval = phi i32 [0, %switch], [0, %switch], [2, %entry]
-    tail call void @bees.b() nounwind
-    ret i32 %retval
-; CHECK-NOT: bees:
+  %retval = phi i32 [0, %switch], [0, %switch], [2, %entry]
+  tail call void @bees.b() nounwind
+  ret i32 %retval
 bees:
-    tail call void @llvm.trap() nounwind
-    unreachable
+  tail call void @llvm.trap() nounwind
+  unreachable
 }
 
 ; Test basic folding to an unconditional branch.
 define i32 @bar(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bar(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret i32 0
+;
 entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[$NUW:#[0-9]+]]
-; CHECK-NEXT: ret i32 0
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %b
-        i32 2, label %a
-    ]
+  %lt = icmp slt i64 %x, %y
+  %qux = select i1 %lt, i32 0, i32 2
+  switch i32 %qux, label %bees [
+  i32 0, label %a
+  i32 1, label %b
+  i32 2, label %a
+  ]
 a:
-    %retval = phi i32 [0, %entry], [0, %entry], [1, %b]
-    tail call void @bees.a() nounwind
-    ret i32 0
+  %retval = phi i32 [0, %entry], [0, %entry], [1, %b]
+  tail call void @bees.a() nounwind
+  ret i32 0
 b:
-    tail call void @bees.b() nounwind
-    br label %a
+  tail call void @bees.b() nounwind
+  br label %a
 bees:
-    tail call void @llvm.trap() nounwind
-    unreachable
+  tail call void @llvm.trap() nounwind
+  unreachable
 }
 
 ; Test the edge case where both values from the select are the default case.
 define void @bazz(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bazz(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.b() #0
+; CHECK-NEXT:    ret void
+;
 entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.b() [[$NUW]]
-; CHECK-NEXT: ret void
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 10, i32 12
-    switch i32 %qux, label %b [
-        i32 0, label %a
-        i32 1, label %bees
-        i32 2, label %bees
-    ]
+  %lt = icmp slt i64 %x, %y
+  %qux = select i1 %lt, i32 10, i32 12
+  switch i32 %qux, label %b [
+  i32 0, label %a
+  i32 1, label %bees
+  i32 2, label %bees
+  ]
 a:
-    tail call void @bees.a() nounwind
-    ret void
+  tail call void @bees.a() nounwind
+  ret void
 b:
-    tail call void @bees.b() nounwind
-    ret void
+  tail call void @bees.b() nounwind
+  ret void
 bees:
-    tail call void @llvm.trap()
-    unreachable
+  tail call void @llvm.trap()
+  unreachable
 }
 
 ; Test the edge case where both values from the select are equal.
 define void @quux(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @quux(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    tail call void @bees.a() #0
+; CHECK-NEXT:    ret void
+;
 entry:
-; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[$NUW]]
-; CHECK-NEXT: ret void
-    %lt = icmp slt i64 %x, %y
-    %qux = select i1 %lt, i32 0, i32 0
-    switch i32 %qux, label %b [
-        i32 0, label %a
-        i32 1, label %bees
-        i32 2, label %bees
-    ]
+  %lt = icmp slt i64 %x, %y
+  %qux = select i1 %lt, i32 0, i32 0
+  switch i32 %qux, label %b [
+  i32 0, label %a
+  i32 1, label %bees
+  i32 2, label %bees
+  ]
 a:
-    tail call void @bees.a() nounwind
-    ret void
+  tail call void @bees.a() nounwind
+  ret void
 b:
-    tail call void @bees.b() nounwind
-    ret void
+  tail call void @bees.b() nounwind
+  ret void
 bees:
-    tail call void @llvm.trap()
-    unreachable
+  tail call void @llvm.trap()
+  unreachable
 }
 
 ; A final test, for phi node munging.
 define i32 @xyzzy(i64 %x, i64 %y) {
 ; CHECK-LABEL: @xyzzy(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1
+; CHECK-NEXT:    [[VAL:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    ret i32 [[VAL]]
+;
 entry:
-    %eq = icmp eq i64 %x, %y
-    br i1 %eq, label %r, label %cont
+  %eq = icmp eq i64 %x, %y
+  br i1 %eq, label %r, label %cont
 cont:
-; CHECK: %lt = icmp slt i64 %x, %y
-    %lt = icmp slt i64 %x, %y
-; CHECK-NEXT: select i1 %lt, i32 -1, i32 1
-    %qux = select i1 %lt, i32 0, i32 2
-    switch i32 %qux, label %bees [
-        i32 0, label %a
-        i32 1, label %r
-        i32 2, label %r
-    ]
+  %lt = icmp slt i64 %x, %y
+  %qux = select i1 %lt, i32 0, i32 2
+  switch i32 %qux, label %bees [
+  i32 0, label %a
+  i32 1, label %r
+  i32 2, label %r
+  ]
 r:
-    %val = phi i32 [0, %entry], [1, %cont], [1, %cont]
-    ret i32 %val
+  %val = phi i32 [0, %entry], [1, %cont], [1, %cont]
+  ret i32 %val
 a:
-    ret i32 -1
-; CHECK-NOT: bees:
+  ret i32 -1
 bees:
-    tail call void @llvm.trap()
-    unreachable
+  tail call void @llvm.trap()
+  unreachable
 }
 
 declare void @llvm.trap() nounwind noreturn
Index: test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
+++ test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
@@ -1,18 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -simplifycfg -S | FileCheck %s
 
 declare i32 @f(i32)
 
 define i32 @basic(i32 %x) {
-; CHECK-LABEL: @basic
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %default
+; CHECK-LABEL: @basic(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[DEFAULT:%.*]]
+; CHECK:       default:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   switch i32 %x, label %default [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
+  i32 5, label %a
+  i32 6, label %a
+  i32 7, label %a
   ]
 default:
   %0 = call i32 @f(i32 0)
@@ -24,20 +33,28 @@
 
 
 define i32 @unreachable(i32 %x) {
-; CHECK-LABEL: @unreachable
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %b
+; CHECK-LABEL: @unreachable(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       b:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   switch i32 %x, label %unreachable [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
-    i32 10, label %b
-    i32 20, label %b
-    i32 30, label %b
-    i32 40, label %b
+  i32 5, label %a
+  i32 6, label %a
+  i32 7, label %a
+  i32 10, label %b
+  i32 20, label %b
+  i32 30, label %b
+  i32 40, label %b
   ]
 unreachable:
   unreachable
@@ -51,20 +68,28 @@
 
 
 define i32 @unreachable2(i32 %x) {
-; CHECK-LABEL: @unreachable2
-; CHECK: x.off = add i32 %x, -5
-; CHECK: %switch = icmp ult i32 %x.off, 3
-; CHECK: br i1 %switch, label %a, label %b
+; CHECK-LABEL: @unreachable2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
+; CHECK:       a:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
+; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK:       b:
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
 
 entry:
   ; Note: folding the most popular case destination into the default
   ; would prevent switch-to-icmp here.
   switch i32 %x, label %unreachable [
-    i32 5, label %a
-    i32 6, label %a
-    i32 7, label %a
-    i32 10, label %b
-    i32 20, label %b
+  i32 5, label %a
+  i32 6, label %a
+  i32 7, label %a
+  i32 10, label %b
+  i32 20, label %b
   ]
 unreachable:
   unreachable
Index: test/Transforms/SimplifyCFG/switch-simplify-range.ll
===================================================================
--- /dev/null
+++ test/Transforms/SimplifyCFG/switch-simplify-range.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes='simplify-cfg<switch-to-lookup>' < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+attributes #0 = { "no-jump-tables"="false" }
+
+define i64 @switch_common_right_bits(i8 %a) #0  {
+; CHECK-LABEL: @switch_common_right_bits(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i8 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i8 123, label [[SWITCHPRONG:%.*]]
+; CHECK-NEXT:    i8 125, label [[SWITCHPRONG1:%.*]]
+; CHECK-NEXT:    i8 127, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i8 -127, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i8 -125, label [[SWITCHPRONG4:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 10, [[ENTRY:%.*]] ], [ 6, [[SWITCHPRONG]] ], [ 3, [[SWITCHPRONG1]] ], [ 4, [[SWITCHPRONG2]] ], [ 2, [[SWITCHPRONG3]] ], [ 1, [[SWITCHPRONG4]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng1:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng4:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 123, label %SwitchProng
+  i8 125, label %SwitchProng1
+  i8 127, label %SwitchProng2
+  i8 129, label %SwitchProng3
+  i8 131, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i64 10
+SwitchProng:                                      ; preds = %Entry
+  ret i64 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i64 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 4
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 2
+SwitchProng4:                                     ; preds = %Entry
+  ret i64 1
+}
+
+define i64 @switch_clz1(i16 %a) optsize #0  {
+; CHECK-LABEL: @switch_clz1(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i16 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i16 2, label [[SWITCHPRONG:%.*]]
+; CHECK-NEXT:    i16 4, label [[SWITCHPRONG1:%.*]]
+; CHECK-NEXT:    i16 8, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i16 1, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i16 64, label [[SWITCHPRONG6:%.*]]
+; CHECK-NEXT:    i16 128, label [[SWITCHPRONG7:%.*]]
+; CHECK-NEXT:    i16 16, label [[SWITCHPRONG5:%.*]]
+; CHECK-NEXT:    i16 32, label [[SWITCHPRONG4:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 10, [[ENTRY:%.*]] ], [ 6, [[SWITCHPRONG]] ], [ 3, [[SWITCHPRONG1]] ], [ 35, [[SWITCHPRONG2]] ], [ 31, [[SWITCHPRONG3]] ], [ 53, [[SWITCHPRONG4]] ], [ 51, [[SWITCHPRONG5]] ], [ 41, [[SWITCHPRONG6]] ], [ 34, [[SWITCHPRONG7]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng1:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng4:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng5:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng6:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+; CHECK:       SwitchProng7:
+; CHECK-NEXT:    br label [[SWITCHELSE]]
+;
+Entry:
+  switch i16 %a, label %SwitchElse [
+  i16 2, label %SwitchProng
+  i16 4, label %SwitchProng1
+  i16 8, label %SwitchProng2
+  i16 1, label %SwitchProng3
+  i16 64, label %SwitchProng6
+  i16 128, label %SwitchProng7
+  i16 16, label %SwitchProng5
+  i16 32, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i64 10
+SwitchProng:                                      ; preds = %Entry
+  ret i64 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i64 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 35
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 31
+SwitchProng4:                                     ; preds = %Entry
+  ret i64 53
+SwitchProng5:                                     ; preds = %Entry
+  ret i64 51
+SwitchProng6:                                     ; preds = %Entry
+  ret i64 41
+SwitchProng7:                                     ; preds = %Entry
+  ret i64 34
+}
+
+define i64 @switch_clz2(i8 %a) optsize #0  {
+; CHECK-LABEL: @switch_clz2(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    switch i8 [[A:%.*]], label [[SWITCHELSE:%.*]] [
+; CHECK-NEXT:    i8 -128, label [[SWITCHPRONG2:%.*]]
+; CHECK-NEXT:    i8 64, label [[SWITCHPRONG3:%.*]]
+; CHECK-NEXT:    i8 32, label [[SWITCHPRONG6:%.*]]
+; CHECK-NEXT:    i8 1, label [[SWITCHPRONG7:%.*]]
+; CHECK-NEXT:    i8 0, label [[SWITCHPRONG5:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       SwitchProng2:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i64 [ 35, [[ENTRY:%.*]] ], [ 31, [[SWITCHPRONG3]] ], [ 41, [[SWITCHPRONG6]] ], [ 40, [[SWITCHPRONG5]] ], [ 43, [[SWITCHPRONG7]] ], [ 12, [[SWITCHELSE]] ]
+; CHECK-NEXT:    ret i64 [[MERGE]]
+; CHECK:       SwitchProng3:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng6:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng5:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchProng7:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    br label [[SWITCHPRONG2]]
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 128, label %SwitchProng2
+  i8 64, label %SwitchProng3
+  i8 32, label %SwitchProng6
+  i8 1, label %SwitchProng7
+  i8 0, label %SwitchProng5
+  ]
+SwitchProng2:                                     ; preds = %Entry
+  ret i64 35
+SwitchProng3:                                     ; preds = %Entry
+  ret i64 31
+SwitchProng6:                                     ; preds = %Entry
+  ret i64 41
+SwitchProng5:                                     ; preds = %Entry
+  ret i64 40
+SwitchProng7:                                     ; preds = %Entry
+  ret i64 43
+SwitchElse:                                     ; preds = %Entry
+  ret i64 12
+}
+
+;Must check that the default was filled in at index 0 as happened here:
+;@switch.table.switch_not_normalized_to_start_at_zero = private unnamed_addr constant [6 x i16] [i16 10, i16 7, i16 3, i16 1, i16 6, i16 8], align 2
+define i16 @switch_not_normalized_to_start_at_zero(i8 %a) #0  {
+; CHECK-LABEL: @switch_not_normalized_to_start_at_zero(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = sub i8 [[A:%.*]], 1
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 5
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SWITCHELSE:%.*]]
+; CHECK:       switch.lookup:
+; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [5 x i16], [5 x i16]* @switch.table.switch_not_normalized_to_start_at_zero, i32 0, i8 [[SWITCH_TABLEIDX]]
+; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i16, i16* [[SWITCH_GEP]]
+; CHECK-NEXT:    ret i16 [[SWITCH_LOAD]]
+; CHECK:       SwitchElse:
+; CHECK-NEXT:    ret i16 10
+;
+Entry:
+  switch i8 %a, label %SwitchElse [
+  i8 4, label %SwitchProng
+  i8 2, label %SwitchProng1
+  i8 1, label %SwitchProng2
+  i8 3, label %SwitchProng3
+  i8 5, label %SwitchProng4
+  ]
+SwitchElse:                                       ; preds = %Entry
+  ret i16 10
+SwitchProng:                                      ; preds = %Entry
+  ret i16 6
+SwitchProng1:                                     ; preds = %Entry
+  ret i16 3
+SwitchProng2:                                     ; preds = %Entry
+  ret i16 7
+SwitchProng3:                                     ; preds = %Entry
+  ret i16 1
+SwitchProng4:                                     ; preds = %Entry
+  ret i16 8
+}
Index: test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
+++ test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 target datalayout="p:40:64:64:32"
 
@@ -6,35 +7,54 @@
 declare void @foo2()
 
 define void @test1(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1(
-; CHECK:  switch i32 %V, label %F [
-; CHECK:    i32 17, label %T
-; CHECK:    i32 4, label %T
-; CHECK:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test1_ptr(i32* %V) {
-        %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
-        %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1_ptr(
+; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
+  %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr(
+  call void @foo2( )
+  ret void
 ; DL:  %magicptr = ptrtoint i32* %V to i32
 ; DL:  switch i32 %magicptr, label %F [
 ; DL:    i32 17, label %T
@@ -43,17 +63,29 @@
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
-        %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
-        %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1_ptr_as1(
+; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i32
+; CHECK-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
+  %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr_as1(
+  call void @foo2( )
+  ret void
 ; DL:  %magicptr = ptrtoint i32 addrspace(1)* %V to i16
 ; DL:  switch i16 %magicptr, label %F [
 ; DL:    i16 17, label %T
@@ -62,46 +94,74 @@
 }
 
 define void @test2(i32 %V) {
-        %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
-        %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 17, label [[F:%.*]]
+; CHECK-NEXT:    i32 4, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
+  %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test2(
-; CHECK:  switch i32 %V, label %T [
-; CHECK:    i32 17, label %F
-; CHECK:    i32 4, label %F
-; CHECK:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test3(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        br i1 %C1, label %T, label %N
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 4, label [[T:%.*]]
+; CHECK-NEXT:    i32 17, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  br i1 %C1, label %T, label %N
 N:              ; preds = %0
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        br i1 %C2, label %T, label %F
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %N
-        call void @foo2( )
-        ret void
+  call void @foo2( )
+  ret void
 
-; CHECK-LABEL: @test3(
-; CHECK: switch i32 %V, label %F [
-; CHECK:     i32 4, label %T
-; CHECK:     i32 17, label %T
-; CHECK:   ]
 }
 
 
 
 define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   %cmp = icmp eq i8 %c, 62
   br i1 %cmp, label %lor.end, label %lor.lhs.false
@@ -119,20 +179,28 @@
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK-LABEL: @test4(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   switch i8 %c, label %lor.rhs [
-    i8 62, label %lor.end
-    i8 34, label %lor.end
-    i8 92, label %lor.end
+  i8 62, label %lor.end
+  i8 34, label %lor.end
+  i8 92, label %lor.end
   ]
 
 lor.rhs:                                          ; preds = %entry
@@ -143,48 +211,63 @@
   %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
-; CHECK-LABEL: @test5(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 
 define i1 @test6({ i32, i32 }* %I) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]]
+; CHECK-NEXT:    [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
 entry:
-        %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
-        %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
-        %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
-        br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
+  %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
+  %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
+  %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
+  br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
 shortcirc_next.0:               ; preds = %entry
-        %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
-        br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
+  %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
+  br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
 shortcirc_next.1:               ; preds = %shortcirc_next.0
-        %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
-        br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
+  %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
+  br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
 shortcirc_next.2:               ; preds = %shortcirc_next.1
-        %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
-        br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
+  %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
+  br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
 shortcirc_next.3:               ; preds = %shortcirc_next.2
-        %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
-        br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
+  %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
+  br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
 shortcirc_next.4:               ; preds = %shortcirc_next.3
-        %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
-        br label %UnifiedReturnBlock
+  %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
+  br label %UnifiedReturnBlock
 shortcirc_done.4:               ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
-        br label %UnifiedReturnBlock
+  br label %UnifiedReturnBlock
 UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
-        %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
-        ret i1 %UnifiedRetVal
+  %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
+  ret i1 %UnifiedRetVal
 
-; CHECK-LABEL: @test6(
-; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
-; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret void
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
@@ -200,17 +283,27 @@
 if.end:                                           ; preds = %entry
   ret void
 
-; CHECK-LABEL: @test7(
-; CHECK:   %cmp = icmp ult i32 %x, 32
-; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
+; CHECK:       N:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 0
+;
 entry:
   br i1 %C, label %N, label %if.then
 N:
@@ -229,17 +322,33 @@
 if.end:                                           ; preds = %entry
   ret i32 0
 
-; CHECK-LABEL: @test8(
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
-; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
 ;; This is "Example 7" from http://blog.regehr.org/archives/320
 define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    i8 62, label [[LOR_END]]
+; CHECK-NEXT:    i8 60, label [[LOR_END]]
+; CHECK-NEXT:    i8 59, label [[LOR_END]]
+; CHECK-NEXT:    i8 58, label [[LOR_END]]
+; CHECK-NEXT:    i8 46, label [[LOR_END]]
+; CHECK-NEXT:    i8 44, label [[LOR_END]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 39, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    [[CONV46:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[CONV46]]
+;
 entry:
   %cmp = icmp ult i8 %c, 33
   br i1 %cmp, label %lor.end, label %lor.lhs.false
@@ -285,25 +394,23 @@
   %conv46 = zext i1 %0 to i32
   ret i32 %conv46
 
-; CHECK-LABEL: @test9(
-; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
-
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 51, label [[F]]
+; CHECK-NEXT:    i32 0, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       F:
+; CHECK-NEXT:    br label [[T]]
+;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
@@ -314,17 +421,27 @@
 F:
   ret i32 324
 
-; CHECK-LABEL: @test10(
-; CHECK:  br i1 %Cond, label %switch.early.test, label %F
-; CHECK:switch.early.test:
-; CHECK:  switch i32 %mode, label %T [
-; CHECK:    i32 51, label %F
-; CHECK:    i32 0, label %F
-; CHECK:  ]
 }
 
 ; PR8780
 define i32 @test11(i32 %bar) nounwind {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 55, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 53, label [[RETURN]]
+; CHECK-NEXT:    i32 35, label [[RETURN]]
+; CHECK-NEXT:    i32 24, label [[RETURN]]
+; CHECK-NEXT:    i32 23, label [[RETURN]]
+; CHECK-NEXT:    i32 12, label [[RETURN]]
+; CHECK-NEXT:    i32 4, label [[RETURN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.end:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   %cmp = icmp eq i32 %bar, 4
   %cmp2 = icmp eq i32 %bar, 35
@@ -353,19 +470,21 @@
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @test11(
-; CHECK: switch i32 %bar, label %if.end [
-; CHECK:   i32 55, label %return
-; CHECK:   i32 53, label %return
-; CHECK:   i32 35, label %return
-; CHECK:   i32 24, label %return
-; CHECK:   i32 23, label %return
-; CHECK:   i32 12, label %return
-; CHECK:   i32 4, label %return
-; CHECK: ]
 }
 
 define void @test12() nounwind {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK:       bb55.us.us:
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK:       malformed:
+; CHECK-NEXT:    ret void
+;
 entry:
   br label %bb49.us.us
 
@@ -382,12 +501,26 @@
 
 malformed:
   ret void
-; CHECK-LABEL: @test12(
 
 }
 
 ; test13 - handle switch formation with ult.
 define void @test13(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 2
   br i1 %cmp, label %if.then, label %lor.lhs.false3
@@ -410,18 +543,26 @@
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test13(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; test14 - handle switch formation with ult.
 define void @test14(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 2, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ugt i32 %x, 2
   br i1 %cmp, label %lor.lhs.false3, label %if.then
@@ -444,18 +585,15 @@
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test14(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; Don't crash on ginormous ranges.
 define void @test15(i128 %x) nounwind {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:  if.end:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ugt i128 %x, 2
   br i1 %cmp, label %if.end, label %lor.false
 
@@ -470,18 +608,19 @@
 if.end:
   ret void
 
-; CHECK-LABEL: @test15(
-; CHECK-NOT: switch
-; CHECK: ret void
 }
 
 ; PR8675
 ; rdar://5134905
 define zeroext i1 @test16(i32 %x) nounwind {
-entry:
 ; CHECK-LABEL: @test16(
-; CHECK: %x.off = add i32 %x, -1
-; CHECK: %switch = icmp ult i32 %x.off, 3
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
+entry:
   %cmp.i = icmp eq i32 %x, 1
   br i1 %cmp.i, label %lor.end, label %lor.lhs.false
 
@@ -500,6 +639,17 @@
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
+; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK:       lor.lhs.false8:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
@@ -512,13 +662,20 @@
 return:
   ret void
 
-; CHECK-LABEL: @test17(
-; CHECK-NOT: switch.early.test
-; CHECK-NOT: switch i32
-; CHECK: ret void
 }
 
 define void @test18(i32 %arg) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]]
+; CHECK:       bb19:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    br label [[BB20]]
+; CHECK:       bb20:
+; CHECK-NEXT:    ret void
+;
 bb:
   %tmp = and i32 %arg, -2
   %tmp1 = icmp eq i32 %tmp, 8
@@ -550,12 +707,23 @@
 bb20:                                             ; preds = %bb19, %bb8
   ret void
 
-; CHECK-LABEL: @test18(
-; CHECK: %arg.off = add i32 %arg, -8
-; CHECK: icmp ult i32 %arg.off, 11
 }
 
 define void @PR26323(i1 %tobool23, i32 %tmp3) {
+; CHECK-LABEL: @PR26323(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0
+; CHECK-NEXT:    [[NEG14:%.*]] = and i32 [[TMP3]], -2
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]]
+; CHECK-NEXT:    [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]]
+; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]]
+; CHECK:       if.then27:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    unreachable
+; CHECK:       if.end29:
+; CHECK-NEXT:    ret void
+;
 entry:
   %tobool5 = icmp ne i32 %tmp3, 0
   %neg14 = and i32 %tmp3, -2
@@ -587,6 +755,18 @@
 ; CHECK: i32 13, label %if
 ; CHECK: i32 12, label %if
 define void @test19(i32 %arg) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    i32 32, label [[IF:%.*]]
+; CHECK-NEXT:    i32 13, label [[IF]]
+; CHECK-NEXT:    i32 12, label [[IF]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
@@ -606,6 +786,18 @@
 ; CHECK-NOT: switch
 ; CHECK: ret void
 define void @test20(i32 %arg) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
@@ -626,6 +818,18 @@
 ; CHECK: i32 13, label %else
 ; CHECK: i32 12, label %else
 define void @test21(i32 %arg) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
+; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
+; CHECK-NEXT:    i32 13, label [[ELSE]]
+; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
@@ -645,6 +849,18 @@
 ; CHECK-NOT: switch
 ; CHECK: ret void
 define void @test22(i32 %arg) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
@@ -657,4 +873,4 @@
 
 else:
   ret void
-}
\ No newline at end of file
+}
Index: test/Transforms/SimplifyCFG/switch_create.ll
===================================================================
--- test/Transforms/SimplifyCFG/switch_create.ll
+++ test/Transforms/SimplifyCFG/switch_create.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg < %s | FileCheck %s
 ; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
 
@@ -6,102 +7,151 @@
 declare void @foo2()
 
 define void @test1(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 17, label [[T:%.*]]
+; CHECK-NEXT:    i32 4, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1(
-; CHECK:  switch i32 %V, label %F [
-; CHECK:    i32 17, label %T
-; CHECK:    i32 4, label %T
-; CHECK:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test1_ptr(i32* %V) {
-        %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
-        %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; DL-LABEL: @test1_ptr(
+; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
+; DL-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
+; DL-NEXT:    i32 17, label [[T:%.*]]
+; DL-NEXT:    i32 4, label [[T]]
+; DL-NEXT:    ]
+; DL:       T:
+; DL-NEXT:    call void @foo1()
+; DL-NEXT:    ret void
+; DL:       F:
+; DL-NEXT:    call void @foo2()
+; DL-NEXT:    ret void
+;
+  %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
+  %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr(
-; DL:  %magicptr = ptrtoint i32* %V to i32
-; DL:  switch i32 %magicptr, label %F [
-; DL:    i32 17, label %T
-; DL:    i32 4, label %T
-; DL:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
-        %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
-        %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
-        %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; DL-LABEL: @test1_ptr_as1(
+; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16
+; DL-NEXT:    switch i16 [[MAGICPTR]], label [[F:%.*]] [
+; DL-NEXT:    i16 17, label [[T:%.*]]
+; DL-NEXT:    i16 4, label [[T]]
+; DL-NEXT:    ]
+; DL:       T:
+; DL-NEXT:    call void @foo1()
+; DL-NEXT:    ret void
+; DL:       F:
+; DL-NEXT:    call void @foo2()
+; DL-NEXT:    ret void
+;
+  %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
+  %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
+  %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test1_ptr_as1(
-; DL:  %magicptr = ptrtoint i32 addrspace(1)* %V to i16
-; DL:  switch i16 %magicptr, label %F [
-; DL:    i16 17, label %T
-; DL:    i16 4, label %T
-; DL:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test2(i32 %V) {
-        %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
-        %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
-        %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
-        br i1 %CN, label %T, label %F
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 17, label [[F:%.*]]
+; CHECK-NEXT:    i32 4, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
+  %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
+  %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
+  br i1 %CN, label %T, label %F
 T:              ; preds = %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %0
-        call void @foo2( )
-        ret void
-; CHECK-LABEL: @test2(
-; CHECK:  switch i32 %V, label %T [
-; CHECK:    i32 17, label %F
-; CHECK:    i32 4, label %F
-; CHECK:  ]
+  call void @foo2( )
+  ret void
 }
 
 define void @test3(i32 %V) {
-        %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
-        br i1 %C1, label %T, label %N
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
+; CHECK-NEXT:    i32 4, label [[T:%.*]]
+; CHECK-NEXT:    i32 17, label [[T]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       F:
+; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    ret void
+;
+  %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
+  br i1 %C1, label %T, label %N
 N:              ; preds = %0
-        %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
-        br i1 %C2, label %T, label %F
+  %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
+  br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0
-        call void @foo1( )
-        ret void
+  call void @foo1( )
+  ret void
 F:              ; preds = %N
-        call void @foo2( )
-        ret void
+  call void @foo2( )
+  ret void
 
-; CHECK-LABEL: @test3(
-; CHECK: switch i32 %V, label %F [
-; CHECK:     i32 4, label %T
-; CHECK:     i32 17, label %T
-; CHECK:   ]
 }
 
 
 
 define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   %cmp = icmp eq i8 %c, 62
   br i1 %cmp, label %lor.end, label %lor.lhs.false
@@ -119,20 +169,28 @@
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK-LABEL: @test4(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 62, label [[LOR_END:%.*]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    [[LOR_EXT:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[LOR_EXT]]
+;
 entry:
   switch i8 %c, label %lor.rhs [
-    i8 62, label %lor.end
-    i8 34, label %lor.end
-    i8 92, label %lor.end
+  i8 62, label %lor.end
+  i8 34, label %lor.end
+  i8 92, label %lor.end
   ]
 
 lor.rhs:                                          ; preds = %entry
@@ -143,48 +201,63 @@
   %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
-; CHECK-LABEL: @test5(
-; CHECK:  switch i8 %c, label %lor.rhs [
-; CHECK:    i8 62, label %lor.end
-; CHECK:    i8 34, label %lor.end
-; CHECK:    i8 92, label %lor.end
-; CHECK:  ]
 }
 
 
 define i1 @test6({ i32, i32 }* %I) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP_1_I:%.*]] = getelementptr { i32, i32 }, { i32, i32 }* [[I:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP_2_I:%.*]] = load i32, i32* [[TMP_1_I]]
+; CHECK-NEXT:    [[TMP_2_I_OFF:%.*]] = add i32 [[TMP_2_I]], -14
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[TMP_2_I_OFF]], 6
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
 entry:
-        %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
-        %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
-        %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
-        br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
+  %tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1         ; <i32*> [#uses=1]
+  %tmp.2.i = load i32, i32* %tmp.1.i           ; <i32> [#uses=6]
+  %tmp.2 = icmp eq i32 %tmp.2.i, 14               ; <i1> [#uses=1]
+  br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
 shortcirc_next.0:               ; preds = %entry
-        %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
-        br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
+  %tmp.6 = icmp eq i32 %tmp.2.i, 15               ; <i1> [#uses=1]
+  br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
 shortcirc_next.1:               ; preds = %shortcirc_next.0
-        %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
-        br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
+  %tmp.11 = icmp eq i32 %tmp.2.i, 16              ; <i1> [#uses=1]
+  br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
 shortcirc_next.2:               ; preds = %shortcirc_next.1
-        %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
-        br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
+  %tmp.16 = icmp eq i32 %tmp.2.i, 17              ; <i1> [#uses=1]
+  br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
 shortcirc_next.3:               ; preds = %shortcirc_next.2
-        %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
-        br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
+  %tmp.21 = icmp eq i32 %tmp.2.i, 18              ; <i1> [#uses=1]
+  br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
 shortcirc_next.4:               ; preds = %shortcirc_next.3
-        %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
-        br label %UnifiedReturnBlock
+  %tmp.26 = icmp eq i32 %tmp.2.i, 19              ; <i1> [#uses=1]
+  br label %UnifiedReturnBlock
 shortcirc_done.4:               ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
-        br label %UnifiedReturnBlock
+  br label %UnifiedReturnBlock
 UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
-        %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
-        ret i1 %UnifiedRetVal
+  %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
+  ret i1 %UnifiedRetVal
 
-; CHECK-LABEL: @test6(
-; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
-; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret void
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
@@ -200,17 +273,27 @@
 if.end:                                           ; preds = %entry
   ret void
 
-; CHECK-LABEL: @test7(
-; CHECK:   %cmp = icmp ult i32 %x, 32
-; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
+; CHECK:       N:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
+; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i8 99, label [[IF_THEN]]
+; CHECK-NEXT:    i8 97, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    tail call void @foo1() #2
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 0
+;
 entry:
   br i1 %C, label %N, label %if.then
 N:
@@ -229,17 +312,33 @@
 if.end:                                           ; preds = %entry
   ret i32 0
 
-; CHECK-LABEL: @test8(
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
-; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
 ;; This is "Example 7" from http://blog.regehr.org/archives/320
 define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
+; CHECK-NEXT:    br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i8 [[C]], label [[LOR_RHS:%.*]] [
+; CHECK-NEXT:    i8 92, label [[LOR_END]]
+; CHECK-NEXT:    i8 62, label [[LOR_END]]
+; CHECK-NEXT:    i8 60, label [[LOR_END]]
+; CHECK-NEXT:    i8 59, label [[LOR_END]]
+; CHECK-NEXT:    i8 58, label [[LOR_END]]
+; CHECK-NEXT:    i8 46, label [[LOR_END]]
+; CHECK-NEXT:    i8 44, label [[LOR_END]]
+; CHECK-NEXT:    i8 34, label [[LOR_END]]
+; CHECK-NEXT:    i8 39, label [[LOR_END]]
+; CHECK-NEXT:    ]
+; CHECK:       lor.rhs:
+; CHECK-NEXT:    br label [[LOR_END]]
+; CHECK:       lor.end:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[SWITCH_EARLY_TEST]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY:%.*]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ], [ true, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    [[CONV46:%.*]] = zext i1 [[TMP0]] to i32
+; CHECK-NEXT:    ret i32 [[CONV46]]
+;
 entry:
   %cmp = icmp ult i8 %c, 33
   br i1 %cmp, label %lor.end, label %lor.lhs.false
@@ -285,25 +384,23 @@
   %conv46 = zext i1 %0 to i32
   ret i32 %conv46
 
-; CHECK-LABEL: @test9(
-; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
-
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
+; CHECK:       switch.early.test:
+; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
+; CHECK-NEXT:    i32 51, label [[F]]
+; CHECK-NEXT:    i32 0, label [[F]]
+; CHECK-NEXT:    ]
+; CHECK:       T:
+; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 123, [[SWITCH_EARLY_TEST]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK:       F:
+; CHECK-NEXT:    br label [[T]]
+;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
@@ -314,17 +411,27 @@
 F:
   ret i32 324
 
-; CHECK-LABEL: @test10(
-; CHECK:  br i1 %Cond, label %switch.early.test, label %F
-; CHECK:switch.early.test:
-; CHECK:  switch i32 %mode, label %T [
-; CHECK:    i32 51, label %F
-; CHECK:    i32 0, label %F
-; CHECK:  ]
 }
 
 ; PR8780
 define i32 @test11(i32 %bar) nounwind {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[BAR:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 55, label [[RETURN:%.*]]
+; CHECK-NEXT:    i32 53, label [[RETURN]]
+; CHECK-NEXT:    i32 35, label [[RETURN]]
+; CHECK-NEXT:    i32 24, label [[RETURN]]
+; CHECK-NEXT:    i32 23, label [[RETURN]]
+; CHECK-NEXT:    i32 12, label [[RETURN]]
+; CHECK-NEXT:    i32 4, label [[RETURN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.end:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_END]] ], [ 1, [[ENTRY:%.*]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ], [ 1, [[ENTRY]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_0]]
+;
 entry:
   %cmp = icmp eq i32 %bar, 4
   %cmp2 = icmp eq i32 %bar, 35
@@ -353,19 +460,21 @@
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
   ret i32 %retval.0
 
-; CHECK-LABEL: @test11(
-; CHECK: switch i32 %bar, label %if.end [
-; CHECK:   i32 55, label %return
-; CHECK:   i32 53, label %return
-; CHECK:   i32 35, label %return
-; CHECK:   i32 24, label %return
-; CHECK:   i32 23, label %return
-; CHECK:   i32 12, label %return
-; CHECK:   i32 4, label %return
-; CHECK: ]
 }
 
 define void @test12() nounwind {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_OLD:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    br i1 [[A_OLD]], label [[BB55_US_US:%.*]], label [[MALFORMED:%.*]]
+; CHECK:       bb55.us.us:
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i32 undef, undef
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i32 undef, undef
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[B]], [[A]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB55_US_US]], label [[MALFORMED]]
+; CHECK:       malformed:
+; CHECK-NEXT:    ret void
+;
 entry:
   br label %bb49.us.us
 
@@ -382,12 +491,26 @@
 
 malformed:
   ret void
-; CHECK-LABEL: @test12(
 
 }
 
 ; test13 - handle switch formation with ult.
 define void @test13(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ult i32 %x, 2
   br i1 %cmp, label %if.then, label %lor.lhs.false3
@@ -410,18 +533,26 @@
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test13(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; test14 - handle switch formation with ult.
 define void @test14(i32 %x) nounwind ssp noredzone {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 6, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 4, label [[IF_THEN]]
+; CHECK-NEXT:    i32 3, label [[IF_THEN]]
+; CHECK-NEXT:    i32 2, label [[IF_THEN]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN]]
+; CHECK-NEXT:    i32 0, label [[IF_THEN]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    call void @foo1() #3
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
 entry:
   %cmp = icmp ugt i32 %x, 2
   br i1 %cmp, label %lor.lhs.false3, label %if.then
@@ -444,18 +575,15 @@
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK-LABEL: @test14(
-; CHECK:  switch i32 %x, label %if.end [
-; CHECK:     i32 6, label %if.then
-; CHECK:     i32 4, label %if.then
-; CHECK:     i32 3, label %if.then
-; CHECK:     i32 1, label %if.then
-; CHECK:     i32 0, label %if.then
-; CHECK:   ]
 }
 
 ; Don't crash on ginormous ranges.
 define void @test15(i128 %x) nounwind {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:  if.end:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i128 [[X:%.*]], 2
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ugt i128 %x, 2
   br i1 %cmp, label %if.end, label %lor.false
 
@@ -470,18 +598,19 @@
 if.end:
   ret void
 
-; CHECK-LABEL: @test15(
-; CHECK-NOT: switch
-; CHECK: ret void
 }
 
 ; PR8675
 ; rdar://5134905
 define zeroext i1 @test16(i32 %x) nounwind {
-entry:
 ; CHECK-LABEL: @test16(
-; CHECK: %x.off = add i32 %x, -1
-; CHECK: %switch = icmp ult i32 %x.off, 3
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i1 true, i1 false
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
+entry:
   %cmp.i = icmp eq i32 %x, 1
   br i1 %cmp.i, label %lor.end, label %lor.lhs.false
 
@@ -500,6 +629,17 @@
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
+; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK:       lor.lhs.false8:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
@@ -512,13 +652,20 @@
 return:
   ret void
 
-; CHECK-LABEL: @test17(
-; CHECK-NOT: switch.early.test
-; CHECK-NOT: switch i32
-; CHECK: ret void
 }
 
 define void @test18(i32 %arg) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG:%.*]], -8
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG_OFF]], 11
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB19:%.*]], label [[BB20:%.*]]
+; CHECK:       bb19:
+; CHECK-NEXT:    tail call void @foo1()
+; CHECK-NEXT:    br label [[BB20]]
+; CHECK:       bb20:
+; CHECK-NEXT:    ret void
+;
 bb:
   %tmp = and i32 %arg, -2
   %tmp1 = icmp eq i32 %tmp, 8
@@ -550,12 +697,23 @@
 bb20:                                             ; preds = %bb19, %bb8
   ret void
 
-; CHECK-LABEL: @test18(
-; CHECK: %arg.off = add i32 %arg, -8
-; CHECK: icmp ult i32 %arg.off, 11
 }
 
 define void @PR26323(i1 %tobool23, i32 %tmp3) {
+; CHECK-LABEL: @PR26323(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TOBOOL5:%.*]] = icmp ne i32 [[TMP3:%.*]], 0
+; CHECK-NEXT:    [[NEG14:%.*]] = and i32 [[TMP3]], -2
+; CHECK-NEXT:    [[CMP17:%.*]] = icmp ne i32 [[NEG14]], -1
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[TOBOOL5]], [[TOBOOL23:%.*]]
+; CHECK-NEXT:    [[OR_COND1:%.*]] = and i1 [[CMP17]], [[OR_COND]]
+; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END29:%.*]], label [[IF_THEN27:%.*]]
+; CHECK:       if.then27:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    unreachable
+; CHECK:       if.end29:
+; CHECK-NEXT:    ret void
+;
 entry:
   %tobool5 = icmp ne i32 %tmp3, 0
   %neg14 = and i32 %tmp3, -2
@@ -587,6 +745,18 @@
 ; CHECK: i32 13, label %if
 ; CHECK: i32 12, label %if
 define void @test19(i32 %arg) {
+; CHECK-LABEL: @test19(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    i32 32, label [[IF:%.*]]
+; CHECK-NEXT:    i32 13, label [[IF]]
+; CHECK-NEXT:    i32 12, label [[IF]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
@@ -606,6 +776,18 @@
 ; CHECK-NOT: switch
 ; CHECK: ret void
 define void @test20(i32 %arg) {
+; CHECK-LABEL: @test20(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
@@ -626,6 +808,18 @@
 ; CHECK: i32 13, label %else
 ; CHECK: i32 12, label %else
 define void @test21(i32 %arg) {
+; CHECK-LABEL: @test21(
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
+; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
+; CHECK-NEXT:    i32 13, label [[ELSE]]
+; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    ]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
@@ -645,6 +839,18 @@
 ; CHECK-NOT: switch
 ; CHECK: ret void
 define void @test22(i32 %arg) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
+; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    call void @foo1()
+; CHECK-NEXT:    ret void
+; CHECK:       else:
+; CHECK-NEXT:    ret void
+;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
@@ -657,4 +863,4 @@
 
 else:
   ret void
-}
\ No newline at end of file
+}