Index: lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- lib/Target/AMDGPU/SOPInstructions.td +++ lib/Target/AMDGPU/SOPInstructions.td @@ -246,8 +246,10 @@ def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">; } // End Uses = [M0] +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in { def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">; def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">; +} // End SubtargetPredicate = isGFX6GFX7GFX8GFX9 let Defs = [SCC] in { def S_ABS_I32 : SOP1_32 <"s_abs_i32">; @@ -272,6 +274,12 @@ def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32">; } // End SubtargetPredicate = isGFX9Plus +let SubtargetPredicate = isGFX10Plus in { + let Uses = [M0] in { + def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">; + } // End Uses = [M0] +} // End SubtargetPredicate = isGFX10Plus + //===----------------------------------------------------------------------===// // SOP2 Instructions //===----------------------------------------------------------------------===// @@ -520,6 +528,7 @@ "$src0, $src1" > { let has_sdst = 0; + let SubtargetPredicate = isGFX6GFX7GFX8GFX9; } let Defs = [SCC] in { @@ -629,6 +638,19 @@ "$sdst, $simm16", pattern>; +class SOPK_32_BR pattern=[]> : SOPK_Pseudo < + opName, + (outs), + (ins sopp_brtarget:$simm16, SReg_32:$sdst), + "$sdst, $simm16", + pattern> { + let Defs = [EXEC]; + let Uses = [EXEC]; + let isBranch = 1; + let isTerminator = 1; + let SchedRW = [WriteBranch]; +} + class SOPK_SCC : SOPK_Pseudo < opName, (outs), @@ -695,6 +717,7 @@ def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">; } +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in def S_CBRANCH_I_FORK : SOPK_Pseudo < "s_cbranch_i_fork", (outs), (ins SReg_64:$sdst, s16imm:$simm16), @@ -731,6 +754,19 @@ } // End hasSideEffects = 1 +class SOPK_WAITCNT pat=[]> : + SOPK_Pseudo< + opName, + (outs), + (ins SReg_32:$sdst, s16imm:$simm16), + "$sdst, $simm16", + pat> { + let hasSideEffects = 1; + let mayLoad = 1; + let mayStore = 1; + let has_sdst = 1; // First source takes place of sdst in encoding +} + let SubtargetPredicate = isGFX9Plus in { def S_CALL_B64 : SOPK_Pseudo< "s_call_b64", @@ -741,6 +777,21 @@ } } // End SubtargetPredicate = isGFX9Plus +let SubtargetPredicate = isGFX10Plus in { + def S_VERSION : SOPK_Pseudo< + "s_version", + (outs), + (ins s16imm:$simm16), + "$simm16"> { + let has_sdst = 0; + } + + def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">; + def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">; + def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">; + def S_WAITCNT_LGKMCNT : SOPK_WAITCNT<"s_waitcnt_lgkmcnt">; +} // End SubtargetPredicate = isGFX10Plus + //===----------------------------------------------------------------------===// // SOPC Instructions //===----------------------------------------------------------------------===// @@ -821,6 +872,7 @@ def S_BITCMP1_B32 : SOPC_32 <0x0d, "s_bitcmp1_b32">; def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">; def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">; +let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">; let SubtargetPredicate = isGFX8Plus in { @@ -890,6 +942,13 @@ } // End isBarrier = 1, isReturn = 1, simm16 = 0 } // End SubtargetPredicate = isGFX9Plus +let SubtargetPredicate = isGFX10Plus in { + let isBarrier = 1, isReturn = 1, simm16 = 0 in { + def S_CODE_END : + SOPP<0x01f, (ins), "s_code_end">; + } // End isBarrier = 1, isReturn = 1, simm16 = 0 +} // End SubtargetPredicate = isGFX10Plus + let isBranch = 1, SchedRW = [WriteBranch] in { def S_BRANCH : SOPP < 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", @@ -1033,6 +1092,25 @@ } } +let SubtargetPredicate = isGFX10Plus in { + def S_INST_PREFETCH : + SOPP<0x020, (ins s16imm:$simm16), "s_inst_prefetch $simm16">; + def S_CLAUSE : + SOPP<0x021, (ins s16imm:$simm16), "s_clause $simm16">; + def S_WAITCNT_IDLE : + SOPP <0x022, (ins), "s_wait_idle"> { + let simm16 = 0; + } + def S_WAITCNT_DEPCTR : + SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">; + def S_ROUND_MODE : + SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">; + def S_DENORM_MODE : + SOPP<0x025, (ins s16imm:$simm16), "s_denorm_mode $simm16">; + def S_TTRACEDATA_IMM : + SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">; +} // End SubtargetPredicate = isGFX10Plus + //===----------------------------------------------------------------------===// // S_GETREG_B32 Intrinsic Pattern. //===----------------------------------------------------------------------===// @@ -1122,142 +1200,238 @@ // Target-specific instruction encodings. //===----------------------------------------------------------------------===// -class Select_si : - SIMCInstr { - list AssemblerPredicates = [isGFX6GFX7]; - string DecoderNamespace = "GFX6GFX7"; +//===----------------------------------------------------------------------===// +// SOP1 - GFX10. +//===----------------------------------------------------------------------===// + +class Select_gfx10 : SIMCInstr { + Predicate AssemblerPredicate = isGFX10Plus; + string DecoderNamespace = "GFX10"; } -class SOP1_Real_si op, SOP1_Pseudo ps> : - SOP1_Real, - Select_si; +multiclass SOP1_Real_gfx10 op> { + def _gfx10 : SOP1_Real(NAME)>, + Select_gfx10(NAME).Mnemonic>; +} -class SOP2_Real_si op, SOP2_Pseudo ps> : - SOP2_Real, - Select_si; +defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>; +defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>; +defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>; +defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>; +defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>; +defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>; -class SOPK_Real_si op, SOPK_Pseudo ps> : - SOPK_Real32, - Select_si; - -def S_MOV_B32_si : SOP1_Real_si <0x03, S_MOV_B32>; -def S_MOV_B64_si : SOP1_Real_si <0x04, S_MOV_B64>; -def S_CMOV_B32_si : SOP1_Real_si <0x05, S_CMOV_B32>; -def S_CMOV_B64_si : SOP1_Real_si <0x06, S_CMOV_B64>; -def S_NOT_B32_si : SOP1_Real_si <0x07, S_NOT_B32>; -def S_NOT_B64_si : SOP1_Real_si <0x08, S_NOT_B64>; -def S_WQM_B32_si : SOP1_Real_si <0x09, S_WQM_B32>; -def S_WQM_B64_si : SOP1_Real_si <0x0a, S_WQM_B64>; -def S_BREV_B32_si : SOP1_Real_si <0x0b, S_BREV_B32>; -def S_BREV_B64_si : SOP1_Real_si <0x0c, S_BREV_B64>; -def S_BCNT0_I32_B32_si : SOP1_Real_si <0x0d, S_BCNT0_I32_B32>; -def S_BCNT0_I32_B64_si : SOP1_Real_si <0x0e, S_BCNT0_I32_B64>; -def S_BCNT1_I32_B32_si : SOP1_Real_si <0x0f, S_BCNT1_I32_B32>; -def S_BCNT1_I32_B64_si : SOP1_Real_si <0x10, S_BCNT1_I32_B64>; -def S_FF0_I32_B32_si : SOP1_Real_si <0x11, S_FF0_I32_B32>; -def S_FF0_I32_B64_si : SOP1_Real_si <0x12, S_FF0_I32_B64>; -def S_FF1_I32_B32_si : SOP1_Real_si <0x13, S_FF1_I32_B32>; -def S_FF1_I32_B64_si : SOP1_Real_si <0x14, S_FF1_I32_B64>; -def S_FLBIT_I32_B32_si : SOP1_Real_si <0x15, S_FLBIT_I32_B32>; -def S_FLBIT_I32_B64_si : SOP1_Real_si <0x16, S_FLBIT_I32_B64>; -def S_FLBIT_I32_si : SOP1_Real_si <0x17, S_FLBIT_I32>; -def S_FLBIT_I32_I64_si : SOP1_Real_si <0x18, S_FLBIT_I32_I64>; -def S_SEXT_I32_I8_si : SOP1_Real_si <0x19, S_SEXT_I32_I8>; -def S_SEXT_I32_I16_si : SOP1_Real_si <0x1a, S_SEXT_I32_I16>; -def S_BITSET0_B32_si : SOP1_Real_si <0x1b, S_BITSET0_B32>; -def S_BITSET0_B64_si : SOP1_Real_si <0x1c, S_BITSET0_B64>; -def S_BITSET1_B32_si : SOP1_Real_si <0x1d, S_BITSET1_B32>; -def S_BITSET1_B64_si : SOP1_Real_si <0x1e, S_BITSET1_B64>; -def S_GETPC_B64_si : SOP1_Real_si <0x1f, S_GETPC_B64>; -def S_SETPC_B64_si : SOP1_Real_si <0x20, S_SETPC_B64>; -def S_SWAPPC_B64_si : SOP1_Real_si <0x21, S_SWAPPC_B64>; -def S_RFE_B64_si : SOP1_Real_si <0x22, S_RFE_B64>; -def S_AND_SAVEEXEC_B64_si : SOP1_Real_si <0x24, S_AND_SAVEEXEC_B64>; -def S_OR_SAVEEXEC_B64_si : SOP1_Real_si <0x25, S_OR_SAVEEXEC_B64>; -def S_XOR_SAVEEXEC_B64_si : SOP1_Real_si <0x26, S_XOR_SAVEEXEC_B64>; -def S_ANDN2_SAVEEXEC_B64_si: SOP1_Real_si <0x27, S_ANDN2_SAVEEXEC_B64>; -def S_ORN2_SAVEEXEC_B64_si : SOP1_Real_si <0x28, S_ORN2_SAVEEXEC_B64>; -def S_NAND_SAVEEXEC_B64_si : SOP1_Real_si <0x29, S_NAND_SAVEEXEC_B64>; -def S_NOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2a, S_NOR_SAVEEXEC_B64>; -def S_XNOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2b, S_XNOR_SAVEEXEC_B64>; -def S_QUADMASK_B32_si : SOP1_Real_si <0x2c, S_QUADMASK_B32>; -def S_QUADMASK_B64_si : SOP1_Real_si <0x2d, S_QUADMASK_B64>; -def S_MOVRELS_B32_si : SOP1_Real_si <0x2e, S_MOVRELS_B32>; -def S_MOVRELS_B64_si : SOP1_Real_si <0x2f, S_MOVRELS_B64>; -def S_MOVRELD_B32_si : SOP1_Real_si <0x30, S_MOVRELD_B32>; -def S_MOVRELD_B64_si : SOP1_Real_si <0x31, S_MOVRELD_B64>; -def S_CBRANCH_JOIN_si : SOP1_Real_si <0x32, S_CBRANCH_JOIN>; -def S_MOV_REGRD_B32_si : SOP1_Real_si <0x33, S_MOV_REGRD_B32>; -def S_ABS_I32_si : SOP1_Real_si <0x34, S_ABS_I32>; -def S_MOV_FED_B32_si : SOP1_Real_si <0x35, S_MOV_FED_B32>; - -def S_ADD_U32_si : SOP2_Real_si <0x00, S_ADD_U32>; -def S_ADD_I32_si : SOP2_Real_si <0x02, S_ADD_I32>; -def S_SUB_U32_si : SOP2_Real_si <0x01, S_SUB_U32>; -def S_SUB_I32_si : SOP2_Real_si <0x03, S_SUB_I32>; -def S_ADDC_U32_si : SOP2_Real_si <0x04, S_ADDC_U32>; -def S_SUBB_U32_si : SOP2_Real_si <0x05, S_SUBB_U32>; -def S_MIN_I32_si : SOP2_Real_si <0x06, S_MIN_I32>; -def S_MIN_U32_si : SOP2_Real_si <0x07, S_MIN_U32>; -def S_MAX_I32_si : SOP2_Real_si <0x08, S_MAX_I32>; -def S_MAX_U32_si : SOP2_Real_si <0x09, S_MAX_U32>; -def S_CSELECT_B32_si : SOP2_Real_si <0x0a, S_CSELECT_B32>; -def S_CSELECT_B64_si : SOP2_Real_si <0x0b, S_CSELECT_B64>; -def S_AND_B32_si : SOP2_Real_si <0x0e, S_AND_B32>; -def S_AND_B64_si : SOP2_Real_si <0x0f, S_AND_B64>; -def S_OR_B32_si : SOP2_Real_si <0x10, S_OR_B32>; -def S_OR_B64_si : SOP2_Real_si <0x11, S_OR_B64>; -def S_XOR_B32_si : SOP2_Real_si <0x12, S_XOR_B32>; -def S_XOR_B64_si : SOP2_Real_si <0x13, S_XOR_B64>; -def S_ANDN2_B32_si : SOP2_Real_si <0x14, S_ANDN2_B32>; -def S_ANDN2_B64_si : SOP2_Real_si <0x15, S_ANDN2_B64>; -def S_ORN2_B32_si : SOP2_Real_si <0x16, S_ORN2_B32>; -def S_ORN2_B64_si : SOP2_Real_si <0x17, S_ORN2_B64>; -def S_NAND_B32_si : SOP2_Real_si <0x18, S_NAND_B32>; -def S_NAND_B64_si : SOP2_Real_si <0x19, S_NAND_B64>; -def S_NOR_B32_si : SOP2_Real_si <0x1a, S_NOR_B32>; -def S_NOR_B64_si : SOP2_Real_si <0x1b, S_NOR_B64>; -def S_XNOR_B32_si : SOP2_Real_si <0x1c, S_XNOR_B32>; -def S_XNOR_B64_si : SOP2_Real_si <0x1d, S_XNOR_B64>; -def S_LSHL_B32_si : SOP2_Real_si <0x1e, S_LSHL_B32>; -def S_LSHL_B64_si : SOP2_Real_si <0x1f, S_LSHL_B64>; -def S_LSHR_B32_si : SOP2_Real_si <0x20, S_LSHR_B32>; -def S_LSHR_B64_si : SOP2_Real_si <0x21, S_LSHR_B64>; -def S_ASHR_I32_si : SOP2_Real_si <0x22, S_ASHR_I32>; -def S_ASHR_I64_si : SOP2_Real_si <0x23, S_ASHR_I64>; -def S_BFM_B32_si : SOP2_Real_si <0x24, S_BFM_B32>; -def S_BFM_B64_si : SOP2_Real_si <0x25, S_BFM_B64>; -def S_MUL_I32_si : SOP2_Real_si <0x26, S_MUL_I32>; -def S_BFE_U32_si : SOP2_Real_si <0x27, S_BFE_U32>; -def S_BFE_I32_si : SOP2_Real_si <0x28, S_BFE_I32>; -def S_BFE_U64_si : SOP2_Real_si <0x29, S_BFE_U64>; -def S_BFE_I64_si : SOP2_Real_si <0x2a, S_BFE_I64>; -def S_CBRANCH_G_FORK_si : SOP2_Real_si <0x2b, S_CBRANCH_G_FORK>; -def S_ABSDIFF_I32_si : SOP2_Real_si <0x2c, S_ABSDIFF_I32>; - -def S_MOVK_I32_si : SOPK_Real_si <0x00, S_MOVK_I32>; -def S_CMOVK_I32_si : SOPK_Real_si <0x02, S_CMOVK_I32>; -def S_CMPK_EQ_I32_si : SOPK_Real_si <0x03, S_CMPK_EQ_I32>; -def S_CMPK_LG_I32_si : SOPK_Real_si <0x04, S_CMPK_LG_I32>; -def S_CMPK_GT_I32_si : SOPK_Real_si <0x05, S_CMPK_GT_I32>; -def S_CMPK_GE_I32_si : SOPK_Real_si <0x06, S_CMPK_GE_I32>; -def S_CMPK_LT_I32_si : SOPK_Real_si <0x07, S_CMPK_LT_I32>; -def S_CMPK_LE_I32_si : SOPK_Real_si <0x08, S_CMPK_LE_I32>; -def S_CMPK_EQ_U32_si : SOPK_Real_si <0x09, S_CMPK_EQ_U32>; -def S_CMPK_LG_U32_si : SOPK_Real_si <0x0a, S_CMPK_LG_U32>; -def S_CMPK_GT_U32_si : SOPK_Real_si <0x0b, S_CMPK_GT_U32>; -def S_CMPK_GE_U32_si : SOPK_Real_si <0x0c, S_CMPK_GE_U32>; -def S_CMPK_LT_U32_si : SOPK_Real_si <0x0d, S_CMPK_LT_U32>; -def S_CMPK_LE_U32_si : SOPK_Real_si <0x0e, S_CMPK_LE_U32>; -def S_ADDK_I32_si : SOPK_Real_si <0x0f, S_ADDK_I32>; -def S_MULK_I32_si : SOPK_Real_si <0x10, S_MULK_I32>; -def S_CBRANCH_I_FORK_si : SOPK_Real_si <0x11, S_CBRANCH_I_FORK>; -def S_GETREG_B32_si : SOPK_Real_si <0x12, S_GETREG_B32>; -def S_SETREG_B32_si : SOPK_Real_si <0x13, S_SETREG_B32>; -//def S_GETREG_REGRD_B32_si : SOPK_Real_si <0x14, S_GETREG_REGRD_B32>; // see pseudo for comments -def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>, - Select_si; +//===----------------------------------------------------------------------===// +// SOP1 - GFX6, GFX7. +//===----------------------------------------------------------------------===// + +class Select_gfx6_gfx7 : SIMCInstr { + Predicate AssemblerPredicate = isGFX6GFX7; + string DecoderNamespace = "GFX6GFX7"; +} + +multiclass SOP1_Real_gfx6_gfx7 op> { + def _gfx6_gfx7 : SOP1_Real(NAME)>, + Select_gfx6_gfx7(NAME).Mnemonic>; +} + +multiclass SOP1_Real_gfx6_gfx7_gfx10 op> : + SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10; + +defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>; +defm S_MOV_REGRD_B32 : SOP1_Real_gfx6_gfx7<0x033>; + +defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>; +defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>; +defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>; +defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>; +defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>; +defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>; +defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>; +defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>; +defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>; +defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>; +defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>; +defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>; +defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>; +defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>; +defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>; +defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>; +defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>; +defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>; +defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>; +defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>; +defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>; +defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>; +defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>; +defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>; +defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>; +defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>; +defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>; +defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>; +defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>; +defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>; +defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>; +defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>; +defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>; +defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>; +defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>; +defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>; +defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>; +defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>; +defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>; +defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02b>; +defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>; +defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>; +defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>; +defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>; +defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>; +defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>; +defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; +defm S_MOV_FED_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x035>; + +//===----------------------------------------------------------------------===// +// SOP2 - GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOP2_Real_gfx10 op> { + def _gfx10 : SOP2_Real(NAME)>, + Select_gfx10(NAME).Mnemonic>; +} + +defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>; +defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>; +defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>; +defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>; +defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10<0x032>; +defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10<0x033>; +defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10<0x034>; +defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>; +defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; + +//===----------------------------------------------------------------------===// +// SOP2 - GFX6, GFX7. +//===----------------------------------------------------------------------===// + +multiclass SOP2_Real_gfx6_gfx7 op> { + def _gfx6_gfx7 : SOP2_Real(NAME)>, + Select_gfx6_gfx7(NAME).Mnemonic>; +} + +multiclass SOP2_Real_gfx6_gfx7_gfx10 op> : + SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10; + +defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>; + +defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x000>; +defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x001>; +defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x002>; +defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x003>; +defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x004>; +defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x005>; +defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>; +defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>; +defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>; +defm S_MAX_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x009>; +defm S_CSELECT_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00a>; +defm S_CSELECT_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00b>; +defm S_AND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00e>; +defm S_AND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00f>; +defm S_OR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x010>; +defm S_OR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x011>; +defm S_XOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x012>; +defm S_XOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x013>; +defm S_ANDN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x014>; +defm S_ANDN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x015>; +defm S_ORN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x016>; +defm S_ORN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x017>; +defm S_NAND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x018>; +defm S_NAND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x019>; +defm S_NOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01a>; +defm S_NOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01b>; +defm S_XNOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01c>; +defm S_XNOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01d>; +defm S_LSHL_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01e>; +defm S_LSHL_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01f>; +defm S_LSHR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x020>; +defm S_LSHR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x021>; +defm S_ASHR_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x022>; +defm S_ASHR_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x023>; +defm S_BFM_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x024>; +defm S_BFM_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x025>; +defm S_MUL_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x026>; +defm S_BFE_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x027>; +defm S_BFE_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x028>; +defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10<0x029>; +defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>; +defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx10 op> { + def _gfx10 : SOPK_Real32(NAME)>, + Select_gfx10(NAME).Mnemonic>; +} + +multiclass SOPK_Real64_gfx10 op> { + def _gfx10 : SOPK_Real64(NAME)>, + Select_gfx10(NAME).Mnemonic>; +} + +defm S_VERSION : SOPK_Real32_gfx10<0x001>; +defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>; +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX6, GFX7. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx6_gfx7 op> { + def _gfx6_gfx7 : SOPK_Real32(NAME)>, + Select_gfx6_gfx7(NAME).Mnemonic>; +} + +multiclass SOPK_Real64_gfx6_gfx7 op> { + def _gfx6_gfx7 : SOPK_Real64(NAME)>, + Select_gfx6_gfx7(NAME).Mnemonic>; +} + +multiclass SOPK_Real32_gfx6_gfx7_gfx10 op> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10; + +multiclass SOPK_Real64_gfx6_gfx7_gfx10 op> : + SOPK_Real64_gfx6_gfx7, SOPK_Real64_gfx10; + +defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; + +defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x000>; +defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x002>; +defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x003>; +defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x004>; +defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x005>; +defm S_CMPK_GE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x006>; +defm S_CMPK_LT_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x007>; +defm S_CMPK_LE_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x008>; +defm S_CMPK_EQ_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x009>; +defm S_CMPK_LG_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00a>; +defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00b>; +defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00c>; +defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00d>; +defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00e>; +defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x00f>; +defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10<0x010>; +defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>; +defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>; +defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; +//===----------------------------------------------------------------------===// +// GFX8, GFX9 (VI). +//===----------------------------------------------------------------------===// class Select_vi : SIMCInstr { Index: test/MC/AMDGPU/out-of-range-registers.s =================================================================== --- test/MC/AMDGPU/out-of-range-registers.s +++ test/MC/AMDGPU/out-of-range-registers.s @@ -1,62 +1,111 @@ -// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s -// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,SI-ERR %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,CIVI9-ERR %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX9-ERR,SICIVI9-ERR,CIVI9-ERR %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX10-ERR %s + +// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SIVICI %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=SIVICI %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s + +s_add_i32 s106, s0, s1 +// GCN-ERR: error: not a valid operand s_add_i32 s104, s0, s1 -// CHECK: error: not a valid operand +// SICIVI9-ERR: error: not a valid operand +// GFX10: s_add_i32 s104, s0, s1 ; encoding: s_add_i32 s105, s0, s1 -// CHECK: error: not a valid operand +// SICIVI9-ERR: error: not a valid operand +// GFX10: s_add_i32 s105, s0, s1 ; encoding: v_add_i32 v256, v0, v1 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand v_add_i32 v257, v0, v1 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_mov_b64 s[0:17], -1 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_mov_b64 s[103:104], -1 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand + +s_mov_b64 s[105:106], -1 +// GCN-ERR: error: not a valid operand s_mov_b64 s[104:105], -1 -// CHECK: error: not a valid operand +// SICIVI9-ERR: error: not a valid operand +// GFX10: s_mov_b64 s[104:105], -1 ; encoding: s_load_dwordx4 s[102:105], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx4 s[104:108], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx4 s[108:112], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx4 s[1:4], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx4 s[1:4], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx8 s[104:111], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx8 s[100:107], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx8 s[108:115], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx16 s[92:107], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx16 s[96:111], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx16 s[100:115], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx16 s[104:119], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand s_load_dwordx16 s[108:123], s[2:3], s4 -// CHECK: error: not a valid operand +// GCN-ERR: error: not a valid operand + +s_mov_b32 ttmp16, 0 +// GCN-ERR: error: not a valid operand + +s_mov_b32 ttmp12, 0 +// SICIVI: error: not a valid operand +// GFX9: s_mov_b32 ttmp12, 0 ; encoding: +// GFX10: s_mov_b32 ttmp12, 0 ; encoding: + +s_mov_b32 ttmp15, 0 +// SICIVI: error: not a valid operand +// GFX9: s_mov_b32 ttmp15, 0 ; encoding: +// GFX10: s_mov_b32 ttmp15, 0 ; encoding: + +s_mov_b32 flat_scratch_lo, 0 +// SI-ERR: error: not a valid operand +// CIVI9: s_mov_b32 flat_scratch_lo, 0 ; encoding: +// GFX10-ERR: error: not a valid operand + +s_mov_b32 flat_scratch_hi, 0 +// SI-ERR: error: not a valid operand +// CIVI9: s_mov_b32 flat_scratch_hi, 0 ; encoding: +// GFX10-ERR: error: not a valid operand + +s_mov_b32 tma_lo, 0 +// SIVICI: s_mov_b32 tma_lo, 0 ; encoding: +// GFX9-ERR: error: not a valid operand +// GFX10-ERR: error: not a valid operand + +s_mov_b32 tba_lo, 0 +// SIVICI: s_mov_b32 tba_lo, 0 ; encoding: +// GFX9-ERR: error: not a valid operand +// GFX10-ERR: error: not a valid operand Index: test/MC/AMDGPU/sop1.s =================================================================== --- test/MC/AMDGPU/sop1.s +++ test/MC/AMDGPU/sop1.s @@ -6,6 +6,8 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI --check-prefix=NOSICIVI --check-prefix=NOGFX89 %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=NOGFX89 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding 2>&1 %s | FileCheck --check-prefix=GFX10-ERR %s + s_mov_b32 s1, s2 // SICI: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe] // GFX89: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe] @@ -238,6 +240,7 @@ s_cbranch_join s4 // SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe] // GFX89: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe] +// GFX10-ERR: error: instruction not supported on this GPU s_cbranch_join 1 // NOSICI: error: invalid operand for instruction Index: test/MC/AMDGPU/sop2.s =================================================================== --- test/MC/AMDGPU/sop2.s +++ test/MC/AMDGPU/sop2.s @@ -10,6 +10,8 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICIVI --check-prefix=NOVI --check-prefix=NOGFX89 %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck --check-prefix=NOGFX89 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding 2>&1 %s | FileCheck --check-prefix=GFX10-ERR %s + s_add_u32 s1, s2, s3 // GCN: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80] @@ -177,14 +179,17 @@ s_cbranch_g_fork s[4:5], s[6:7] // SICI: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95] // GFX89: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x94] +// GFX10-ERR: error: instruction not supported on this GPU s_cbranch_g_fork 1, s[6:7] // SICI: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x95] // GFX89: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x94] +// GFX10-ERR: error: instruction not supported on this GPU s_cbranch_g_fork s[6:7], 2 // SICI: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x95] // GFX89: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x94] +// GFX10-ERR: error: instruction not supported on this GPU s_absdiff_i32 s2, s4, s6 // SICI: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96] Index: test/MC/AMDGPU/sopc.s =================================================================== --- test/MC/AMDGPU/sopc.s +++ test/MC/AMDGPU/sopc.s @@ -1,6 +1,7 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSICI %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10-ERR %s //===----------------------------------------------------------------------===// // SOPC Instructions @@ -62,6 +63,7 @@ s_setvskip s3, s5 // GCN: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf] +// GFX10-ERR: error: instruction not supported on this GPU s_cmp_eq_u64 s[0:1], s[2:3] // VI: s_cmp_eq_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x12,0xbf] Index: test/MC/AMDGPU/sopk-err.s =================================================================== --- test/MC/AMDGPU/sopk-err.s +++ test/MC/AMDGPU/sopk-err.s @@ -1,7 +1,9 @@ // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI-ERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI-ERR %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GFX9-ERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s s_setreg_b32 0x1f803, s2 // GCN: error: invalid immediate: only 16-bit values are legal @@ -27,10 +29,62 @@ s_getreg_b32 s2, hwreg(3,32,32) // GCN: error: invalid bit offset: only 5-bit values are legal +s_cbranch_i_fork s[2:3], 0x6 +// GFX10: error: instruction not supported on this GPU + s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) // SI-ERR: error: invalid symbolic name of hardware register // VI-ERR: error: invalid symbolic name of hardware register -// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] +// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) +// SI-ERR: error: invalid symbolic name of hardware register +// VI-ERR: error: invalid symbolic name of hardware register +// GFX9-ERR: error: invalid symbolic name of hardware register +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9] s_cmpk_le_u32 s2, -1 // GCN: error: invalid operand for instruction Index: test/MC/AMDGPU/sopk.s =================================================================== --- test/MC/AMDGPU/sopk.s +++ test/MC/AMDGPU/sopk.s @@ -2,6 +2,7 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=VI %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI9 --check-prefix=GFX9 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=GFX10 %s // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI -check-prefix=NOSI %s @@ -117,9 +118,61 @@ // HW_REG_SH_MEM_BASES valid starting from GFX9 s_getreg_b32 s2, hwreg(15) -// SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9] -// VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8] -// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] +// SICI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x02,0xb9] +// VI: s_getreg_b32 s2, hwreg(15) ; encoding: [0x0f,0xf8,0x82,0xb8] +// GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9] + +// GFX10+ registers +s_getreg_b32 s2, hwreg(16) +// SICI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(17) +// SICI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(18) +// SICI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(19) +// SICI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(20) +// SICI: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(21) +// SICI: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(21) ; encoding: [0x15,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(22) +// SICI: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(22) ; encoding: [0x16,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(23) +// SICI: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(23) ; encoding: [0x17,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(24) +// SICI: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(24) ; encoding: [0x18,0xf8,0x02,0xb9] + +s_getreg_b32 s2, hwreg(25) +// SICI: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x02,0xb9] +// VI9: s_getreg_b32 s2, hwreg(25) ; encoding: [0x19,0xf8,0x82,0xb8] +// GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9] // raw number mapped to known HW register s_setreg_b32 0x6, s2 @@ -153,9 +206,61 @@ // HW_REG_SH_MEM_BASES valid starting from GFX9 s_setreg_b32 hwreg(15), s2 -// SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] -// VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] -// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] +// SICI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] +// VI: s_setreg_b32 hwreg(15), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] +// GFX9: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_SH_MEM_BASES), s2 ; encoding: [0x0f,0xf8,0x82,0xb9] + +// GFX10+ registers +s_setreg_b32 hwreg(16), s2 +// SICI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(17), s2 +// SICI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(18), s2 +// SICI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(19), s2 +// SICI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(20), s2 +// SICI: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(20), s2 ; encoding: [0x14,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; encoding: [0x14,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(21), s2 +// SICI: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(21), s2 ; encoding: [0x15,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s2 ; encoding: [0x15,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(22), s2 +// SICI: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(22), s2 ; encoding: [0x16,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s2 ; encoding: [0x16,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(23), s2 +// SICI: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(23), s2 ; encoding: [0x17,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(24), s2 +// SICI: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(24), s2 ; encoding: [0x18,0xf8,0x82,0xb9] + +s_setreg_b32 hwreg(25), s2 +// SICI: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x82,0xb9] +// VI9: s_setreg_b32 hwreg(25), s2 ; encoding: [0x19,0xf8,0x02,0xb9] +// GFX10: s_setreg_b32 hwreg(HW_REG_POPS_PACKER), s2 ; encoding: [0x19,0xf8,0x82,0xb9] // HW register code, non-default offset/width s_setreg_b32 hwreg(5, 1, 31), s2 Index: test/MC/AMDGPU/sopp.s =================================================================== --- test/MC/AMDGPU/sopp.s +++ test/MC/AMDGPU/sopp.s @@ -194,6 +194,9 @@ s_sendmsg 0x4 // GCN: s_sendmsg 4 ; encoding: [0x04,0x00,0x90,0xbf] +s_sendmsg 9 +// GCN: s_sendmsg 9 ; encoding: [0x09,0x00,0x90,0xbf] + s_sendmsg 11 // GCN: s_sendmsg 11 ; encoding: [0x0b,0x00,0x90,0xbf]