Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
===================================================================
--- lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
+++ lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h
@@ -16,6 +16,9 @@
 
 #include "llvm/MC/MCInst.h"
 
+#include <memory>
+
+extern "C" void LLVMInitializeHexagonTargetMC();
 namespace llvm {
 class MCInstrDesc;
 class MCOperand;
@@ -22,6 +25,7 @@
 class HexagonTargetMachine;
 
 class HexagonMCInst : public MCInst {
+  friend void ::LLVMInitializeHexagonTargetMC();
 public:
   explicit HexagonMCInst(unsigned op);
 
@@ -61,7 +65,8 @@
   int getMaxValue() const;
   bool packetBegin;
   bool packetEnd;
-  MCInstrDesc const &MCID;
+  MCInstrDesc const &getDesc() const;
+  static std::unique_ptr <MCInstrInfo const> MCII;
 };
 }
 
Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
===================================================================
--- lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
+++ lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
@@ -20,10 +20,15 @@
 
 using namespace llvm;
 
+std::unique_ptr <MCInstrInfo const> HexagonMCInst::MCII;
+
+MCInstrDesc const& HexagonMCInst::getDesc() const
+{
+  return (MCII->get(getOpcode()));
+}
+
 HexagonMCInst::HexagonMCInst(unsigned op)
-    : packetBegin(false), packetEnd(false),
-      MCID(llvm::TheHexagonTarget.createMCInstrInfo()->get(op)) {
-  assert(MCID.getSize() == 4 && "All instructions should be 32bit");
+    : packetBegin(false), packetEnd(false) {
   setOpcode(op);
 }
 
@@ -42,17 +47,17 @@
 }
 
 bool HexagonMCInst::isNewValue() const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
 }
 
 bool HexagonMCInst::hasNewValue() const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
 }
 
 MCOperand const &HexagonMCInst::getNewValue() const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   const unsigned O =
       (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
   const MCOperand &MCO = getOperand(O);
@@ -98,33 +103,33 @@
 }
 
 bool HexagonMCInst::isExtended(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
 }
 
 bool HexagonMCInst::isExtendable(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
 }
 
 unsigned HexagonMCInst::getBitCount(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
 }
 
 unsigned short HexagonMCInst::getCExtOpNum(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
 }
 
 bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
          OperandNum;
 }
 
 int HexagonMCInst::getMinValue(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   unsigned isSigned =
       (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
   unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
@@ -136,7 +141,7 @@
 }
 
 int HexagonMCInst::getMaxValue(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = getDesc().TSFlags;
   unsigned isSigned =
       (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
   unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
===================================================================
--- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -14,6 +14,7 @@
 #include "HexagonMCTargetDesc.h"
 #include "HexagonMCAsmInfo.h"
 #include "MCTargetDesc/HexagonInstPrinter.h"
+#include "MCTargetDesc/HexagonMCInst.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
@@ -95,6 +96,7 @@
   // Register the MC instruction info.
   TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
                                       createHexagonMCInstrInfo);
+  HexagonMCInst::MCII.reset (createHexagonMCInstrInfo());
 
   // Register the MC register info.
   TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,