Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -145,7 +145,7 @@ StringMap RegisterReqs; bool NextSymbolIsThumb; - +// SmallVector ReglistOperandRulesList; struct { ARMCC::CondCodes Cond; // Condition for IT block. unsigned Mask:4; // Condition mask for instructions. @@ -174,8 +174,11 @@ if (++ITState.CurPosition == 5 - TZ) ITState.CurPosition = ~0U; // Done with the IT block after this. } + bool lastInITBlock() { + unsigned TZ = countTrailingZeros(ITState.Mask); + return (ITState.CurPosition == 4 - TZ); + } - MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -323,6 +326,8 @@ bool processInstruction(MCInst &Inst, const OperandVector &Ops); bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); + bool validateRegListOperands(MCInst &Inst, const OperandVector &Operands, + unsigned OpNo); public: enum ARMMatchResultTy { @@ -5772,7 +5777,7 @@ return false; } -// Check if the specified regisgter is in the register list of the inst, +// Check if the specified register is in the register list of the inst, // starting at the indicated operand number. static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { @@ -5783,8 +5788,66 @@ return false; } +// Check if there are any special registers in the register list of the inst, +// starting at the indicated operand number. +static void findSpecialRegsInList(MCInst &Inst, unsigned OpNo, bool &SP, + bool &PC, bool &LR) { + SP = PC = LR = false; + for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { + unsigned OpReg = Inst.getOperand(i).getReg(); + if (OpReg == ARM::SP) + SP = true; + else if (OpReg == ARM::PC) + PC = true; + else if (OpReg == ARM::LR) + LR = true; + } + + return; +} + +bool ARMAsmParser::validateRegListOperands(MCInst &Inst, + const OperandVector &Operands, + unsigned OpNo) { + bool SP, PC, LR; + const unsigned Opcode = Inst.getOpcode(); + findSpecialRegsInList(Inst, OpNo, SP, PC, LR); + + switch (Opcode) { + case ARM::tLDMIA: + case ARM::t2LDMIA: + case ARM::t2LDMDB: + case ARM::t2LDMIA_UPD: + case ARM::t2LDMDB_UPD: + case ARM::tPOP: { + if (SP) + return Error(Operands[OpNo]->getStartLoc(), + "SP not allowed in register list"); + if (PC && LR) + return Error( + Operands[OpNo]->getStartLoc(), + "LR not allowed in the list, when PC is in the register list"); + if (PC && inITBlock() && !lastInITBlock()) + return Error(Operands[OpNo]->getStartLoc(), + "Instruction should be outside an IT block or last in IT " + "block, when PC is in the register list"); + } break; + case ARM::tSTMIA_UPD: + case ARM::t2STMIA: + case ARM::t2STMDB: + case ARM::t2STMIA_UPD: + case ARM::t2STMDB_UPD: + case ARM::tPUSH: { + if (SP || PC) + return Error(Operands[OpNo]->getStartLoc(), + "SP, PC not allowed in register list"); + } break; + } + return false; +} + // Return true if instruction has the interesting property of being -// allowed in IT blocks, but not being predicable. +// allowed in IT blocks, but not beOpNoing predicable. static bool instIsBreakpoint(const MCInst &Inst) { return Inst.getOpcode() == ARM::tBKPT || Inst.getOpcode() == ARM::BKPT || @@ -5976,9 +6039,7 @@ return Error(Operands[3]->getStartLoc(), "writeback operator '!' not allowed when base register " "in register list"); - if (listContainsReg(Inst, 3 + HasWritebackToken, ARM::SP)) - return Error(Operands[3 + HasWritebackToken]->getStartLoc(), - "SP not allowed in register list"); + validateRegListOperands(Inst, Operands, 3 + HasWritebackToken); break; } case ARM::LDMIA_UPD: @@ -5997,9 +6058,7 @@ case ARM::t2LDMDB: case ARM::t2STMIA: case ARM::t2STMDB: { - if (listContainsReg(Inst, 3, ARM::SP)) - return Error(Operands.back()->getStartLoc(), - "SP not allowed in register list"); + validateRegListOperands(Inst, Operands, 3); break; } case ARM::t2LDMIA_UPD: @@ -6009,12 +6068,9 @@ if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) return Error(Operands.back()->getStartLoc(), "writeback register not allowed in register list"); - - if (listContainsReg(Inst, 4, ARM::SP)) - return Error(Operands.back()->getStartLoc(), - "SP not allowed in register list"); - break; - } + validateRegListOperands(Inst, Operands, 4); + break; + } case ARM::sysLDMIA_UPD: case ARM::sysLDMDA_UPD: case ARM::sysLDMDB_UPD: @@ -6057,6 +6113,7 @@ !isThumbTwo()) return Error(Operands[2]->getStartLoc(), "registers must be in range r0-r7 or pc"); + validateRegListOperands(Inst, Operands, 2); break; } case ARM::tPUSH: { @@ -6065,6 +6122,7 @@ !isThumbTwo()) return Error(Operands[2]->getStartLoc(), "registers must be in range r0-r7 or lr"); + validateRegListOperands(Inst, Operands, 2); break; } case ARM::tSTMIA_UPD: { @@ -6081,11 +6139,9 @@ return Error(Operands[4]->getStartLoc(), "writeback operator '!' not allowed when base register " "in register list"); - if (listContainsReg(Inst, 4, ARM::SP) && !inITBlock()) - return Error(Operands.back()->getStartLoc(), - "SP not allowed in register list"); + validateRegListOperands(Inst, Operands, 4); break; - } + } case ARM::tADDrSP: { // If the non-SP source operand and the destination operand are not the // same, we need thumb2 (for the wide encoding), or we have an error. Index: test/MC/ARM/thumb-diagnostics.s =================================================================== --- test/MC/ARM/thumb-diagnostics.s +++ test/MC/ARM/thumb-diagnostics.s @@ -68,6 +68,7 @@ ldmfd r2!, {r1, r3-r6, sp} ldmdb r1, {r2, r3, sp} ldmdb r1!, {r2, r3, sp} + ldm r2, {r5, lr, pc} @ CHECK-ERRORS: error: registers must be in range r0-r7 @ CHECK-ERRORS: ldm r2!, {r5, r8} @ CHECK-ERRORS: ^ @@ -104,16 +105,31 @@ @ CHECK-ERRORS-V7M: error: SP not allowed in register list @ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: LR not allowed in the list, when PC is in the register list +@ CHECK-ERRORS-V7M: ldm r2, {r5, lr, pc} +@ CHECK-ERRORS-V7M: ^ @ Invalid writeback and register lists for PUSH/POP pop {r1, r2, r10} + pop {r1, r2, lr, pc} push {r8, r9} + push {r8, r9, sp} + push {r8, r9, pc} @ CHECK-ERRORS: error: registers must be in range r0-r7 or pc @ CHECK-ERRORS: pop {r1, r2, r10} @ CHECK-ERRORS: ^ +@ CHECK-ERRORS-V7M: error: LR not allowed in the list, when PC is in the register list +@ CHECK-ERRORS-V7M: pop {r1, r2, lr, pc} +@ CHECK-ERRORS-V7M: ^ @ CHECK-ERRORS: error: registers must be in range r0-r7 or lr @ CHECK-ERRORS: push {r8, r9} @ CHECK-ERRORS: ^ +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list +@ CHECK-ERRORS-V7M: push {r8, r9, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list +@ CHECK-ERRORS-V7M: push {r8, r9, pc} +@ CHECK-ERRORS-V7M: ^ @ Invalid writeback and register lists for STM @@ -125,6 +141,8 @@ stmia r4!, {r0-r3, sp} stmdb r1, {r2, r3, sp} stmdb r1!, {r2, r3, sp} + stmia r4, {r2, sp, pc} + stmdb r1!, {r2, r3, pc} @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: stm r1, {r2, r6} @ CHECK-ERRORS: ^ @@ -137,18 +155,24 @@ @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: stmdb r2!, {r0, r2} @ CHECK-ERRORS-V8: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list @ CHECK-ERRORS-V7M: stm r1!, {r2, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list @ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list @ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ -@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list @ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp} @ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list +@ CHECK-ERRORS-V7M: stmia r4, {r2, sp, pc} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP, PC not allowed in register list +@ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, pc} +@ CHECK-ERRORS-V7M: ^ @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 Index: test/MC/ARM/thumb2-diagnostics.s =================================================================== --- test/MC/ARM/thumb2-diagnostics.s +++ test/MC/ARM/thumb2-diagnostics.s @@ -9,6 +9,9 @@ iteeee gt ittfe le nopeq + ite eq + ldmiaeq sp!, {r4, pc} + movne r0, #0 @ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq' @ CHECK-ERRORS: addle r0, r1, r2 @@ -28,6 +31,9 @@ @ CHECK-ERRORS: error: predicated instructions must be in IT block @ CHECK-ERRORS: nopeq @ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: Instruction should be outside an IT block or last in IT block, when PC is in the register list +@ CHECK-ERRORS: ldmiaeq sp!, {r4, pc} +@ CHECK-ERRORS: ^ @ Out of range immediates for MRC/MRC2/MRRC/MRRC2 mrc p14, #8, r1, c1, c2, #4 Index: test/MC/ARM/v8_IT_manual.s =================================================================== --- test/MC/ARM/v8_IT_manual.s +++ test/MC/ARM/v8_IT_manual.s @@ -554,11 +554,11 @@ @ PUSH, encoding T2 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r1, r13, r7} +pushge {r1, r3, r7} @ PUSH, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r13} +pushge {r3} @ REV, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block @@ -614,9 +614,10 @@ @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge stmge r1, {r2, r3} +@ STM, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -stmge r1!, {r2, r13} +stmge r1!, {r2} @ LDM, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block