diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h @@ -437,15 +437,15 @@ unsigned Size = MRI.getType(MO.getReg()).getSizeInBits(); if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT && - MMO->getSize() * 8 != Size) { + MMO->getSizeInBits() != Size) { if (handleReject() == RejectAndGiveUp) return false; } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT && - MMO->getSize() * 8 >= Size) { + MMO->getSizeInBits() >= Size) { if (handleReject() == RejectAndGiveUp) return false; } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT && - MMO->getSize() * 8 <= Size) + MMO->getSizeInBits() <= Size) if (handleReject() == RejectAndGiveUp) return false; diff --git a/llvm/include/llvm/CodeGen/MachineMemOperand.h b/llvm/include/llvm/CodeGen/MachineMemOperand.h --- a/llvm/include/llvm/CodeGen/MachineMemOperand.h +++ b/llvm/include/llvm/CodeGen/MachineMemOperand.h @@ -220,6 +220,9 @@ /// Return the size in bytes of the memory reference. uint64_t getSize() const { return Size; } + /// Return the size in bits of the memory reference. + uint64_t getSizeInBits() const { return Size * 8; } + /// Return the minimum known alignment in bytes of the actual memory /// reference. uint64_t getAlignment() const; diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -603,7 +603,7 @@ unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy); auto &MMO = **MI.memoperands_begin(); - if (MMO.getSize() * 8 == NarrowSize) { + if (MMO.getSizeInBits() == NarrowSize) { MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); } else { unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD @@ -1496,7 +1496,7 @@ LLT DstTy = MRI.getType(DstReg); auto &MMO = **MI.memoperands_begin(); - if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) { + if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { if (MI.getOpcode() == TargetOpcode::G_LOAD) { // This load needs splitting into power of 2 sized loads. if (DstTy.isVector()) @@ -1551,8 +1551,8 @@ } if (DstTy.isScalar()) { - unsigned TmpReg = MRI.createGenericVirtualRegister( - LLT::scalar(MMO.getSize() /* in bytes */ * 8)); + unsigned TmpReg = + MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits())); MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); switch (MI.getOpcode()) { default: @@ -1584,7 +1584,7 @@ unsigned PtrReg = MI.getOperand(1).getReg(); LLT SrcTy = MRI.getType(SrcReg); MachineMemOperand &MMO = **MI.memoperands_begin(); - if (SrcTy.getSizeInBits() != MMO.getSize() /* in bytes */ * 8) + if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) return UnableToLegalize; if (SrcTy.isVector()) return UnableToLegalize; diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1022,13 +1022,13 @@ const MachineMemOperand &MMO = **MI->memoperands_begin(); if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD || MI->getOpcode() == TargetOpcode::G_SEXTLOAD) { - if (MMO.getSize() * 8 >= ValTy.getSizeInBits()) + if (MMO.getSizeInBits() >= ValTy.getSizeInBits()) report("Generic extload must have a narrower memory type", MI); } else if (MI->getOpcode() == TargetOpcode::G_LOAD) { - if (MMO.getSize() > (ValTy.getSizeInBits() + 7) / 8) + if (MMO.getSizeInBits() > (ValTy.getSizeInBits() + 7)) report("load memory size cannot exceed result size", MI); } else if (MI->getOpcode() == TargetOpcode::G_STORE) { - if ((ValTy.getSizeInBits() + 7) / 8 < MMO.getSize()) + if ((ValTy.getSizeInBits() + 7) < MMO.getSizeInBits()) report("store memory size cannot exceed value size", MI); } }