diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -770,6 +770,14 @@
 
 //===----------------------------------------------------------------------===//
 
+static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
+                             unsigned LabelId, MCContext &Ctx) {
+
+  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
+                       + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
+  return Label;
+}
+
 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
                              unsigned LabelId, MCContext &Ctx) {
 
@@ -1444,6 +1452,65 @@
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
+  case ARM::t2BFi:
+  case ARM::t2BFic:
+  case ARM::t2BFLi:
+  case ARM::t2BFr:
+  case ARM::t2BFLr: {
+    // This is a Branch Future instruction.
+
+    const MCExpr *BranchLabel = MCSymbolRefExpr::create(
+        getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
+                   MI->getOperand(0).getIndex(), OutContext),
+        OutContext);
+
+    auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
+    if (MI->getOperand(1).isReg()) {
+      // For BFr/BFLr
+      MCInst.addReg(MI->getOperand(1).getReg());
+    } else {
+      // For BFi/BFLi/BFic
+      const MCExpr *BranchTarget;
+      if (MI->getOperand(1).isMBB())
+        BranchTarget = MCSymbolRefExpr::create(
+            MI->getOperand(1).getMBB()->getSymbol(), OutContext);
+      else if (MI->getOperand(1).isGlobal()) {
+        const GlobalValue *GV = MI->getOperand(1).getGlobal();
+        BranchTarget = MCSymbolRefExpr::create(
+            GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
+      } else if (MI->getOperand(1).isSymbol()) {
+        BranchTarget = MCSymbolRefExpr::create(
+            GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
+            OutContext);
+      }
+
+      MCInst.addExpr(BranchTarget);
+    }
+
+      if (Opc == ARM::t2BFic) {
+        const MCExpr *ElseLabel = MCSymbolRefExpr::create(
+            getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
+                       MI->getOperand(2).getIndex(), OutContext),
+            OutContext);
+        MCInst.addExpr(ElseLabel);
+        MCInst.addImm(MI->getOperand(3).getImm());
+      } else {
+        MCInst.addImm(MI->getOperand(2).getImm())
+            .addReg(MI->getOperand(3).getReg());
+      }
+
+    EmitToStreamer(*OutStreamer, MCInst);
+    return;
+  }
+  case ARM::t2BF_LabelPseudo: {
+    // This is a pseudo op for a label used by a branch future instruction
+
+    // Emit the label.
+    OutStreamer->EmitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
+                                       getFunctionNumber(),
+                                       MI->getOperand(0).getIndex(), OutContext));
+    return;
+  }
   case ARM::tPICADD: {
     // This is a pseudo op for a label + instruction sequence, which looks like:
     // LPC0:
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -477,6 +477,21 @@
   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
 }
 
+static inline bool isVPTOpcode(int Opc) {
+  return Opc == ARM::t2VPTv16i8 || Opc == ARM::t2VPTv16u8 ||
+         Opc == ARM::t2VPTv16s8 || Opc == ARM::t2VPTv8i16 ||
+         Opc == ARM::t2VPTv8u16 || Opc == ARM::t2VPTv8s16 ||
+         Opc == ARM::t2VPTv4i32 || Opc == ARM::t2VPTv4u32 ||
+         Opc == ARM::t2VPTv4s32 || Opc == ARM::t2VPTv4f32 ||
+         Opc == ARM::t2VPTv8f16 || Opc == ARM::t2VPTv16i8r ||
+         Opc == ARM::t2VPTv16u8r || Opc == ARM::t2VPTv16s8r ||
+         Opc == ARM::t2VPTv8i16r || Opc == ARM::t2VPTv8u16r ||
+         Opc == ARM::t2VPTv8s16r || Opc == ARM::t2VPTv4i32r ||
+         Opc == ARM::t2VPTv4u32r || Opc == ARM::t2VPTv4s32r ||
+         Opc == ARM::t2VPTv4f32r || Opc == ARM::t2VPTv8f16r ||
+         Opc == ARM::t2VPST;
+}
+
 static inline
 bool isCondBranchOpcode(int Opc) {
   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -203,6 +203,8 @@
     for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
       if (Reserved.test(*SI))
         markSuperRegs(Reserved, Reg);
+  // For v8.1m architecture
+  markSuperRegs(Reserved, ARM::ZR);
 
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -189,6 +189,86 @@
   let DecoderMethod = "DecodeCCOutOperand";
 }
 
+// VPT predicate
+
+def VPTPredNOperand : AsmOperandClass {
+  let Name = "VPTPredN";
+  let PredicateMethod = "isVPTPred";
+}
+def VPTPredROperand : AsmOperandClass {
+  let Name = "VPTPredR";
+  let PredicateMethod = "isVPTPred";
+}
+def undef_tied_input;
+
+// Operand classes for the cluster of MC operands describing a
+// VPT-predicated MVE instruction.
+//
+// There are two of these classes. Both of them have the same first
+// two options:
+//
+// $cond (an integer) indicates the instruction's predication status:
+//   * ARMVCC::None means it's unpredicated
+//   * ARMVCC::Then means it's in a VPT block and appears with the T suffix
+//   * ARMVCC::Else means it's in a VPT block and appears with the E suffix.
+// During code generation, unpredicated and predicated instructions
+// are indicated by setting this parameter to 'None' or to 'Then'; the
+// third value 'Else' is only used for assembly and disassembly.
+//
+// $cond_reg (type VCCR) gives the input predicate register. This is
+// always either zero_reg or VPR, but needs to be modelled as an
+// explicit operand so that it can be register-allocated and spilled
+// when these operands are used in code generation).
+//
+// For 'vpred_r', there's an extra operand $inactive, which specifies
+// the vector register which will supply any lanes of the output
+// register that the predication mask prevents from being written by
+// this instruction. It's always tied to the actual output register
+// (i.e. must be allocated into the same physical reg), but again,
+// code generation will need to model it as a separate input value.
+//
+// 'vpred_n' doesn't have that extra operand: it only has $cond and
+// $cond_reg. This variant is used for any instruction that can't, or
+// doesn't want to, tie $inactive to the output register. Sometimes
+// that's because another input parameter is already tied to it (e.g.
+// instructions that both read and write their Qd register even when
+// unpredicated, either because they only partially overwrite it like
+// a narrowing integer conversion, or simply because the instruction
+// encoding doesn't have enough register fields to make the output
+// independent of all inputs). It can also be because the instruction
+// is defined to set disabled output lanes to zero rather than leaving
+// them unchanged (vector loads), or because it doesn't output a
+// vector register at all (stores, compares). In any of these
+// situations it's unnecessary to have an extra operand tied to the
+// output, and inconvenient to leave it there unused.
+
+// Base class for both kinds of vpred.
+class vpred_ops<dag extra_op, dag extra_mi> : OperandWithDefaultOps<OtherVT,
+            !con((ops (i32 0), (i32 zero_reg)), extra_op)> {
+  let PrintMethod = "printVPTPredicateOperand";
+  let OperandNamespace = "ARM";
+  let MIOperandInfo = !con((ops i32imm:$cond, VCCR:$cond_reg), extra_mi);
+
+  // For convenience, we provide a string value that can be appended
+  // to the constraints string. It's empty for vpred_n, and for
+  // vpred_r it ties the $inactive operand to the output q-register
+  // (which by convention will be called $Qd).
+  string vpred_constraint;
+}
+
+def vpred_r : vpred_ops<(ops (v4i32 undef_tied_input)), (ops MQPR:$inactive)> {
+  let ParserMatchClass = VPTPredROperand;
+  let OperandType = "OPERAND_VPRED_R";
+  let DecoderMethod = "DecodeVpredROperand";
+  let vpred_constraint = ",$Qd = $vp.inactive";
+}
+
+def vpred_n : vpred_ops<(ops), (ops)> {
+  let ParserMatchClass = VPTPredNOperand;
+  let OperandType = "OPERAND_VPRED_N";
+  let vpred_constraint = "";
+}
+
 // ARM special operands for disassembly only.
 //
 def SetEndAsmOperand : ImmAsmOperand<0,1> {
@@ -289,6 +369,8 @@
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
 class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
       : InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
+class MVEInstAlias<string Asm, dag Result, bit EmitPriority = 1>
+      : InstAlias<Asm, Result, EmitPriority>, Requires<[HasMVEInt, IsThumb]>;
 
 
 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
@@ -386,6 +468,8 @@
   : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
 class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
   : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
+class MVEAsmPseudo<string asm, dag iops, dag oops = (outs)>
+  : AsmPseudoInst<asm, iops, oops>, Requires<[HasMVEInt]>;
 
 // Pseudo instructions for the code generator.
 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -367,6 +367,16 @@
   let DecoderMethod = "DecodeRegListOperand";
 }
 
+// A list of general purpose registers and APSR separated by comma.
+// Used by CLRM
+def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; }
+def reglist_with_apsr : Operand<i32> {
+  let EncoderMethod = "getRegisterListOpValue";
+  let ParserMatchClass = RegListWithAPSRAsmOperand;
+  let PrintMethod = "printRegisterList";
+  let DecoderMethod = "DecodeRegListOperand";
+}
+
 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
 
 def DPRRegListAsmOperand : AsmOperandClass {
@@ -391,6 +401,21 @@
   let DecoderMethod = "DecodeSPRRegListOperand";
 }
 
+def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name =
+    "FPSRegListWithVPR"; }
+def fp_sreglist_with_vpr : Operand<i32> {
+  let EncoderMethod = "getRegisterListOpValue";
+  let ParserMatchClass = FPSRegListWithVPRAsmOperand;
+  let PrintMethod = "printRegisterList";
+}
+def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name =
+    "FPDRegListWithVPR"; }
+def fp_dreglist_with_vpr : Operand<i32> {
+  let EncoderMethod = "getRegisterListOpValue";
+  let ParserMatchClass = FPDRegListWithVPRAsmOperand;
+  let PrintMethod = "printRegisterList";
+}
+
 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
 def cpinst_operand : Operand<i32> {
   let PrintMethod = "printCPInstOperand";
@@ -436,6 +461,88 @@
   let ParserMatchClass = RotImmAsmOperand;
 }
 
+// vcmla_rot_imm: An integer that encodes a rotate amount. Must be 0, 90, 180, 270.
+def VCMLARotImmAsmOperand : AsmOperandClass {
+  let Name = "VCMLARotImm";
+  let RenderMethod = "addImmOperands";
+}
+def vcmla_rot_imm : Operand<i32> {
+  let EncoderMethod = "getVCMLARotOpValue";
+  let DecoderMethod = "DecodeVCMLARotOperand";
+  let ParserMatchClass = VCMLARotImmAsmOperand;
+}
+
+// vcadd_rot_imm: An integer that encodes a rotate amount. Must be 90, 180.
+def VCADDRotImmAsmOperand : AsmOperandClass {
+  let Name = "VCADDRotImm";
+  let RenderMethod = "addImmOperands";
+}
+def vcadd_rot_imm : Operand<i32> {
+  let EncoderMethod = "getVCADDRotOpValue";
+  let DecoderMethod = "DecodeVCADDRotOperand";
+  let ParserMatchClass = VCADDRotImmAsmOperand;
+}
+
+// Power of two operand
+def powertwo_asmoperand : AsmOperandClass { let Name = "PowerTwo"; }
+def powertwo : Operand<i32> {
+  let EncoderMethod = "getPowerTwoOpValue";
+  let DecoderMethod = "DecodePowerTwoOperand";
+  let ParserMatchClass = powertwo_asmoperand;
+}
+
+// Pair vector indexing
+class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass {
+  let Name = "MVEPairVectorIndex"#start;
+  let RenderMethod = "addMVEPairVectorIndexOperands";
+  let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">";
+}
+
+class MVEPairVectorIndex<string opval> : Operand<i32> {
+  let PrintMethod = "printVectorIndex";
+  let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">";
+  let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">";
+  let MIOperandInfo = (ops i32imm);
+}
+
+def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> {
+  let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">;
+}
+
+def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> {
+  let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">;
+}
+
+// Vector indexing
+class MVEVectorIndexOperand<string size> : AsmOperandClass {
+  let Name = "MVEVectorIndex"#size;
+  let RenderMethod = "addMVEVectorIndexOperands";
+  let PredicateMethod = "isMVEVectorIndex<"#size#">";
+}
+
+class MVEVectorIndex<string opval> : Operand<i32> {
+  let PrintMethod = "printVectorIndex";
+  let EncoderMethod = "getMVEVectorIndexOpValue<"#opval#">";
+  let DecoderMethod = "DecodeMVEVectorIndexOperand<"#opval#">";
+  let MIOperandInfo = (ops i32imm);
+}
+
+def MVEVectorIndex8  : MVEVectorIndex<"4"> {
+  let ParserMatchClass = MVEVectorIndexOperand<"16">;
+}
+def MVEVectorIndex16  : MVEVectorIndex<"2"> {
+  let ParserMatchClass = MVEVectorIndexOperand<"8">;
+}
+def MVEVectorIndex32  : MVEVectorIndex<"1"> {
+  let ParserMatchClass = MVEVectorIndexOperand<"4">;
+}
+
+def MVEImmSplatI64AsmOperand : AsmOperandClass { let Name = "MVEi64splat"; }
+def splati64 : Operand<i32> {
+  let PrintMethod = "printMVEi64SplatOperand";
+  let ParserMatchClass = MVEImmSplatI64AsmOperand;
+}
+
 // shift_imm: An integer that encodes a shift amount and the type of shift
 // (asr or lsl). The 6-bit immediate encodes as:
 //    {5}     0 ==> lsl
@@ -754,6 +861,32 @@
   let ParserMatchClass = Imm1_16AsmOperand;
 }
 
+def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> {
+  let Name = "MVEShiftImm1_7";
+  // Reason we're doing this is because instruction vshll.s8 t1 encoding
+  // accepts 1,7 but the t2 encoding accepts 8.  By doing this we can get a
+  // better diagnostic message if someone uses bigger immediate than the t1/t2
+  // encodings allow.
+  let DiagnosticString = "operand must be an immediate in the range [1,8]";
+}
+def mve_shift_imm1_7 : Operand<i32> {
+  let ParserMatchClass = MVEShiftImm1_7AsmOperand;
+  let EncoderMethod = "getMVEShiftImmOpValue";
+}
+
+def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> {
+  let Name = "MVEShiftImm1_15";
+  // Reason we're doing this is because instruction vshll.s16 t1 encoding
+  // accepts 1,15 but the t2 encoding accepts 16.  By doing this we can get a
+  // better diagnostic message if someone uses bigger immediate than the t1/t2
+  // encodings allow.
+  let DiagnosticString = "operand must be an immediate in the range [1,16]";
+}
+def mve_shift_imm1_15 : Operand<i32> {
+  let ParserMatchClass = MVEShiftImm1_15AsmOperand;
+  let EncoderMethod = "getMVEShiftImmOpValue";
+}
+
 // Define ARM specific addressing modes.
 // addrmode_imm12 := reg +/- imm12
 //
@@ -1134,6 +1267,15 @@
   let MIOperandInfo = (ops GPR:$base);
 }
 
+// t_addr_offset_none := reg [r0-r7]
+def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; }
+def t_addr_offset_none : MemOperand {
+  let PrintMethod = "printAddrMode7Operand";
+  let DecoderMethod = "DecodetGPRRegisterClass";
+  let ParserMatchClass = MemNoOffsetTAsmOperand;
+  let MIOperandInfo = (ops tGPR:$base);
+}
+
 def nohash_imm : Operand<i32> {
   let PrintMethod = "printNoHashImmediate";
 }
@@ -5734,6 +5876,12 @@
 include "ARMInstrNEON.td"
 
 //===----------------------------------------------------------------------===//
+// MVE Support
+//
+
+include "ARMInstrMVE.td"
+
+//===----------------------------------------------------------------------===//
 // Assembler aliases
 //
 
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -0,0 +1,4068 @@
+class ExpandImmAsmOp<string shift> : AsmOperandClass {
+  let Name = !strconcat("ExpandImm", shift);
+  let PredicateMethod = !strconcat("isExpImm<", shift, ">");
+  let RenderMethod = "addImmOperands";
+}
+class InvertedExpandImmAsmOp<string shift, string size> : AsmOperandClass {
+  let Name = !strconcat("InvertedExpandImm", shift, "_", size);
+  let PredicateMethod = !strconcat("isInvertedExpImm<", shift, ",", size, ">");
+  let RenderMethod = "addImmOperands";
+}
+
+class ExpandImm<string shift> : Operand<i32> {
+  let ParserMatchClass = ExpandImmAsmOp<shift>;
+  let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",false>");
+  let DecoderMethod = !strconcat("DecodeExpandedImmOperand<",shift,">");
+  let PrintMethod = "printExpandedImmOperand";
+}
+class InvertedExpandImm<string shift, string size> : Operand<i32> {
+  let ParserMatchClass = InvertedExpandImmAsmOp<shift, size>;
+  let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",true>");
+  let DecoderMethod = !strconcat(
+    "DecodeInvertedExpandedImmOperand<",shift,",",size,">");
+  let PrintMethod = "printExpandedImmOperand";
+}
+
+def expzero00 : ExpandImm<"0">;
+def expzero08 : ExpandImm<"8">;
+def expzero16 : ExpandImm<"16">;
+def expzero24 : ExpandImm<"24">;
+
+def expzero00inv16 : InvertedExpandImm<"0", "16">;
+def expzero08inv16 : InvertedExpandImm<"8", "16">;
+
+def expzero00inv32 : InvertedExpandImm<"0", "32">;
+def expzero08inv32 : InvertedExpandImm<"8", "32">;
+def expzero16inv32 : InvertedExpandImm<"16", "32">;
+def expzero24inv32 : InvertedExpandImm<"24", "32">;
+
+def mve_vmovfp : Operand<i32> {
+  let PrintMethod = "printFPImmOperand";
+  let ParserMatchClass = FPImmOperand;
+}
+
+// VPT condition mask
+def vpt_mask : Operand<i32> {
+  let PrintMethod = "printVPTMask";
+  let ParserMatchClass = it_mask_asmoperand;
+  let EncoderMethod = "getVPTMaskOpValue";
+  let DecoderMethod = "DecodeVPTMaskOperand";
+}
+
+// VPT/VCMP restricted predicate for sign invariant types
+def pred_restricted_i_asmoperand : AsmOperandClass {
+  let Name = "CondCodeRestrictedI";
+  let RenderMethod = "addITCondCodeOperands";
+  let PredicateMethod = "isITCondCodeRestrictedI";
+  let ParserMethod = "parseITCondCode";
+}
+
+// VPT/VCMP restricted predicate for signed types
+def pred_restricted_s_asmoperand : AsmOperandClass {
+  let Name = "CondCodeRestrictedS";
+  let RenderMethod = "addITCondCodeOperands";
+  let PredicateMethod = "isITCondCodeRestrictedS";
+  let ParserMethod = "parseITCondCode";
+}
+
+// VPT/VCMP restricted predicate for unsigned types
+def pred_restricted_u_asmoperand : AsmOperandClass {
+  let Name = "CondCodeRestrictedU";
+  let RenderMethod = "addITCondCodeOperands";
+  let PredicateMethod = "isITCondCodeRestrictedU";
+  let ParserMethod = "parseITCondCode";
+}
+
+// VPT/VCMP restricted predicate for floating point
+def pred_restricted_fp_asmoperand : AsmOperandClass {
+  let Name = "CondCodeRestrictedFP";
+  let RenderMethod = "addITCondCodeOperands";
+  let PredicateMethod = "isITCondCodeRestrictedFP";
+  let ParserMethod = "parseITCondCode";
+}
+
+def pred_basic_i : Operand<i32> {
+  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
+  let ParserMatchClass = pred_restricted_i_asmoperand;
+  let DecoderMethod = "DecodeRestrictedIPredicateOperand";
+  let EncoderMethod = "getRestrictedCondCodeOpValue";
+}
+
+def pred_basic_u : Operand<i32> {
+  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
+  let ParserMatchClass = pred_restricted_u_asmoperand;
+  let DecoderMethod = "DecodeRestrictedUPredicateOperand";
+  let EncoderMethod = "getRestrictedCondCodeOpValue";
+}
+
+def pred_basic_s : Operand<i32> {
+  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
+  let ParserMatchClass = pred_restricted_s_asmoperand;
+  let DecoderMethod = "DecodeRestrictedSPredicateOperand";
+  let EncoderMethod = "getRestrictedCondCodeOpValue";
+}
+
+def pred_basic_fp : Operand<i32> {
+  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
+  let ParserMatchClass = pred_restricted_fp_asmoperand;
+  let DecoderMethod = "DecodeRestrictedFPPredicateOperand";
+  let EncoderMethod = "getRestrictedCondCodeOpValue";
+}
+
+class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
+             string ops, string cstr, list<dag> pattern>
+  : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
+             pattern>,
+    Requires<[HasMVEInt]> {
+  let D = MVEDomain;
+  let DecoderNamespace = "MVE";
+}
+
+// MVE_p is used for most predicated instructions, to add the cluster
+// of input operands that provides the VPT suffix (none, T or E) and
+// the input predicate register.
+class MVE_p<dag oops, dag iops, InstrItinClass itin, string iname,
+            string suffix, string ops, vpred_ops vpred, string cstr,
+            list<dag> pattern=[]>
+  : MVE_MI<oops, !con(iops, (ins vpred:$vp)), itin,
+           // If the instruction has a suffix, like vadd.f32, then the
+           // VPT predication suffix goes before the dot, so the full
+           // name has to be "vadd${vp}.f32".
+           !strconcat(iname, "${vp}",
+                      !if(!eq(suffix, ""), "", !strconcat(".", suffix))),
+           ops, !strconcat(cstr, vpred.vpred_constraint), pattern> {
+  let Inst{31-29} = 0b111;
+  let Inst{27-26} = 0b11;
+}
+
+class MVE_f<dag oops, dag iops, InstrItinClass itin, string iname,
+            string suffix, string ops, vpred_ops vpred, string cstr,
+            list<dag> pattern=[]>
+  : MVE_p<oops, iops, itin, iname, suffix, ops, vpred, cstr, pattern> {
+  let Predicates = [HasMVEFloat];
+}
+
+class V8_1_MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
+             string ops, string cstr, list<dag> pattern>
+  : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm, !strconcat("\t", ops), cstr,
+             pattern>,
+    Requires<[HasV8_1MMainline, HasMVEInt]> {
+  let D = MVEDomain;
+  let DecoderNamespace = "MVE";
+}
+
+class VMOV<dag oops, dag iops, InstrItinClass itin, string asm,
+           string suffix, string ops, string cstr, list<dag> pattern>
+  : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm,
+            !strconcat(!if(!eq(suffix, ""), "", !strconcat(".", suffix)), "\t", ops),
+            cstr, pattern>,
+    Requires<[HasV8_1MMainline, HasMVEInt]> {
+  let D = MVEDomain;
+  let DecoderNamespace = "MVE";
+}
+
+class t2MVEShift<string iname, dag oops, dag iops, string asm, string cstr,
+            list<dag> pattern=[]>
+  : V8_1_MVE_MI<oops, iops, NoItinerary, iname, asm,
+                cstr, pattern> {
+  let Inst{31-20} = 0b111010100101;
+  let Inst{8} = 0b1;
+
+}
+
+class t2MVEShiftSingleReg<string iname, dag iops, string asm, string cstr,
+                    list<dag> pattern=[]>
+  : t2MVEShift<iname, (outs rGPR:$RdaDest), iops, asm, cstr, pattern> {
+  bits<4> RdaDest;
+
+  let Inst{19-16} = RdaDest{3-0};
+}
+
+class t2MVEShiftSRegImm<string iname, list<dag> pattern=[]>
+  : t2MVEShiftSingleReg<iname, (ins rGPR:$RdaSrc, long_shift:$imm),
+                     "$RdaSrc, $imm", "$RdaDest = $RdaSrc", pattern> {
+  bits<5> imm;
+
+  let Inst{15} = 0b0;
+  let Inst{14-12} = imm{4-2};
+  let Inst{11-8} = 0b1111;
+  let Inst{7-6} = imm{1-0};
+  let Inst{3-0} = 0b1111;
+}
+
+def t2SQSHL : t2MVEShiftSRegImm<"sqshl"> {
+  let Inst{5-4} = 0b11;
+}
+
+def t2SRSHR : t2MVEShiftSRegImm<"srshr"> {
+  let Inst{5-4} = 0b10;
+}
+
+def t2UQSHL : t2MVEShiftSRegImm<"uqshl"> {
+  let Inst{5-4} = 0b00;
+}
+
+def t2URSHR : t2MVEShiftSRegImm<"urshr"> {
+  let Inst{5-4} = 0b01;
+}
+
+class t2MVEShiftSRegReg<string iname, list<dag> pattern=[]>
+  : t2MVEShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
+                     "$RdaSrc, $Rm", "$RdaDest = $RdaSrc", pattern> {
+  bits<4> Rm;
+
+  let Inst{15-12} = Rm{3-0};
+  let Inst{11-8} = 0b1111;
+  let Inst{7-6} = 0b00;
+  let Inst{3-0} = 0b1101;
+}
+
+def t2SQRSHR : t2MVEShiftSRegReg<"sqrshr"> {
+  let Inst{5-4} = 0b10;
+}
+
+def t2UQRSHL : t2MVEShiftSRegReg<"uqrshl"> {
+  let Inst{5-4} = 0b00;
+}
+
+class t2MVEShiftDoubleReg<string iname, dag iops, string asm, string cstr,
+                       list<dag> pattern=[]>
+  : t2MVEShift<iname, (outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, asm, cstr,
+            pattern> {
+  bits<4> RdaLo;
+  bits<4> RdaHi;
+
+  let Inst{19-17} = RdaLo{3-1};
+  let Inst{11-9} = RdaHi{3-1};
+}
+
+class t2MVEShiftDRegImm<string iname, list<dag> pattern=[]>
+  : t2MVEShiftDoubleReg<iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src,
+                        long_shift:$imm), "$RdaLo, $RdaHi, $imm",
+                        "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src", pattern> {
+  bits<5> imm;
+
+  let Inst{15} = 0b0;
+  let Inst{14-12} = imm{4-2};
+  let Inst{7-6} = imm{1-0};
+  let Inst{4-0} = 0b01111;
+}
+
+class t2MVEShiftDRegReg<string iname, list<dag> pattern=[]>
+  : t2MVEShiftDoubleReg<iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
+                    "$RdaLo, $RdaHi, $Rm",
+                    "@earlyclobber $RdaHi,@earlyclobber $RdaLo,$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
+                    pattern> {
+  bits<4> Rm;
+
+  let Inst{16} = 0b0;
+  let Inst{15-12} = Rm{3-0};
+  let Inst{7-6} = 0b00;
+  let Inst{4} = 0b0;
+  let Inst{3-0} = 0b1101;
+}
+
+def t2ASRLr : t2MVEShiftDRegReg<"asrl"> {
+  let Inst{5} = 0b1;
+  // Custom decoder method because SQRSHR overlaps this encoding
+  let DecoderMethod = "DecodeMVEOverlappingLongShift";
+}
+
+def t2ASRLi : t2MVEShiftDRegImm<"asrl"> {
+  let Inst{5} = 0b1;
+}
+
+def t2LSLLr : t2MVEShiftDRegReg<"lsll"> {
+  let Inst{5} = 0b0;
+  // Custom decoder method because UQRSHL overlaps this encoding
+  let DecoderMethod = "DecodeMVEOverlappingLongShift";
+}
+
+def t2LSLLi : t2MVEShiftDRegImm<"lsll"> {
+  let Inst{5} = 0b0;
+}
+
+def t2LSRL : t2MVEShiftDRegImm<"lsrl"> {
+  let Inst{5-4} = 0b01;
+}
+
+def t2SQRSHRL : t2MVEShiftDRegReg<"sqrshrl"> {
+  let Inst{5} = 0b1;
+  let Inst{16} = 0b1;
+  // Custom decoder method because SQRSHR overlaps this encoding
+  let DecoderMethod = "DecodeMVEOverlappingLongShift";
+}
+
+def t2SQSHLL : t2MVEShiftDRegImm<"sqshll"> {
+  let Inst{5-4} = 0b11;
+  let Inst{16} = 0b1;
+}
+
+def t2SRSHRL : t2MVEShiftDRegImm<"srshrl"> {
+  let Inst{5} = 0b1;
+  let Inst{16} = 0b1;
+}
+
+def t2UQRSHLL : t2MVEShiftDRegReg<"uqrshll"> {
+  let Inst{5} = 0b0;
+  let Inst{16} = 0b1;
+  // Custom decoder method because UQRSHL overlaps this encoding
+  let DecoderMethod = "DecodeMVEOverlappingLongShift";
+}
+
+def t2UQSHLL : t2MVEShiftDRegImm<"uqshll"> {
+  let Inst{5} = 0b0;
+  let Inst{16} = 0b1;
+}
+
+def t2URSHRL : t2MVEShiftDRegImm<"urshrl"> {
+  let Inst{5-4} = 0b01;
+  let Inst{16} = 0b1;
+}
+
+// start of mve_rDest instructions
+
+class MVE_rDest<dag oops, dag iops, InstrItinClass itin, string iname, string suffix,
+                string ops, string cstr, list<dag> pattern=[]>
+// Always use vpred_n and not vpred_r: with the output register being
+// a GPR and not a vector register, there can't be any question of
+// what to put in its inactive lanes.
+  : MVE_p<oops, iops, itin, iname, suffix, ops, vpred_n, cstr, pattern> {
+
+  let Inst{25-23} = 0b101;
+  let Inst{11-9} = 0b111;
+  let Inst{4} = 0b0;
+}
+
+class t2VABAV<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$Rda), (ins rGPR:$Rda_src, MQPR:$Qn, MQPR:$Qm),
+              NoItinerary, "vabav", suffix, "$Rda, $Qn, $Qm", "$Rda = $Rda_src",
+              pattern> {
+  bits<4> Qm;
+  bits<4> Qn;
+  bits<4> Rda;
+
+  let Inst{28} = U;
+  let Inst{22} = 0b0;
+  let Inst{21-20} = size{1-0};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-12} = Rda{3-0};
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def VABAVs8  : t2VABAV<"s8", 0b0, 0b00>;
+def VABAVs16 : t2VABAV<"s16", 0b0, 0b01>;
+def VABAVs32 : t2VABAV<"s32", 0b0, 0b10>;
+def VABAVu8  : t2VABAV<"u8", 0b1, 0b00>;
+def VABAVu16 : t2VABAV<"u16", 0b1, 0b01>;
+def VABAVu32 : t2VABAV<"u32", 0b1, 0b10>;
+
+class t2VADDV<string suffix, bit A, string acc, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$Rda), (ins tGPREven:$Rda_src, MQPR:$Qm), NoItinerary,
+              !strconcat("vaddv", acc), suffix, "$Rda, $Qm", "$Rda = $Rda_src",
+              pattern> {
+  bits<3> Qm;
+  bits<4> Rda;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b111;
+  let Inst{19-18} = size{1-0};
+  let Inst{17-16} = 0b01;
+  let Inst{15-13} = Rda{3-1};
+  let Inst{12} = 0b0;
+  let Inst{8-6} = 0b100;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VADDV_A<string suffix, bit U, bits<2> size, list<dag> pattern=[]> {
+  def acc : t2VADDV<suffix, 1, "a", U, size>;
+  def no_acc : t2VADDV<suffix, 0, "", U, size>;
+}
+
+defm VADDVs8  : t2VADDV_A<"s8", 0b0, 0b00>;
+defm VADDVs16 : t2VADDV_A<"s16", 0b0, 0b01>;
+defm VADDVs32 : t2VADDV_A<"s32", 0b0, 0b10>;
+defm VADDVu8  : t2VADDV_A<"u8", 0b1, 0b00>;
+defm VADDVu16 : t2VADDV_A<"u16", 0b1, 0b01>;
+defm VADDVu32 : t2VADDV_A<"u32", 0b1, 0b10>;
+
+class t2VADDLV<string suffix, bit A, string acc, bit U, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), (ins tGPREven:$RdaLo_src,
+              tGPROdd:$RdaHi_src, MQPR:$Qm), NoItinerary, !strconcat("vaddlv", acc),
+              suffix, "$RdaLo, $RdaHi, $Qm", "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
+              pattern> {
+  bits<3> Qm;
+  bits<4> RdaLo;
+  bits<4> RdaHi;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHi{3-1};
+  let Inst{19-18} = 0b10;
+  let Inst{17-16} = 0b01;
+  let Inst{15-13} = RdaLo{3-1};
+  let Inst{12} = 0b0;
+  let Inst{8-6} = 0b100;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
+  def acc : t2VADDLV<suffix, 1, "a", U>;
+  def no_acc : t2VADDLV<suffix, 0, "", U>;
+}
+
+
+defm VADDLVs32 : t2VADDLV_A<"s32", 0b0>;
+defm VADDLVu32 : t2VADDLV_A<"u32", 0b1>;
+
+class t2VMINNM<string iname, string suffix, bit sz, bit bit_17,
+               list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<3> Qm;
+  bits<4> RdaDest;
+
+  let Inst{28} = sz;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = 0b11;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b110;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+multiclass t2VMINNM_fty<string iname, bit bit_17, list<dag> pattern=[]> {
+  def f32 : t2VMINNM<iname, "f32", 0b0, bit_17>;
+  def f16 : t2VMINNM<iname, "f16", 0b1, bit_17>;
+}
+
+defm VMINNMV : t2VMINNM_fty<"vminnmv", 0b1>;
+defm VMINNMAV : t2VMINNM_fty<"vminnmav", 0b0>;
+
+class t2VMINV<string iname, string suffix, bit U, bits<2> size,
+              bit bit_17, list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
+              iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
+  bits<3> Qm;
+  bits<4> RdaDest;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = size{1-0};
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b110;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+// Prefixed with MVE to prevent conflict with A57 scheduler.
+def MVE_VMINVs8  : t2VMINV<"vminv", "s8", 0b0, 0b00, 0b1>;
+def MVE_VMINVs16 : t2VMINV<"vminv", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMINVs32 : t2VMINV<"vminv", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMINVu8  : t2VMINV<"vminv", "u8", 0b1, 0b00, 0b1>;
+def MVE_VMINVu16 : t2VMINV<"vminv", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMINVu32 : t2VMINV<"vminv", "u32", 0b1, 0b10, 0b1>;
+
+def MVE_VMINAVs8  : t2VMINV<"vminav", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMINAVs16 : t2VMINV<"vminav", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMINAVs32 : t2VMINV<"vminav", "s32", 0b0, 0b10, 0b0>;
+
+class t2VMAXNMV<string iname, string suffix, bit sz, bit bit_17,
+                list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+
+  let Inst{28} = sz;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = 0b11;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b100;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VMAXNMVf32 : t2VMAXNMV<"vmaxnmv", "f32", 0b0, 0b1>;
+def VMAXNMVf16 : t2VMAXNMV<"vmaxnmv", "f16", 0b1, 0b1>;
+
+def VMAXNMAVf32 : t2VMAXNMV<"vmaxnmav", "f32", 0b0, 0b0>;
+def VMAXNMAVf16 : t2VMAXNMV<"vmaxnmav", "f16", 0b1, 0b0>;
+
+class t2VMAX<string iname, string suffix, bit U, bits<2> size, bit bit_17,
+                list<dag> pattern=[]>
+  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b110;
+  let Inst{19-18} = size{1-0};
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b0;
+  let Inst{15-12} = RdaDest{3-0};
+  let Inst{8-6} = 0b100;
+  let Inst{5} = 0b0; // undefined if 1
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+def MVE_VMAXVs8  : t2VMAX<"vmaxv", "s8", 0b0, 0b00, 0b1>;
+def MVE_VMAXVs16 : t2VMAX<"vmaxv", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMAXVs32 : t2VMAX<"vmaxv", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMAXVu8  : t2VMAX<"vmaxv", "u8", 0b1, 0b00, 0b1>;
+def MVE_VMAXVu16 : t2VMAX<"vmaxv", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMAXVu32 : t2VMAX<"vmaxv", "u32", 0b1, 0b10, 0b1>;
+
+def MVE_VMAXAVs8  : t2VMAX<"vmaxav", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMAXAVs16 : t2VMAX<"vmaxav", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMAXAVs32 : t2VMAX<"vmaxav", "s32", 0b0, 0b10, 0b0>;
+
+class t2VMLADAV<string iname, string suffix, bit sz, bit U,
+                bit A, bit X, bit bit_8, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaDest), (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+              NoItinerary, !strconcat(iname, !if(!eq(A, 1), "a", ""),
+              !if(!eq(X, 1), "x", "")), suffix, "$RdaSrc, $Qn, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = 0b111;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaDest{3-1};
+  let Inst{12} = X; // undefined if 1
+  let Inst{8} = bit_8;
+  let Inst{7-6} = 0b00; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VMLADAV_multi<string iname, string suffix, bit sz, bit U,
+                           bit bit_8, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLADAV<iname, suffix, sz, U, 0b1, 0b0, bit_8, pattern>;
+  def noacc_exch : t2VMLADAV<iname, suffix, sz, U, 0b0, 0b1, bit_8, pattern>;
+  def acc_exch : t2VMLADAV<iname, suffix, sz, U, 0b1, 0b1, bit_8, pattern>;
+  def noacc_noexch : t2VMLADAV<iname, suffix, sz, U, 0b0, 0b0, bit_8, pattern>;
+}
+
+defm VMLADAVs16 : t2VMLADAV_multi<"vmladav", "s16", 0b0, 0b0, 0b0>;
+defm VMLADAVs32 : t2VMLADAV_multi<"vmladav", "s32", 0b1, 0b0, 0b0>;
+defm VMLADAVu16 : t2VMLADAV_multi<"vmladav", "u16", 0b0, 0b1, 0b0>;
+defm VMLADAVu32 : t2VMLADAV_multi<"vmladav", "u32", 0b1, 0b1, 0b0>;
+
+defm VMLADAVs8 : t2VMLADAV_multi<"vmladav", "s8", 0b0, 0b0, 0b1>;
+defm VMLADAVu8 : t2VMLADAV_multi<"vmladav", "u8", 0b0, 0b1, 0b1>;
+
+// vmlav aliases vmladav
+foreach acc = ["acc", "noacc"] in {
+  foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
+    def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "acc"), "a", ""),
+                       "${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
+                       (!cast<Instruction>(!strconcat("VMLADAV", suffix, acc, "_noexch")) tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+  }
+}
+
+class t2VRMLALDAVH<string iname, string suffix, bit U, bit A,
+                   bit X, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm", "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
+              pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b100; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VRMLALDAVH_multi<string iname, string suffix, bit U,
+                              list<dag> pattern=[]> {
+  def acc_noexch : t2VRMLALDAVH<iname, suffix, U, 0b1, 0b0, pattern>;
+  def noacc_exch : t2VRMLALDAVH<iname, suffix, U, 0b0, 0b1, pattern>;
+  def acc_exch : t2VRMLALDAVH<iname, suffix, U, 0b1, 0b1, pattern>;
+  def noacc_noexch : t2VRMLALDAVH<iname, suffix, U, 0b0, 0b0, pattern>;
+}
+
+defm t2VRMLALDAVHs32 : t2VRMLALDAVH_multi<"vrmlaldavh", "s32", 0>;
+defm t2VRMLALDAVHu32 : t2VRMLALDAVH_multi<"vrmlaldavh", "u32", 1>;
+
+// vrmlalvh aliases for vrmlaldavh
+def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHs32noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHs32acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHu32noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+                  (t2VRMLALDAVHu32acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+
+class t2VMLSDAV<string iname, string suffix, bit sz, bit A,
+                bit X, bit bit_28, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaDest), (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+              NoItinerary, !strconcat(iname, !if(!eq(A, 1), "a", ""),
+              !if(!eq(X, 1), "x", "")), suffix, "$RdaSrc, $Qn, $Qm",
+              "$RdaDest = $RdaSrc", pattern> {
+  bits<4> RdaDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{22-20} = 0b111;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b000; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+multiclass t2VMLSDAV_multi<string iname, string suffix, bit sz,
+                           bit bit_28, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLSDAV<iname, suffix, sz, 0b1, 0b0, bit_28, pattern>;
+  def noacc_exch : t2VMLSDAV<iname, suffix, sz, 0b0, 0b1, bit_28, pattern>;
+  def acc_exch : t2VMLSDAV<iname, suffix, sz, 0b1, 0b1, bit_28, pattern>;
+  def noacc_noexch : t2VMLSDAV<iname, suffix, sz, 0b0, 0b0, bit_28, pattern>;
+}
+
+defm t2VMLSDAVs8  : t2VMLSDAV_multi<"vmlsdav", "s8", 0, 0b1>;
+defm t2VMLSDAVs16 : t2VMLSDAV_multi<"vmlsdav", "s16", 0, 0b0>;
+defm t2VMLSDAVs32 : t2VMLSDAV_multi<"vmlsdav", "s32", 1, 0b0>;
+
+class t2VMLALDAV<string iname, string suffix, bit sz, bit U, bit A,
+                   bit X, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm",
+              "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc", pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<3> Qm;
+  bits<3> Qn;
+
+  let Inst{28} = U;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8-6} = 0b000; // bit 7 if 1 is undefined
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass t2VMLALDAV_multi<string iname, string suffix, bit sz,
+                            bit U, list<dag> pattern=[]> {
+  def acc_noexch : t2VMLALDAV<iname, suffix, sz, U, 0b1, 0b0, pattern>;
+  def noacc_exch : t2VMLALDAV<iname, suffix, sz, U, 0b0, 0b1, pattern>;
+  def acc_exch : t2VMLALDAV<iname, suffix, sz, U, 0b1, 0b1, pattern>;
+  def noacc_noexch : t2VMLALDAV<iname, suffix, sz, U, 0b0, 0b0, pattern>;
+}
+
+defm VMLALDAVs16 : t2VMLALDAV_multi<"vmlaldav", "s16", 0, 0>;
+defm VMLALDAVs32 : t2VMLALDAV_multi<"vmlaldav", "s32", 1, 0>;
+defm VMLALDAVu16 : t2VMLALDAV_multi<"vmlaldav", "u16", 0, 1>;
+defm VMLALDAVu32 : t2VMLALDAV_multi<"vmlaldav", "u32", 1, 1>;
+
+// vmlalv aliases vmlaldav
+foreach acc = ["acc", "noacc"] in {
+  foreach suffix = ["s16", "s32", "u16", "u32"] in {
+    def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "acc"), "a", ""),
+                       "${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
+                       (!cast<Instruction>(!strconcat("VMLALDAV", suffix, acc, "_noexch"))
+                       tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
+                       MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+  }
+}
+
+class t2VMLSLDAV<string iname, string suffix, bit A, bit X,
+                 bit sz, bit bit_28, list<dag> pattern=[]>
+  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), (ins tGPREven:$RdaLoSrc,
+              tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm), NoItinerary, !strconcat(iname,
+              !if(!eq(A, 1), "a", ""), !if(!eq(X, 1), "x", "")), suffix,
+              "$RdaLoSrc, $RdaHiSrc, $Qn, $Qm",
+              "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc", pattern> {
+  bits<4> RdaLoDest;
+  bits<4> RdaHiDest;
+  bits<4> Qm;
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{22-20} = RdaHiDest{3-1};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = sz;
+  let Inst{15-13} = RdaLoDest{3-1};
+  let Inst{12} = X;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = A;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+multiclass t2VMLSLDAwV_multi<string iname, string suffix, bit sz,
+                             bit bit_28, list<dag> pattern=[]> {
+  def acc_noexch   : t2VMLSLDAV<iname, suffix, 0b1, 0b0, sz, bit_28, pattern>;
+  def noacc_exch   : t2VMLSLDAV<iname, suffix, 0b0, 0b1, sz, bit_28, pattern>;
+  def acc_exch     : t2VMLSLDAV<iname, suffix, 0b1, 0b1, sz, bit_28, pattern>;
+  def noacc_noexch : t2VMLSLDAV<iname, suffix, 0b0, 0b0, sz, bit_28, pattern>;
+}
+
+defm t2VMLSLDAVs16   : t2VMLSLDAwV_multi<"vmlsldav", "s16", 0b0, 0b0>;
+defm t2VMLSLDAVs32   : t2VMLSLDAwV_multi<"vmlsldav", "s32", 0b1, 0b0>;
+defm t2VRMLSLDAVHs32 : t2VMLSLDAwV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
+
+// end of mve_rDest instructions
+
+// start of mve_comp instructions
+
+class MVE_comp<InstrItinClass itin, string iname, string suffix,
+               string cstr, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), itin, iname, suffix,
+           "$Qd, $Qn, $Qm", vpred_r, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = 0b0;
+  let Inst{10-9} = 0b11;
+  let Inst{7} = Qn{3};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+class VMINMAXNM<string iname, string suffix, bit sz, bit bit_21,
+                list<dag> pattern=[]>
+  : MVE_comp<NoItinerary, iname, suffix, "", pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-24} = 0b11;
+  let Inst{23} = 0b0;
+  let Inst{21} = bit_21;
+  let Inst{20} = sz;
+  let Inst{11} = 0b1;
+  let Inst{8} = 0b1;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b1;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VMAXNMf32 : VMINMAXNM<"vmaxnm", "f32", 0b0, 0b0>;
+def VMAXNMf16 : VMINMAXNM<"vmaxnm", "f16", 0b1, 0b0>;
+
+def VMINNMf32 : VMINMAXNM<"vminnm", "f32", 0b0, 0b1>;
+def VMINNMf16 : VMINMAXNM<"vminnm", "f16", 0b1, 0b1>;
+
+class VMINMAX<string iname, string suffix, bit U, bits<2> size,
+              bit bit_4, list<dag> pattern=[]>
+  : MVE_comp<NoItinerary, iname, suffix, "", pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-24} = 0b11;
+  let Inst{23} = 0b0;
+  let Inst{21-20} = size{1-0};
+  let Inst{11} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{6} = 0b1;
+  let Inst{4} = bit_4;
+}
+
+// prefix with MVE to avoid conflict with NEON equivalents.
+def MVE_VMAXs8 : VMINMAX<"vmax", "s8", 0b0, 0b00, 0b0>;
+def MVE_VMAXs16 : VMINMAX<"vmax", "s16", 0b0, 0b01, 0b0>;
+def MVE_VMAXs32 : VMINMAX<"vmax", "s32", 0b0, 0b10, 0b0>;
+def MVE_VMAXu8 : VMINMAX<"vmax", "u8", 0b1, 0b00, 0b0>;
+def MVE_VMAXu16 : VMINMAX<"vmax", "u16", 0b1, 0b01, 0b0>;
+def MVE_VMAXu32 : VMINMAX<"vmax", "u32", 0b1, 0b10, 0b0>;
+
+// prefix with MVE to avoid conflict with NEON equivalents.
+def MVE_VMINs8 : VMINMAX<"vmin", "s8", 0b0, 0b00, 0b1>;
+def MVE_VMINs16 : VMINMAX<"vmin", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMINs32 : VMINMAX<"vmin", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMINu8 : VMINMAX<"vmin", "u8", 0b1, 0b00, 0b1>;
+def MVE_VMINu16 : VMINMAX<"vmin", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMINu32 : VMINMAX<"vmin", "u32", 0b1, 0b10, 0b1>;
+
+// end of mve_comp instructions
+
+// start of mve_imm_shift instructions
+
+def VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd), (ins MQPR:$QdSrc, rGPR:$RdmSrc,
+                  long_shift:$imm), NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
+                  vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {
+  bits<5> imm;
+  bits<4> Qd;
+  bits<4> RdmDest;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b101;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b1;
+  let Inst{20-16} = imm{4-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-4} = 0b011111100;
+  let Inst{3-0} = RdmDest{3-0};
+}
+
+class MVE_imm_shift<dag oops, dag iops, string iname, string suffix,
+                    string ops, vpred_ops vpred, string cstr,
+                    list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class t2VMOVL<string iname, string suffix, bits<2> sz, bit U,
+              list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), (ins MQPR:$Qm),
+                  iname, suffix, "$Qd, $Qm", vpred_r, "",
+                  pattern> {
+  let Inst{28} = U;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b1;
+  let Inst{20-19} = sz{1-0};
+  let Inst{18-16} = 0b000;
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+multiclass VMOVL_shift_half<string iname, string suffix, bits<2> sz, bit U,
+                            list<dag> pattern=[]> {
+  def bh : t2VMOVL<!strconcat(iname, "b"), suffix, sz, U, pattern> {
+    let Inst{12} = 0b0;
+  }
+  def th : t2VMOVL<!strconcat(iname, "t"), suffix, sz, U, pattern> {
+    let Inst{12} = 0b1;
+  }
+}
+
+defm VMOVLs8 : VMOVL_shift_half<"vmovl", "s8", 0b01, 0b0>;
+defm VMOVLu8 : VMOVL_shift_half<"vmovl", "u8", 0b01, 0b1>;
+defm VMOVLs16 : VMOVL_shift_half<"vmovl", "s16", 0b10, 0b0>;
+defm VMOVLu16 : VMOVL_shift_half<"vmovl", "u16", 0b10, 0b1>;
+
+class t2VSHLLt2<string iname, string suffix, bits<2> size, bit U, string ops,
+              list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), (ins MQPR:$Qm),
+                  iname, suffix, ops, vpred_r, "", pattern> {
+  let Inst{28} = U;
+  let Inst{25-23} = 0b100;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size{1-0};
+  let Inst{17-16} = 0b01;
+  let Inst{11-6} = 0b111000;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+multiclass VSHLLt2_shift_half<string iname, string suffix, bits<2> sz, bit U,
+                              string ops, list<dag> pattern=[]> {
+  def bh : t2VSHLLt2<!strconcat(iname, "b"), suffix, sz, U, ops, pattern> {
+    let Inst{12} = 0b0;
+  }
+  def th : t2VSHLLt2<!strconcat(iname, "t"), suffix, sz, U, ops, pattern> {
+    let Inst{12} = 0b1;
+  }
+}
+
+defm t2VSHLLs8 : VSHLLt2_shift_half<"vshll", "s8", 0b00, 0b0, "$Qd, $Qm, #8">;
+defm t2VSHLLs16 : VSHLLt2_shift_half<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
+defm t2VSHLLu8 : VSHLLt2_shift_half<"vshll", "u8", 0b00, 0b1, "$Qd, $Qm, #8">;
+defm t2VSHLLu16 : VSHLLt2_shift_half<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
+
+class t2VSHLLt1<string iname, string suffix, bit sz, bit U,
+              dag immops, list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), !con((ins MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $szimm5", vpred_r, "", pattern> {
+  // We only use the first 4 bits of this field because otherwise the decoder
+  // would have encoding conflicts between the 8 and 16-bit variants, since the
+  // difference between the two would only be visible in a variable encoding
+  // element.
+  bits<5> szimm5;
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b1;
+  let Inst{20} = sz;
+  let Inst{19-16} = szimm5{3-0};
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+  let DecoderMethod = "DecodeMVEVSHLL";
+}
+
+multiclass VSHLLt1_shift_half<string iname, string suffix, bit sz, bit U,
+                              dag immops, list<dag> pattern=[]> {
+  def bh : t2VSHLLt1<!strconcat(iname, "b"), suffix, sz, U, immops, pattern> {
+    let Inst{12} = 0b0;
+  }
+  def th : t2VSHLLt1<!strconcat(iname, "t"), suffix, sz, U, immops, pattern> {
+    let Inst{12} = 0b1;
+  }
+}
+
+// The t1 vshll encoding does not accept #8/#16 as an immediate the t2 encoding
+// does. The reason imm1_8/imm1_16 is used instead of imm1_7/imm1_15 is because
+// it will provide a more accurate error message, if the user did use #8/#16
+// with this instruction then the t2 encoding will automatically get used.
+defm t1VSHLLs8 : VSHLLt1_shift_half<"vshll", "s8", 0b0, 0b0, (ins mve_shift_imm1_7:$szimm5)>;
+defm t1VSHLLu8 : VSHLLt1_shift_half<"vshll", "u8", 0b0, 0b1, (ins mve_shift_imm1_7:$szimm5)>;
+defm t1VSHLLs16 : VSHLLt1_shift_half<"vshll", "s16", 0b1, 0b0, (ins mve_shift_imm1_15:$szimm5)>;
+defm t1VSHLLu16 : VSHLLt1_shift_half<"vshll", "u16", 0b1, 0b1, (ins mve_shift_imm1_15:$szimm5)>;
+
+class t2VRSHRN<string iname, string suffix, bit bit_12, bit bit_28,
+               dag immops, list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+def VRSHRNi16bh : t2VRSHRN<"vrshrnb", "i16", 0b0, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VRSHRNi16th : t2VRSHRN<"vrshrnt", "i16", 0b1, 0b1,(ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VRSHRNi32bh : t2VRSHRN<"vrshrnb", "i32", 0b0, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def VRSHRNi32th : t2VRSHRN<"vrshrnt", "i32", 0b1, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+def VSHRNi16bh : t2VRSHRN<"vshrnb", "i16", 0b0, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VSHRNi16th : t2VRSHRN<"vshrnt", "i16", 0b1, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VSHRNi32bh : t2VRSHRN<"vshrnb", "i32", 0b0, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def VSHRNi32th : t2VRSHRN<"vshrnt", "i32", 0b1, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+class t2VQRSHRUN<string iname, string suffix, bit bit_28, bit bit_12, dag immops,
+                 list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VQRSHRUNs16bh : t2VQRSHRUN<"vqrshrunb", "s16", 0b1, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VQRSHRUNs16th : t2VQRSHRUN<"vqrshrunt", "s16", 0b1, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VQRSHRUNs32bh : t2VQRSHRUN<"vqrshrunb", "s32", 0b1, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def VQRSHRUNs32th : t2VQRSHRUN<"vqrshrunt", "s32", 0b1, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+def VQSHRUNs16bh : t2VQRSHRUN<"vqshrunb", "s16", 0b0, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VQSHRUNs16th : t2VQRSHRUN<"vqshrunt", "s16", 0b0, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def VQSHRUNs32bh : t2VQRSHRUN<"vqshrunb", "s32", 0b0, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def VQSHRUNs32th : t2VQRSHRUN<"vqshrunt", "s32", 0b0, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+class t2VQRSHRN<string iname, string suffix, bit bit_0, bit bit_12, dag immops,
+                list<dag> pattern=[]>
+  : MVE_imm_shift<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = bit_0;
+}
+
+multiclass VQRSHRN_sign_type<string iname, bit bit_0, bit bit_12> {
+  def s16 : t2VQRSHRN<iname, "s16", bit_0, bit_12, (ins shr_imm8:$imm)> {
+    let Inst{28} = 0b0;
+    let Inst{20-19} = 0b01;
+  }
+  def u16 : t2VQRSHRN<iname, "u16", bit_0, bit_12, (ins shr_imm8:$imm)> {
+    let Inst{28} = 0b1;
+    let Inst{20-19} = 0b01;
+  }
+  def s32 : t2VQRSHRN<iname, "s32", bit_0, bit_12, (ins shr_imm16:$imm)> {
+    let Inst{28} = 0b0;
+    let Inst{20} = 0b1;
+  }
+  def u32 : t2VQRSHRN<iname, "u32", bit_0, bit_12, (ins shr_imm16:$imm)> {
+    let Inst{28} = 0b1;
+    let Inst{20} = 0b1;
+  }
+}
+
+defm VQRSHRNbh : VQRSHRN_sign_type<"vqrshrnb", 0b1, 0b0>;
+defm VQRSHRNth : VQRSHRN_sign_type<"vqrshrnt", 0b1, 0b1>;
+defm VQSHRNbh  : VQRSHRN_sign_type<"vqshrnb", 0b0, 0b0>;
+defm VQSHRNth  : VQRSHRN_sign_type<"vqshrnt", 0b0, 0b1>;
+
+// end of mve_imm_shift instructions
+
+// start of mve_bit instructions
+
+class MVE_bit_arith<dag oops, dag iops, string iname, string suffix,
+                    string ops, string cstr, list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred_r, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+def VBIC : MVE_bit_arith<(outs MQPR:$Qd),
+                         (ins MQPR:$Qn, MQPR:$Qm), "vbic", "",
+                         "$Qd, $Qn, $Qm", ""> {
+  bits<4> Qn;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b110;
+  let Inst{21-20} = 0b01;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00001;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+class t2VREV<string iname, string suffix, bits<2> size, bits<2> bit_8_7>
+  : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm), iname,
+                  suffix, "$Qd, $Qm", ""> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size{1-0};
+  let Inst{17-16} = 0b00;
+  let Inst{12-9} = 0b0000;
+  let Inst{8-7} = bit_8_7{1-0};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VREV64_8  : t2VREV<"vrev64", "8", 0b00, 0b00>;
+def VREV64_16 : t2VREV<"vrev64", "16", 0b01, 0b00>;
+def VREV64_32 : t2VREV<"vrev64", "32", 0b10, 0b00>;
+
+def VREV32_8  : t2VREV<"vrev32", "8", 0b00, 0b01>;
+def VREV32_16 : t2VREV<"vrev32", "16", 0b01, 0b01>;
+
+def VREV16_8  : t2VREV<"vrev16", "8", 0b00, 0b10>;
+
+def VMVN : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm),
+                         "vmvn", "", "$Qd, $Qm", ""> {
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-16} = 0b110000;
+  let Inst{12-6} = 0b0010111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28>
+  : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
+                  iname, "", "$Qd, $Qn, $Qm", ""> {
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{25-23} = 0b110;
+  let Inst{21-20} = bit_21_20{1-0};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00001;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+def VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
+def VORN : MVE_bit_ops<"vorn", 0b11, 0b0>;
+def MVE_VORR : MVE_bit_ops<"vorr", 0b10, 0b0>;
+def MVE_VAND : MVE_bit_ops<"vand", 0b00, 0b0>;
+
+// add ignored suffixes as aliases
+
+foreach s=["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32", "f16", "f32"] in {
+  def : MVEInstAlias<!strconcat("vbic${vp}.", s, "\t$QdSrc, $QnSrc, $QmSrc"),
+                     (VBIC MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
+  def : MVEInstAlias<!strconcat("veor${vp}.", s, "\t$QdSrc, $QnSrc, $QmSrc"),
+                     (VEOR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
+  def : MVEInstAlias<!strconcat("vorn${vp}.", s, "\t$QdSrc, $QnSrc, $QmSrc"),
+                     (VORN MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
+  def : MVEInstAlias<!strconcat("vorr${vp}.", s, "\t$QdSrc, $QnSrc, $QmSrc"),
+                     (MVE_VORR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
+  def : MVEInstAlias<!strconcat("vand${vp}.", s, "\t$QdSrc, $QnSrc, $QmSrc"),
+                     (MVE_VAND MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
+}
+
+class MVE_bit_cmode<string iname, string suffix, bits<4> cmode, dag inOps>
+  : MVE_p<(outs MQPR:$Qd), inOps, NoItinerary,
+          iname, suffix, "$Qd, $imm", vpred_n, "$Qd = $Qd_src"> {
+  bits<8> imm;
+  bits<4> Qd;
+
+  let Inst{28} = imm{7};
+  let Inst{27-23} = 0b11111;
+  let Inst{22} = Qd{3};
+  let Inst{21-19} = 0b000;
+  let Inst{18-16} = imm{6-4};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = 0b0;
+  let Inst{11-8} = cmode{3-0};
+  let Inst{7-6} = 0b01;
+  let Inst{4} = 0b1;
+  let Inst{3-0} = imm{3-0};
+}
+
+class MVE_VORR<string suffix, bits<4> cmode, dag inOps>
+  : MVE_bit_cmode<"vorr", suffix, cmode, inOps> {
+  let Inst{5} = 0b0;
+}
+
+def VORRIZ0v4i32  : MVE_VORR<"i32", 0b0001, (ins MQPR:$Qd_src, expzero00:$imm)>;
+def VORRIZ0v8i16  : MVE_VORR<"i16", 0b1001, (ins MQPR:$Qd_src, expzero00:$imm)>;
+def VORRIZ8v4i32  : MVE_VORR<"i32", 0b0011, (ins MQPR:$Qd_src, expzero08:$imm)>;
+def VORRIZ8v8i16  : MVE_VORR<"i16", 0b1011, (ins MQPR:$Qd_src, expzero08:$imm)>;
+def VORRIZ16v4i32 : MVE_VORR<"i32", 0b0101, (ins MQPR:$Qd_src, expzero16:$imm)>;
+def VORRIZ24v4i32 : MVE_VORR<"i32", 0b0111, (ins MQPR:$Qd_src, expzero24:$imm)>;
+
+def VORNIZ0v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
+                   (ins MQPR:$Qd_src, expzero00inv32:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qd)>;
+def VORNIZ0v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm",
+                   (ins MQPR:$Qd_src, expzero00inv16:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qd)>;
+def VORNIZ8v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
+                   (ins MQPR:$Qd_src, expzero08inv32:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qd)>;
+def VORNIZ8v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm",
+                   (ins MQPR:$Qd_src, expzero08inv16:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qd)>;
+def VORNIZ16v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
+                    (ins MQPR:$Qd_src, expzero16inv32:$imm, vpred_n:$vp),
+                    (outs MQPR:$Qd)>;
+def VORNIZ24v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
+                    (ins MQPR:$Qd_src, expzero24inv32:$imm, vpred_n:$vp),
+                    (outs MQPR:$Qd)>;
+
+def VMOVt1 : MVEInstAlias<"vmov${vp}\t$Qd, $Qm",
+                          (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp)>;
+
+class MVE_VBIC<string suffix, bits<4> cmode, dag inOps>
+  : MVE_bit_cmode<"vbic", suffix, cmode, inOps> {
+  let Inst{5} = 0b1;
+}
+
+def VBICIZ0v4i32  : MVE_VBIC<"i32", 0b0001, (ins MQPR:$Qd_src, expzero00:$imm)>;
+def VBICIZ0v8i16  : MVE_VBIC<"i16", 0b1001, (ins MQPR:$Qd_src, expzero00:$imm)>;
+def VBICIZ8v4i32  : MVE_VBIC<"i32", 0b0011, (ins MQPR:$Qd_src, expzero08:$imm)>;
+def VBICIZ8v8i16  : MVE_VBIC<"i16", 0b1011, (ins MQPR:$Qd_src, expzero08:$imm)>;
+def VBICIZ16v4i32 : MVE_VBIC<"i32", 0b0101, (ins MQPR:$Qd_src, expzero16:$imm)>;
+def VBICIZ24v4i32 : MVE_VBIC<"i32", 0b0111, (ins MQPR:$Qd_src, expzero24:$imm)>;
+
+def VANDIZ0v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
+                   (ins MQPR:$Qda_src, expzero00inv32:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qda)>;
+def VANDIZ0v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm",
+                   (ins MQPR:$Qda_src, expzero00inv16:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qda)>;
+def VANDIZ8v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
+                   (ins MQPR:$Qda_src, expzero08inv32:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qda)>;
+def VANDIZ8v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm",
+                   (ins MQPR:$Qda_src, expzero08inv16:$imm, vpred_n:$vp),
+                   (outs MQPR:$Qda)>;
+def VANDIZ16v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
+                    (ins MQPR:$Qda_src, expzero16inv32:$imm, vpred_n:$vp),
+                    (outs MQPR:$Qda)>;
+def VANDIZ24v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
+                    (ins MQPR:$Qda_src, expzero24inv32:$imm, vpred_n:$vp),
+                    (outs MQPR:$Qda)>;
+
+class VMOVt1<string suffix, bit U, bit bit_20, dag index, dag oops,
+             dag iops, string ops, string cstr>
+  : VMOV<oops, iops, NoItinerary, "vmov", suffix, ops, cstr, []> {
+  bits<4> Qd;
+  bits<5> Rt;
+  bits<5> Idx;
+
+  let Inst{31-24} = 0b11101110;
+  let Inst{23} = U;
+  let Inst{22-21} = Idx{3-2};
+  let Inst{20} = bit_20;
+  let Inst{19-17} = Qd{2-0};
+  let Inst{16} = Idx{4};
+  let Inst{15-12} = Rt{3-0};
+  let Inst{11-8} = 0b1011;
+  let Inst{7} = Qd{3};
+  let Inst{6-5} = Idx{1-0};
+  let Inst{4-0} = 0b10000;
+}
+
+class VMOVt1vectoreg<string suffix, bit U, dag index>
+  : VMOVt1<suffix, U, 0b1, index, (outs rGPR:$Rt),
+           !con((ins MQPR:$Qd), index), "$Rt, $Qd$Idx", "">;
+
+class VMOVt1regtovec<string suffix, bit U, dag index>
+  : VMOVt1<suffix, U, 0b0, index,(outs MQPR:$Qd),
+           !con((ins MQPR:$Qd_src, rGPR:$Rt), index), "$Qd$Idx, $Rt",
+           "$Qd = $Qd_src">;
+
+def VMOVt1vtor32 : VMOVt1vectoreg<"32", 0b0, (ins MVEVectorIndex32:$Idx)> {
+  let Inst{22} = 0b0;
+  let Inst{6-5} = 0b00;
+  let Predicates = [HasFPRegsV8_1M];
+}
+
+def VMOVt1s16 : VMOVt1vectoreg<"s16", 0b0, (ins MVEVectorIndex16:$Idx)> {
+  let Inst{22} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VMOVt1s8 : VMOVt1vectoreg<"s8", 0b0, (ins MVEVectorIndex8:$Idx)> {
+  let Inst{22} = 0b1;
+}
+
+def VMOVt1u16 : VMOVt1vectoreg<"u16", 0b1, (ins MVEVectorIndex16:$Idx)> {
+  let Inst{22} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VMOVt1u8 : VMOVt1vectoreg<"u8", 0b1, (ins MVEVectorIndex8:$Idx)> {
+  let Inst{22} = 0b1;
+}
+
+def VMOVt18 : VMOVt1regtovec<"8", 0b0, (ins MVEVectorIndex8:$Idx)> {
+  let Inst{22} = 0b1;
+}
+def VMOVt116 : VMOVt1regtovec<"16", 0b0, (ins MVEVectorIndex16:$Idx)> {
+  let Inst{22} = 0b0;
+  let Inst{5} = 0b1;
+}
+def VMOVt132 : VMOVt1regtovec<"32", 0b0, (ins MVEVectorIndex32:$Idx)> {
+  let Inst{22} = 0b0;
+  let Inst{6-5} = 0b00;
+  let Predicates = [HasFPRegsV8_1M];
+}
+
+// end of mve_bit instructions
+
+// start of MVE Integer instructions
+
+class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class VMULt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<"vmul", suffix, size, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01001;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+def VMULt1i8  : VMULt1<"i8", 0b00>;
+def VMULt1i16 : VMULt1<"i16", 0b01>;
+def VMULt1i32 : VMULt1<"i32", 0b10>;
+
+class VQDMULH<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01011;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VQDMULHt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VQDMULH<"vqdmulh", suffix, size, pattern> {
+  let Inst{28} = 0b0;
+}
+
+class VQDMULHt2<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VQDMULH<"vqrdmulh", suffix, size, pattern> {
+  let Inst{28} = 0b1;
+}
+
+def VQDMULHt1i8  : VQDMULHt1<"s8", 0b00>;
+def VQDMULHt1i16 : VQDMULHt1<"s16", 0b01>;
+def VQDMULHt1i32 : VQDMULHt1<"s32", 0b10>;
+
+def VQRDMULHt2i8  : VQDMULHt2<"s8", 0b00>;
+def VQRDMULHt2i16 : VQDMULHt2<"s16", 0b01>;
+def VQRDMULHt2i32 : VQDMULHt2<"s32", 0b10>;
+
+class VADDSUBt1<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01000;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VSUBt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VADDSUBt1<"vsub", suffix, size, pattern> {
+  let Inst{28} = 0b1;
+}
+
+class VADDt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VADDSUBt1<"vadd", suffix, size, pattern> {
+  let Inst{28} = 0b0;
+}
+
+def VSUBt1i8  : VSUBt1<"i8", 0b00>;
+def VSUBt1i16 : VSUBt1<"i16", 0b01>;
+def VSUBt1i32 : VSUBt1<"i32", 0b10>;
+
+def VADDt1i8  : VADDt1<"i8", 0b00>;
+def VADDt1i16 : VADDt1<"i16", 0b01>;
+def VADDt1i32 : VADDt1<"i32", 0b10>;
+
+class VQADDVQSUBt1<string iname, string suffix, bit U, bits<2> size,
+                  list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+class VQSUBt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VQADDVQSUBt1<"vqsub", suffix, U, size, pattern> {
+  let Inst{9} = 0b1;
+}
+
+class VQADDt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VQADDVQSUBt1<"vqadd", suffix, U, size, pattern> {
+  let Inst{9} = 0b0;
+}
+def VQSUBt1s8  : VQSUBt1<"s8", 0b0, 0b00>;
+def VQSUBt1s16 : VQSUBt1<"s16", 0b0, 0b01>;
+def VQSUBt1s32 : VQSUBt1<"s32", 0b0, 0b10>;
+def VQSUBt1u8  : VQSUBt1<"u8", 0b1, 0b00>;
+def VQSUBt1u16 : VQSUBt1<"u16", 0b1, 0b01>;
+def VQSUBt1u32 : VQSUBt1<"u32", 0b1, 0b10>;
+
+def VQADDt1s8  : VQADDt1<"s8", 0b0, 0b00>;
+def VQADDt1s16 : VQADDt1<"s16", 0b0, 0b01>;
+def VQADDt1s32 : VQADDt1<"s32", 0b0, 0b10>;
+def VQADDt1u8  : VQADDt1<"u8", 0b1, 0b00>;
+def VQADDt1u16 : VQADDt1<"u16", 0b1, 0b01>;
+def VQADDt1u32 : VQADDt1<"u32", 0b1, 0b10>;
+
+class VABDt1<string suffix, bit U, bits<2> size,
+           list<dag> pattern=[]>
+  : MVE_int<"vabd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VABDt1s8  : VABDt1<"s8", 0b0, 0b00>;
+def VABDt1s16 : VABDt1<"s16", 0b0, 0b01>;
+def VABDt1s32 : VABDt1<"s32", 0b0, 0b10>;
+def VABDt1u8  : VABDt1<"u8", 0b1, 0b00>;
+def VABDt1u16 : VABDt1<"u16", 0b1, 0b01>;
+def VABDt1u32 : VABDt1<"u32", 0b1, 0b10>;
+
+class VRHADDt1<string suffix, bit U, bits<2> size,
+               list<dag> pattern=[]>
+  : MVE_int<"vrhadd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00001;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VRHADDt1s8  : VRHADDt1<"s8", 0b0, 0b00>;
+def VRHADDt1s16 : VRHADDt1<"s16", 0b0, 0b01>;
+def VRHADDt1s32 : VRHADDt1<"s32", 0b0, 0b10>;
+def VRHADDt1u8  : VRHADDt1<"u8", 0b1, 0b00>;
+def VRHADDt1u16 : VRHADDt1<"u16", 0b1, 0b01>;
+def VRHADDt1u32 : VRHADDt1<"u32", 0b1, 0b10>;
+
+class VHADDVHSUBt1<string iname, string suffix, bit U, bits<2> size,
+                   list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VHSUBt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VHADDVHSUBt1<"vhsub", suffix, U, size, pattern> {
+
+  let Inst{9} = 0b1;
+}
+
+class VHADDt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VHADDVHSUBt1<"vhadd", suffix, U, size, pattern> {
+
+  let Inst{9} = 0b0;
+}
+
+def VHSUBt1s8  : VHSUBt1<"s8", 0b0, 0b00>;
+def VHSUBt1s16 : VHSUBt1<"s16", 0b0, 0b01>;
+def VHSUBt1s32 : VHSUBt1<"s32", 0b0, 0b10>;
+def VHSUBt1u8  : VHSUBt1<"u8", 0b1, 0b00>;
+def VHSUBt1u16 : VHSUBt1<"u16", 0b1, 0b01>;
+def VHSUBt1u32 : VHSUBt1<"u32", 0b1, 0b10>;
+
+def VHADDt1s8  : VHADDt1<"s8", 0b0, 0b00>;
+def VHADDt1s16 : VHADDt1<"s16", 0b0, 0b01>;
+def VHADDt1s32 : VHADDt1<"s32", 0b0, 0b10>;
+def VHADDt1u8  : VHADDt1<"u8", 0b1, 0b00>;
+def VHADDt1u16 : VHADDt1<"u16", 0b1, 0b01>;
+def VHADDt1u32 : VHADDt1<"u32", 0b1, 0b10>;
+
+class VDUPt1<string suffix, bit B, bit E, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins rGPR:$Rt), NoItinerary,
+          "vdup", suffix, "$Qd, $Rt", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Rt;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b101;
+  let Inst{22} = B;
+  let Inst{21-20} = 0b10;
+  let Inst{19-17} = Qd{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-12} = Rt;
+  let Inst{11-8} = 0b1011;
+  let Inst{7} = Qd{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = E;
+  let Inst{4-0} = 0b10000;
+}
+
+def VDUPt132 : VDUPt1<"32", 0b0, 0b0>;
+def VDUPt116 : VDUPt1<"16", 0b0, 0b1>;
+def VDUPt18  : VDUPt1<"8", 0b1, 0b0>;
+
+class MVEIntSingleSrc<string iname, string suffix, bits<2> size,
+                         list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{19-18} = size{1-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class VCLSVCLZt1<string iname, string suffix, bits<2> size,
+                 bit bit_7, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00100;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VCLSt1s8  : VCLSVCLZt1<"vcls", "s8", 0b00, 0b0>;
+def VCLSt1s16 : VCLSVCLZt1<"vcls", "s16", 0b01, 0b0>;
+def VCLSt1s32 : VCLSVCLZt1<"vcls", "s32", 0b10, 0b0>;
+
+def VCLZt1s8  : VCLSVCLZt1<"vclz", "i8", 0b00, 0b1>;
+def VCLZt1s16 : VCLSVCLZt1<"vclz", "i16", 0b01, 0b1>;
+def VCLZt1s32 : VCLSVCLZt1<"vclz", "i32", 0b10, 0b1>;
+
+class VNEGVABSt1<string iname, string suffix, bits<2> size, bit bit_7,
+             list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b01;
+  let Inst{12-8} = 0b00011;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VNEGt1s8  : VNEGVABSt1<"vneg", "s8", 0b00, 0b1>;
+def VNEGt1s16 : VNEGVABSt1<"vneg", "s16", 0b01, 0b1>;
+def VNEGt1s32 : VNEGVABSt1<"vneg", "s32", 0b10, 0b1>;
+
+def VABSt1s8  : VNEGVABSt1<"vabs", "s8", 0b00, 0b0>;
+def VABSt1s16 : VNEGVABSt1<"vabs", "s16", 0b01, 0b0>;
+def VABSt1s32 : VNEGVABSt1<"vabs", "s32", 0b10, 0b0>;
+
+class VQNEGVQABSt1<string iname, string suffix, bits<2> size,
+                   bit bit_7, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00111;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VQNEGt1s8  : VQNEGVQABSt1<"vqneg", "s8", 0b00, 0b1>;
+def VQNEGt1s16 : VQNEGVQABSt1<"vqneg", "s16", 0b01, 0b1>;
+def VQNEGt1s32 : VQNEGVQABSt1<"vqneg", "s32", 0b10, 0b1>;
+
+def VQABSt1s8  : VQNEGVQABSt1<"vqabs", "s8", 0b00, 0b0>;
+def VQABSt1s16 : VQNEGVQABSt1<"vqabs", "s16", 0b01, 0b0>;
+def VQABSt1s32 : VQNEGVQABSt1<"vqabs", "s32", 0b10, 0b0>;
+
+class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
+                  dag iops, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
+          vpred_r, "", pattern> {
+  bits<13> imm;
+  bits<4> Qd;
+
+  let Inst{28} = imm{7};
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-19} = 0b000;
+  let Inst{18-16} = imm{6-4};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = 0b0;
+  let Inst{11-8} = cmode{3-0};
+  let Inst{7-6} = 0b01;
+  let Inst{5} = op;
+  let Inst{4} = 0b1;
+  let Inst{3-0} = imm{3-0};
+
+  let DecoderMethod = "DecodeMveModImmInstruction";
+}
+
+let isReMaterializable = 1 in {
+let isAsCheapAsAMove = 1 in {
+def VMOVimmi8  : MVE_mod_imm<"vmov", "i8",  {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
+def VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def VMOVimmi32 : MVE_mod_imm<"vmov", "i32", {?,?,?,?}, 0b0, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+def VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm)>;
+def VMOVimmf32 : MVE_mod_imm<"vmov", "f32", {1,1,1,1}, 0b0, (ins nImmVMOVF32:$imm)>;
+} // let isAsCheapAsAMove = 1
+
+def VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+} // let isReMaterializable = 1
+
+// end of MVE Integer instructions
+
+// start of MVE Floating Point instructions
+
+class MVE_float<string iname, string suffix, dag oops, dag iops, string ops,
+                vpred_ops vpred, string cstr, list<dag> pattern=[]>
+  : MVE_f<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qm;
+
+  let Inst{12} = 0b0;
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+class VRINTt1<string rmode, bits<3> op, string suffix, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_float<!strconcat("vrint", rmode), suffix, (outs MQPR:$Qd),
+              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b10;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-10} = 0b01;
+  let Inst{9-7} = op{2-0};
+  let Inst{4} = 0b0;
+
+}
+
+multiclass VRINTt1_ops<string suffix, bits<2> size, list<dag> pattern=[]> {
+  def N : VRINTt1<"n", 0b000, suffix, size, pattern>;
+  def X : VRINTt1<"x", 0b001, suffix, size, pattern>;
+  def A : VRINTt1<"a", 0b010, suffix, size, pattern>;
+  def Z : VRINTt1<"z", 0b011, suffix, size, pattern>;
+  def M : VRINTt1<"m", 0b101, suffix, size, pattern>;
+  def P : VRINTt1<"p", 0b111, suffix, size, pattern>;
+}
+
+defm VRINT_f16 : VRINTt1_ops<"f16", 0b01>;
+defm VRINT_f32 : VRINTt1_ops<"f32", 0b10>;
+
+class MVEFloatArithNeon<string iname, string suffix, bit size,
+                           dag oops, dag iops, string ops,
+                           vpred_ops vpred, string cstr, list<dag> pattern=[]>
+  : MVE_float<iname, suffix, oops, iops, ops, vpred, cstr, pattern> {
+  let Inst{20} = size;
+  let Inst{16} = 0b0;
+}
+
+class VMULfpt1<string suffix, bit size, list<dag> pattern=[]>
+  : MVEFloatArithNeon<"vmul", suffix, size, (outs MQPR:$Qd),
+                      (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm", vpred_r, "",
+                      pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b110;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b0;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-8} = 0b01101;
+  let Inst{7} = Qn{3};
+  let Inst{4} = 0b1;
+}
+
+def VMULfpt1f32 : VMULfpt1<"f32", 0b0>;
+def VMULfpt1f16 : VMULfpt1<"f16", 0b1>;
+
+class VCMLAt1<string suffix, bit size, list<dag> pattern=[]>
+  : MVEFloatArithNeon<"vcmla", suffix, size, (outs MQPR:$Qd),
+                         (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm, vcmla_rot_imm:$rot),
+                         "$Qd, $Qn, $Qm, $rot", vpred_n, "$Qd = $Qd_src", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<2> rot;
+
+  let Inst{28} = 0b1;
+  let Inst{25} = 0b0;
+  let Inst{24-23} = rot;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b1;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-8} = 0b01000;
+  let Inst{7} = Qn{3};
+  let Inst{4} = 0b0;
+}
+
+def VCMLAt1f16 : VCMLAt1<"f16", 0b0>;
+def VCMLAt1f32 : VCMLAt1<"f32", 0b1>;
+
+class VADDVSUBVFMAfp<string iname, string suffix, bit size, bit bit_4,
+                     bit bit_8, bit bit_21, dag iops=(ins),
+                     vpred_ops vpred=vpred_r, string cstr="",
+                     list<dag> pattern=[]>
+  : MVEFloatArithNeon<iname, suffix, size, (outs MQPR:$Qd),
+                      !con(iops, (ins MQPR:$Qn, MQPR:$Qm)), "$Qd, $Qn, $Qm",
+                      vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b110;
+  let Inst{22} = Qd{3};
+  let Inst{21} = bit_21;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b110;
+  let Inst{8} = bit_8;
+  let Inst{7} = Qn{3};
+  let Inst{4} = bit_4;
+}
+
+def VFMAt1f32 : VADDVSUBVFMAfp<"vfma", "f32", 0b0, 0b1, 0b0, 0b0,
+                               (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
+def VFMAt1f16 : VADDVSUBVFMAfp<"vfma", "f16", 0b1, 0b1, 0b0, 0b0,
+                               (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
+
+def VFMSt2f32 : VADDVSUBVFMAfp<"vfms", "f32", 0b0, 0b1, 0b0, 0b1,
+                               (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
+def VFMSt2f16 : VADDVSUBVFMAfp<"vfms", "f16", 0b1, 0b1, 0b0, 0b1,
+                               (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
+
+def VADDt1f32 : VADDVSUBVFMAfp<"vadd", "f32", 0b0, 0b0, 0b1, 0b0>;
+def VADDt1f16 : VADDVSUBVFMAfp<"vadd", "f16", 0b1, 0b0, 0b1, 0b0>;
+
+def VSUBt1f32 : VADDVSUBVFMAfp<"vsub", "f32", 0b0, 0b0, 0b1, 0b1>;
+def VSUBt1f16 : VADDVSUBVFMAfp<"vsub", "f16", 0b1, 0b0, 0b1, 0b1>;
+
+class VCADDt1<string suffix, bit size, list<dag> pattern=[]>
+  : MVEFloatArithNeon<"vcadd", suffix, size, (outs MQPR:$Qd),
+                         (ins MQPR:$Qn, MQPR:$Qm, vcadd_rot_imm:$rot),
+                         "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bit rot;
+
+  let Inst{28} = 0b1;
+  let Inst{25} = 0b0;
+  let Inst{24} = rot;
+  let Inst{23} = 0b1;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b0;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-8} = 0b01000;
+  let Inst{7} = Qn{3};
+  let Inst{4} = 0b0;
+}
+
+def VCADDt1f16 : VCADDt1<"f16", 0b0>;
+def VCADDt1f32 : VCADDt1<"f32", 0b1>;
+
+class VABDt1fp<string suffix, bit size>
+  : MVE_float<"vabd", suffix, (outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
+              "$Qd, $Qn, $Qm", vpred_r, ""> {
+  bits<4> Qd;
+  bits<4> Qn;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b110;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b1;
+  let Inst{20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-8} = 0b1101;
+  let Inst{7} = Qn{3};
+  let Inst{4} = 0b0;
+}
+
+def VABDt1f32 : VABDt1fp<"f32", 0b0>;
+def VABDt1f16 : VABDt1fp<"f16", 0b1>;
+
+class VCVTt1fp<string suffix, bit fsi, bit U, bit op, list<dag> pattern=[]>
+  : MVE_float<"vcvt", suffix, (outs MQPR:$Qd), (ins MQPR:$Qm,
+              neon_vcvt_imm32:$imm6), "$Qd, $Qm, $imm6", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<6> imm6;
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b1;
+  let Inst{19-16} = imm6{3-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-10} = 0b11;
+  let Inst{9} = fsi;
+  let Inst{8} = op;
+  let Inst{7} = 0b0;
+  let Inst{4} = 0b1;
+
+  let DecoderMethod = "DecodeMVEVCVTt1fp";
+}
+
+class VCVTt1f32<string suffix, bit U, bit op> : VCVTt1fp<suffix, 0b1, U, op> {
+  let Inst{20} = imm6{4};
+}
+class VCVTt1f16<string suffix, bit U, bit op> : VCVTt1fp<suffix, 0b0, U, op> {
+  let Inst{20} = 0b1;
+}
+
+def VCVTt1f16s16 : VCVTt1f16<"f16.s16", 0b0, 0b0>;
+def VCVTt1s16f16 : VCVTt1f16<"s16.f16", 0b0, 0b1>;
+def VCVTt1f16u16 : VCVTt1f16<"f16.u16", 0b1, 0b0>;
+def VCVTt1u16f16 : VCVTt1f16<"u16.f16", 0b1, 0b1>;
+def VCVTt1f32s32 : VCVTt1f32<"f32.s32", 0b0, 0b0>;
+def VCVTt1s32f32 : VCVTt1f32<"s32.f32", 0b0, 0b1>;
+def VCVTt1f32u32 : VCVTt1f32<"f32.u32", 0b1, 0b0>;
+def VCVTt1u32f32 : VCVTt1f32<"u32.f32", 0b1, 0b1>;
+
+class VCVTt1rfp<string suffix, bits<2> size, bit op, string anpm,
+                bits<2> rm, list<dag> pattern=[]>
+  : MVE_float<!strconcat("vcvt", anpm), suffix, (outs MQPR:$Qd),
+              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-10} = 0b000;
+  let Inst{9-8} = rm;
+  let Inst{7} = op;
+  let Inst{4} = 0b0;
+}
+
+multiclass VCVTt1rfp_anpm_multi<string suffix, bits<2> size, bit op,
+                                list<dag> pattern=[]> {
+  def A : VCVTt1rfp<suffix, size, op, "a", 0b00>;
+  def N : VCVTt1rfp<suffix, size, op, "n", 0b01>;
+  def P : VCVTt1rfp<suffix, size, op, "p", 0b10>;
+  def M : VCVTt1rfp<suffix, size, op, "m", 0b11>;
+}
+
+defm VCVTt1rfps16f16 : VCVTt1rfp_anpm_multi<"s16.f16", 0b01, 0b0>;
+defm VCVTt1rfpu16f16 : VCVTt1rfp_anpm_multi<"u16.f16", 0b01, 0b1>;
+defm VCVTt1rfps32f32 : VCVTt1rfp_anpm_multi<"s32.f32", 0b10, 0b0>;
+defm VCVTt1rfpu32f32 : VCVTt1rfp_anpm_multi<"u32.f32", 0b10, 0b1>;
+
+class VCVTt1fpi<string suffix, bits<2> size, bits<2> op, list<dag> pattern=[]>
+  : MVE_float<"vcvt", suffix, (outs MQPR:$Qd),
+              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0011;
+  let Inst{8-7} = op;
+  let Inst{4} = 0b0;
+}
+
+def VCVTt1fpif16s16 : VCVTt1fpi<"f16.s16", 0b01, 0b00>;
+def VCVTt1fpif16u16 : VCVTt1fpi<"f16.u16", 0b01, 0b01>;
+def VCVTt1fpis16f16 : VCVTt1fpi<"s16.f16", 0b01, 0b10>;
+def VCVTt1fpiu16f16 : VCVTt1fpi<"u16.f16", 0b01, 0b11>;
+def VCVTt1fpif32s32 : VCVTt1fpi<"f32.s32", 0b10, 0b00>;
+def VCVTt1fpif32u32 : VCVTt1fpi<"f32.u32", 0b10, 0b01>;
+def VCVTt1fpis32f32 : VCVTt1fpi<"s32.f32", 0b10, 0b10>;
+def VCVTt1fpiu32f32 : VCVTt1fpi<"u32.f32", 0b10, 0b11>;
+
+class VNEGVABSt1fp<string iname, string suffix, bits<2> size, bit bit_7,
+                   list<dag> pattern=[]>
+  : MVE_float<iname, suffix, (outs MQPR:$Qd),
+              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b01;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-8} = 0b0111;
+  let Inst{7} = bit_7;
+  let Inst{4} = 0b0;
+}
+
+def VNEGt1f16 : VNEGVABSt1fp<"vneg", "f16", 0b01, 0b1>;
+def VNEGt1f32 : VNEGVABSt1fp<"vneg", "f32", 0b10, 0b1>;
+
+def VABSt1f16 : VNEGVABSt1fp<"vabs", "f16", 0b01, 0b0>;
+def VABSt1f32 : VNEGVABSt1fp<"vabs", "f32", 0b10, 0b0>;
+
+// end of MVE Floating Point instructions
+
+// start of mve_shift instructions
+
+class MVE_shift_vec<string iname, string suffix, bit U, bits<2> size,
+                    dag oops, dag iops, string ops, string cstr,
+                    list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix,
+          ops, vpred_r, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+  bits<4> Qn;
+
+  let Inst{28} = U;
+  let Inst{25-24} = 0b11;
+  let Inst{23} = 0b0;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0010;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+class MVE_shift_helper<string iname, string suffix, bit U,
+                       bits<2> size, bit bit_4, bit bit_8>
+  : MVE_shift_vec<iname, suffix, U, size,
+                  (outs MQPR:$Qd), (ins MQPR:$Qm, MQPR:$Qn),
+                  "$Qd, $Qm, $Qn", ""> {
+
+  let Inst{8} = bit_8;
+  let Inst{4} = bit_4;
+}
+
+multiclass mve_shift_vec_multi<string iname, bit bit_4, bit bit_8> {
+  def s8  : MVE_shift_helper<iname, "s8", 0b0, 0b00, bit_4, bit_8>;
+  def s16 : MVE_shift_helper<iname, "s16", 0b0, 0b01, bit_4, bit_8>;
+  def s32 : MVE_shift_helper<iname, "s32", 0b0, 0b10, bit_4, bit_8>;
+  def u8  : MVE_shift_helper<iname, "u8", 0b1, 0b00, bit_4, bit_8>;
+  def u16 : MVE_shift_helper<iname, "u16", 0b1, 0b01, bit_4, bit_8>;
+  def u32 : MVE_shift_helper<iname, "u32", 0b1, 0b10, bit_4, bit_8>;
+}
+
+defm VSHLt3   : mve_shift_vec_multi<"vshl", 0b0, 0b0>;
+defm VQSHLt4  : mve_shift_vec_multi<"vqshl", 0b1, 0b0>;
+defm VQRSHLt1 : mve_shift_vec_multi<"vqrshl", 0b1, 0b1>;
+defm VRSHLt1  : mve_shift_vec_multi<"vrshl", 0b0, 0b1>;
+
+class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
+                         string ops, vpred_ops vpred, string cstr,
+                         list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{23} = 0b1;
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-11} = 0b00;
+  let Inst{7-6} = 0b01;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b1;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+class VSRIVSLIt1<string iname, string suffix, bit bit_8, dag imm>
+  : MVE_shift_with_imm<iname, suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qd_src, MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_n, "$Qd = $Qd_src"> {
+  bits<6> imm;
+  let Inst{28} = 0b1;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-9} = 0b10;
+  let Inst{8} = bit_8;
+}
+
+def VSRIt18 : VSRIVSLIt1<"vsri", "8", 0b0, (ins shr_imm8:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def VSRIt116 : VSRIVSLIt1<"vsri", "16", 0b0, (ins shr_imm16:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def VSRIt132 : VSRIVSLIt1<"vsri", "32", 0b0,(ins shr_imm32:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+def VSLIt18 : VSRIVSLIt1<"vsli", "8", 0b1, (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def VSLIt116 : VSRIVSLIt1<"vsli", "16", 0b1, (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def VSLIt132 : VSRIVSLIt1<"vsli", "32", 0b1,(ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+class VQSHLt2<string suffix, dag imm>
+  : MVE_shift_with_imm<"vqshl", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b111;
+}
+
+def VSLIt2s8 : VQSHLt2<"s8", (ins imm0_7:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def VSLIt2u8 : VQSHLt2<"u8", (ins imm0_7:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def VSLIt2s16 : VQSHLt2<"s16", (ins imm0_15:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def VSLIt2u16 : VQSHLt2<"u16", (ins imm0_15:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def VSLIt2s32 : VQSHLt2<"s32", (ins imm0_31:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def VSLIt2u32 : VQSHLt2<"u32", (ins imm0_31:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class VQSHLUt3<string suffix, dag imm>
+  : MVE_shift_with_imm<"vqshlu", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{28} = 0b1;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b110;
+}
+
+def VQSHLUt3s8 : VQSHLUt3<"s8", (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def VQSHLUt3s16 : VQSHLUt3<"s16", (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def VQSHLUt3s32 : VQSHLUt3<"s32", (ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+class VRSHRt1<string suffix, dag imm>
+  : MVE_shift_with_imm<"vrshr", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b010;
+}
+
+def VRSHRt1s8 : VRSHRt1<"s8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def VRSHRt1u8 : VRSHRt1<"u8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def VRSHRt1s16 : VRSHRt1<"s16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def VRSHRt1u16 : VRSHRt1<"u16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def VRSHRt1s32 : VRSHRt1<"s32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def VRSHRt1u32 : VRSHRt1<"u32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class VSHRt1<string suffix, dag imm>
+  : MVE_shift_with_imm<"vshr", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b000;
+}
+
+def VSHRt1s8 : VSHRt1<"s8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def VSHRt1u8 : VSHRt1<"u8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def VSHRt1s16 : VSHRt1<"s16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def VSHRt1u16 : VSHRt1<"u16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def VSHRt1s32 : VSHRt1<"s32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def VSHRt1u32 : VSHRt1<"u32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class VSHLt1<string suffix, dag imm>
+  : MVE_shift_with_imm<"vshl", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b101;
+}
+
+def VSHLt1i8 : VSHLt1<"i8", (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def VSHLt1i16 : VSHLt1<"i16", (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def VSHLt1i32 : VSHLt1<"i32", (ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+// end of mve_shift instructions
+
+def VPSELt1 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+                    "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
+  bits<4> Qn;
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0111;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+// start of mve_qDest_qSrc
+
+class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
+                     string ops, vpred_ops vpred, string cstr,
+                     list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix,
+          ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b111;
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+}
+
+foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32", "f16",
+                  "f32"] in {
+  def : MVEInstAlias<!strconcat("vpsel", "${vp}.", suffix, "\t$Qd, $Qn, $Qm"),
+                     (VPSELt1 MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+}
+
+class VCMPt1<string suffix, bit bit_28, bits<2> bits_21_20, dag iops,
+             list<dag> pattern=[]>
+  : MVE_p<(outs VCCR:$P0), iops, NoItinerary, "vcmp", suffix,
+          "$fc, $Qn, $Qm", vpred_n, "", pattern> {
+  bits<3> fc;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-22} = 0b1000;
+  let Inst{21-20} = bits_21_20;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16-13} = 0b1000;
+  let Inst{12} = fc{2};
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = fc{0};
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = fc{1};
+
+  let Constraints = "";
+  let DecoderMethod = "DecodeMveVCMP";
+}
+
+let Predicates = [HasMVEFloat] in
+  class VCMPt1f<string suffix, bit size>
+    : VCMPt1<suffix, size, 0b11, (ins MQPR:$Qn, MQPR:$Qm, pred_basic_fp:$fc)>;
+
+def VCMPt1f32 : VCMPt1f<"f32", 0b0>;
+def VCMPt1f16 : VCMPt1f<"f16", 0b1>;
+
+class VCMPt1i<string suffix, bits<2> size>
+  : VCMPt1<suffix, 0b1, size, (ins MQPR:$Qn, MQPR:$Qm, pred_basic_i:$fc)> {
+  let Inst{12} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VCMPt1i8  : VCMPt1i<"i8", 0b00>;
+def VCMPt1i16 : VCMPt1i<"i16", 0b01>;
+def VCMPt1i32 : VCMPt1i<"i32", 0b10>;
+
+class VCMPt1u<string suffix, bits<2> size>
+  : VCMPt1<suffix, 0b1, size, (ins MQPR:$Qn, MQPR:$Qm, pred_basic_u:$fc)> {
+  let Inst{12} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+def VCMPt1u8  : VCMPt1u<"u8", 0b00>;
+def VCMPt1u16 : VCMPt1u<"u16", 0b01>;
+def VCMPt1u32 : VCMPt1u<"u32", 0b10>;
+
+class VCMPt1s<string suffix, bits<2> size>
+  : VCMPt1<suffix, 0b1, size, (ins MQPR:$Qn, MQPR:$Qm, pred_basic_s:$fc)> {
+  let Inst{12} = 0b1;
+}
+
+def VCMPt1s8  : VCMPt1s<"s8", 0b00>;
+def VCMPt1s16 : VCMPt1s<"s16", 0b01>;
+def VCMPt1s32 : VCMPt1s<"s32", 0b10>;
+
+class VCMPt2<string suffix, bit bit_28, bits<2> bits_21_20, dag iops,
+             list<dag> pattern=[]>
+  : MVE_p<(outs VCCR:$P0), iops, NoItinerary, "vcmp", suffix,
+          "$fc, $Qn, $Rm", vpred_n, "", pattern> {
+  bits<3> fc;
+  bits<4> Qn;
+  bits<5> Rm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-22} = 0b1000;
+  let Inst{21-20} = bits_21_20;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16-13} = 0b1000;
+  let Inst{12} = fc{2};
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = fc{0};
+  let Inst{6} = 0b1;
+  let Inst{5} = fc{1};
+  let Inst{4} = 0b0;
+  let Inst{3-0} = Rm{3-0};
+
+  let Constraints = "";
+  let DecoderMethod = "DecodeMveVCMP";
+}
+
+let Predicates = [HasMVEFloat] in
+  class VCMPt2f<string suffix, bit size>
+    : VCMPt2<suffix, size, 0b11,
+             (ins MQPR:$Qn, GPRwithZR:$Rm, pred_basic_fp:$fc)>;
+
+def VCMPt2f32 : VCMPt2f<"f32", 0b0>;
+def VCMPt2f16 : VCMPt2f<"f16", 0b1>;
+
+class VCMPt2i<string suffix, bits<2> size>
+  : VCMPt2<suffix, 0b1, size, (ins MQPR:$Qn, GPRwithZR:$Rm, pred_basic_i:$fc)> {
+  let Inst{12} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def VCMPt2i8  : VCMPt2i<"i8", 0b00>;
+def VCMPt2i16 : VCMPt2i<"i16", 0b01>;
+def VCMPt2i32 : VCMPt2i<"i32", 0b10>;
+
+class VCMPt2u<string suffix, bits<2> size>
+  : VCMPt2<suffix, 0b1, size, (ins MQPR:$Qn, GPRwithZR:$Rm, pred_basic_u:$fc)> {
+  let Inst{12} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VCMPt2u8  : VCMPt2u<"u8", 0b00>;
+def VCMPt2u16 : VCMPt2u<"u16", 0b01>;
+def VCMPt2u32 : VCMPt2u<"u32", 0b10>;
+
+class VCMPt2s<string suffix, bits<2> size>
+  : VCMPt2<suffix, 0b1, size, (ins MQPR:$Qn, GPRwithZR:$Rm, pred_basic_s:$fc)> {
+  let Inst{12} = 0b1;
+}
+
+def VCMPt2s8  : VCMPt2s<"s8", 0b00>;
+def VCMPt2s16 : VCMPt2s<"s16", 0b01>;
+def VCMPt2s32 : VCMPt2s<"s32", 0b10>;
+
+
+class VQDMLADH<string iname, bit exch, string suffix, bits<2> size,
+               bit bit_0, bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = exch;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = bit_0;
+}
+
+def VQDMLADHt1xs8  : VQDMLADH<"vqdmladhx", 0b1, "s8", 0b00, 0b0, 0b0>;
+def VQDMLADHt1xs16 : VQDMLADH<"vqdmladhx", 0b1, "s16", 0b01, 0b0, 0b0>;
+def VQDMLADHt1xs32 : VQDMLADH<"vqdmladhx", 0b1, "s32", 0b10, 0b0, 0b0>;
+
+def VQDMLADHt1s8  : VQDMLADH<"vqdmladh", 0b0, "s8", 0b00, 0b0, 0b0>;
+def VQDMLADHt1s16 : VQDMLADH<"vqdmladh", 0b0, "s16", 0b01, 0b0, 0b0>;
+def VQDMLADHt1s32 : VQDMLADH<"vqdmladh", 0b0, "s32", 0b10, 0b0, 0b0>;
+
+def VQDMLADHt2xs8  : VQDMLADH<"vqrdmladhx", 0b1, "s8", 0b00, 0b1, 0b0>;
+def VQDMLADHt2xs16 : VQDMLADH<"vqrdmladhx", 0b1, "s16", 0b01, 0b1, 0b0>;
+def VQDMLADHt2xs32 : VQDMLADH<"vqrdmladhx", 0b1, "s32", 0b10, 0b1, 0b0>;
+
+def VQDMLADHt2s8  : VQDMLADH<"vqrdmladh", 0b0, "s8", 0b00, 0b1, 0b0>;
+def VQDMLADHt2s16 : VQDMLADH<"vqrdmladh", 0b0, "s16", 0b01, 0b1, 0b0>;
+def VQDMLADHt2s32 : VQDMLADH<"vqrdmladh", 0b0, "s32", 0b10, 0b1, 0b0>;
+
+def VQDMLSDHt1xs8  : VQDMLADH<"vqdmlsdhx", 0b1, "s8", 0b00, 0b0, 0b1>;
+def VQDMLSDHt1xs16 : VQDMLADH<"vqdmlsdhx", 0b1, "s16", 0b01, 0b0, 0b1>;
+def VQDMLSDHt1xs32 : VQDMLADH<"vqdmlsdhx", 0b1, "s32", 0b10, 0b0, 0b1>;
+
+def VQDMLSDHt1s8  : VQDMLADH<"vqdmlsdh", 0b0, "s8", 0b00, 0b0, 0b1>;
+def VQDMLSDHt1s16 : VQDMLADH<"vqdmlsdh", 0b0, "s16", 0b01, 0b0, 0b1>;
+def VQDMLSDHt1s32 : VQDMLADH<"vqdmlsdh", 0b0, "s32", 0b10, 0b0, 0b1>;
+
+def VQDMLSDHt2xs8  : VQDMLADH<"vqrdmlsdhx", 0b1, "s8", 0b00, 0b1, 0b1>;
+def VQDMLSDHt2xs16 : VQDMLADH<"vqrdmlsdhx", 0b1, "s16", 0b01, 0b1, 0b1>;
+def VQDMLSDHt2xs32 : VQDMLADH<"vqrdmlsdhx", 0b1, "s32", 0b10, 0b1, 0b1>;
+
+def VQDMLSDHt2s8  : VQDMLADH<"vqrdmlsdh", 0b0, "s8", 0b00, 0b1, 0b1>;
+def VQDMLSDHt2s16 : VQDMLADH<"vqrdmlsdh", 0b0, "s16", 0b01, 0b1, 0b1>;
+def VQDMLSDHt2s32 : VQDMLADH<"vqrdmlsdh", 0b0, "s32", 0b10, 0b1, 0b1>;
+
+class VCMUL<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm, vcmla_rot_imm:$rot),
+                   "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
+  bits<4> Qn;
+  bits<2> rot;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = rot{1};
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = rot{0};
+}
+
+let Predicates = [HasMVEFloat] in {
+  def VCMULt1f16 : VCMUL<"vcmul", "f16", 0b0>;
+  def VCMULt1f32 : VCMUL<"vcmul", "f32", 0b1>;
+}
+
+class VMULL<string iname, string suffix, bit U, bits<2> size, bit T,
+            list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = T;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+multiclass VMULL_half_multi<string iname, string suffix, bit U, bits<2> size> {
+  def bh : VMULL<!strconcat(iname, "b"), suffix, U, size, 0b0>;
+  def th : VMULL<!strconcat(iname, "t"), suffix, U, size, 0b1>;
+}
+
+defm VMULLt1s8  : VMULL_half_multi<"vmull", "s8", 0b0, 0b00>;
+defm VMULLt1s16 : VMULL_half_multi<"vmull", "s16", 0b0, 0b01>;
+defm VMULLt1s32 : VMULL_half_multi<"vmull", "s32", 0b0, 0b10>;
+defm VMULLt1u8  : VMULL_half_multi<"vmull", "u8", 0b1, 0b00>;
+defm VMULLt1u16 : VMULL_half_multi<"vmull", "u16", 0b1, 0b01>;
+defm VMULLt1u32 : VMULL_half_multi<"vmull", "u32", 0b1, 0b10>;
+
+class VMULLp<string iname, string suffix, bit size, bit T,
+             list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                  (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                  vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = T;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+multiclass VMULLp_half_multi<string iname, string suffix, bit size> {
+  def bh : VMULLp<!strconcat(iname, "b"), suffix, size, 0b0>;
+  def th : VMULLp<!strconcat(iname, "t"), suffix, size, 0b1>;
+}
+
+defm VMULLt1p8  : VMULLp_half_multi<"vmull", "p8", 0b0>;
+defm VMULLt1p16 : VMULLp_half_multi<"vmull", "p16", 0b1>;
+
+class VMULH<string iname, string suffix, bit U, bits<2> size,
+            bit bit_12, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b0;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b1;
+}
+
+def VMULHt1s8  : VMULH<"vmulh", "s8", 0b0, 0b00, 0b0>;
+def VMULHt1s16 : VMULH<"vmulh", "s16", 0b0, 0b01, 0b0>;
+def VMULHt1s32 : VMULH<"vmulh", "s32", 0b0, 0b10, 0b0>;
+def VMULHt1u8  : VMULH<"vmulh", "u8", 0b1, 0b00, 0b0>;
+def VMULHt1u16 : VMULH<"vmulh", "u16", 0b1, 0b01, 0b0>;
+def VMULHt1u32 : VMULH<"vmulh", "u32", 0b1, 0b10, 0b0>;
+
+def VRMULHt2s8  : VMULH<"vrmulh", "s8", 0b0, 0b00, 0b1>;
+def VRMULHt2s16 : VMULH<"vrmulh", "s16", 0b0, 0b01, 0b1>;
+def VRMULHt2s32 : VMULH<"vrmulh", "s32", 0b0, 0b10, 0b1>;
+def VRMULHt2u8  : VMULH<"vrmulh", "u8", 0b1, 0b00, 0b1>;
+def VRMULHt2u16 : VMULH<"vrmulh", "u16", 0b1, 0b01, 0b1>;
+def VRMULHt2u32 : VMULH<"vrmulh", "u32", 0b1, 0b10, 0b1>;
+
+class VQMOVN<string iname, string suffix, bit U, bits<2> size,
+             bit T, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
+                   vpred_n, "$Qd = $Qd_src", pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b00;
+  let Inst{0} = 0b1;
+}
+
+multiclass VQMOVN_half_multi<string suffix, bit U, bits<2> size> {
+  def bh : VQMOVN<!strconcat("vqmovn", "b"), suffix, U, size, 0b0>;
+  def th : VQMOVN<!strconcat("vqmovn", "t"), suffix, U, size, 0b1>;
+}
+
+defm VQMOVNt1s16 : VQMOVN_half_multi<"s16", 0b0, 0b00>;
+defm VQMOVNt1s32 : VQMOVN_half_multi<"s32", 0b0, 0b01>;
+defm VQMOVNt1u16 : VQMOVN_half_multi<"u16", 0b1, 0b00>;
+defm VQMOVNt1u32 : VQMOVN_half_multi<"u32", 0b1, 0b01>;
+
+class VCVTt1sh<string iname, string suffix, bit op, bit T,
+               list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+                   "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
+  let Inst{28} = op;
+  let Inst{21-16} = 0b111111;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b00;
+  let Inst{0} = 0b1;
+
+  let Predicates = [HasMVEFloat];
+}
+
+multiclass VCVTt1sh_half_multi<string suffix, bit op> {
+  def bh : VCVTt1sh<!strconcat("vcvt", "b"), suffix, op, 0b0>;
+  def th : VCVTt1sh<!strconcat("vcvt", "t"), suffix, op, 0b1>;
+}
+
+defm VCVTt1shf16f32 : VCVTt1sh_half_multi<"f16.f32", 0b0>;
+defm VCVTt1shf32f16 : VCVTt1sh_half_multi<"f32.f16", 0b1>;
+
+class VQMOV<string iname, string suffix, bits<2> size, bit T,
+            bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+                   "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
+  let Inst{28} = bit_28;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b01;
+  let Inst{12} = T;
+  let Inst{8-7} = 0b01;
+  let Inst{0} = 0b1;
+}
+
+multiclass VQMOV_half_multi<string iname, string suffix, bits<2> size,
+                            bit bit_28> {
+  def bh : VQMOV<!strconcat(iname, "b"), suffix, size, 0b0, bit_28>;
+  def th : VQMOV<!strconcat(iname, "t"), suffix, size, 0b1, bit_28>;
+}
+
+defm VQMOVUNs16 : VQMOV_half_multi<"vqmovun", "s16", 0b00, 0b0>;
+defm VQMOVUNs32 : VQMOV_half_multi<"vqmovun", "s32", 0b01, 0b0>;
+
+defm VMOVNi16 : VQMOV_half_multi<"vmovn", "i16", 0b00, 0b1>;
+defm VMOVNi32 : VQMOV_half_multi<"vmovn", "i32", 0b01, 0b1>;
+
+class VMAXAVMINAt2<string iname, string suffix, bits<2> size,
+                   bit bit_12, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17-16} = 0b11;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111010;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def VMAXAt2s8  : VMAXAVMINAt2<"vmaxa", "s8", 0b00, 0b0>;
+def VMAXAt2s16 : VMAXAVMINAt2<"vmaxa", "s16", 0b01, 0b0>;
+def VMAXAt2s32 : VMAXAVMINAt2<"vmaxa", "s32", 0b10, 0b0>;
+
+def VMINAt2s8  : VMAXAVMINAt2<"vmina", "s8", 0b00, 0b1>;
+def VMINAt2s16 : VMAXAVMINAt2<"vmina", "s16", 0b01, 0b1>;
+def VMINAt2s32 : VMAXAVMINAt2<"vmina", "s32", 0b10, 0b1>;
+
+class VMAXNMVMINNMt2<string iname, string suffix, bit size, bit bit_12,
+                     list<dag> pattern=[]>
+  : MVE_f<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
+          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = size;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-16} = 0b111111;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111010;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+def VMAXNMAt2f32 : VMAXNMVMINNMt2<"vmaxnma", "f32", 0b0, 0b0>;
+def VMAXNMAt2f16 : VMAXNMVMINNMt2<"vmaxnma", "f16", 0b1, 0b0>;
+
+def VMINNMAt2f32 : VMAXNMVMINNMt2<"vminnma", "f32", 0b0, 0b1>;
+def VMINNMAt2f16 : VMAXNMVMINNMt2<"vminnma", "f16", 0b1, 0b1>;
+
+class VHCADDt1<string iname, string suffix, bits<2> size, bit bit_28,
+               list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm, vcadd_rot_imm:$rot),
+                   "$Qd, $Qn, $Qm, $rot", vpred_r, "",
+          pattern> {
+  bits<4> Qn;
+  bit rot;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = rot;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+}
+
+def VHCADDt1s8  : VHCADDt1<"vhcadd", "s8", 0b00, 0b0>;
+def VHCADDt1s16 : VHCADDt1<"vhcadd", "s16", 0b01, 0b0>;
+def VHCADDt1s32 : VHCADDt1<"vhcadd", "s32", 0b10, 0b0>;
+
+def VCADDt1i8  : VHCADDt1<"vcadd", "i8", 0b00, 0b1>;
+def VCADDt1i16 : VHCADDt1<"vcadd", "i16", 0b01, 0b1>;
+def VCADDt1i32 : VHCADDt1<"vcadd", "i32", 0b10, 0b1>;
+
+class VADCt1<string iname, bit I, bit bit_28, dag iops, list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
+                   !con((ins MQPR:$Qn, MQPR:$Qm), iops),
+                   "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = I;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b0;
+
+  let DecoderMethod = "DecodeMveVADCInstruction";
+}
+
+def VADCt1carry : VADCt1<"vadc", 0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
+def VADCt1nocarry : VADCt1<"vadci", 0b1, 0b0, (ins)>;
+
+def VSBCt1carry : VADCt1<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
+def VSBCt1nocarry : VADCt1<"vsbci", 0b1, 0b1, (ins)>;
+
+class VQDMULLt1<string iname, string suffix, bit size, bit T,
+                list<dag> pattern=[]>
+  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
+                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_r, "", pattern> {
+  bits<4> Qn;
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{12} = T;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{0} = 0b1;
+}
+
+multiclass VQDMULLt1_half_multi<string suffix, bit size> {
+  def bh : VQDMULLt1<!strconcat("vqdmull", "b"), suffix, size, 0b0>;
+  def th : VQDMULLt1<!strconcat("vqdmull", "t"), suffix, size, 0b1>;
+}
+
+defm VQDMULLt1s16 : VQDMULLt1_half_multi<"s16", 0b0>;
+defm VQDMULLt1s32 : VQDMULLt1_half_multi<"s32", 0b1>;
+
+// end of mve_qDest_qSrc
+
+// start of mve_qDest_rSrc
+
+class MVE_qr_base<dag oops, dag iops, InstrItinClass itin, string iname,
+                  string suffix, string ops, vpred_ops vpred, string cstr,
+                  list<dag> pattern=[]>
+   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<5> Rm;
+
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b111;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{3-0} = Rm{3-0};
+}
+
+class MVE_qDest_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, "",
+           pattern>;
+
+class MVE_qDestSrc_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_n, "$Qd = $Qd_src",
+           pattern>;
+
+class MVE_qDest_single_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, rGPR:$Rm), NoItinerary, iname,
+          suffix, "$Qd, $Rm", vpred_n, "$Qd = $Qd_src", pattern> {
+  bits<4> Qd;
+  bits<5> Rm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{3-0} = Rm{3-0};
+}
+
+class VADDVSUBt2i<string iname, string suffix, bits<2> size,
+                  bit bit_5, bit bit_12, bit bit_16,
+                  bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{16} = bit_16;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = bit_5;
+}
+
+def VSUBt2i8  : VADDVSUBt2i<"vsub", "i8", 0b00, 0b0, 0b1, 0b1, 0b0>;
+def VSUBt2i16 : VADDVSUBt2i<"vsub", "i16", 0b01, 0b0, 0b1, 0b1, 0b0>;
+def VSUBt2i32 : VADDVSUBt2i<"vsub", "i32", 0b10, 0b0, 0b1, 0b1, 0b0>;
+
+def VQSUBt2s8  : VADDVSUBt2i<"vqsub", "s8", 0b00, 0b1, 0b1, 0b0, 0b0>;
+def VQSUBt2s16 : VADDVSUBt2i<"vqsub", "s16", 0b01, 0b1, 0b1, 0b0, 0b0>;
+def VQSUBt2s32 : VADDVSUBt2i<"vqsub", "s32", 0b10, 0b1, 0b1, 0b0,  0b0>;
+def VQSUBt2u8  : VADDVSUBt2i<"vqsub", "u8", 0b00, 0b1, 0b1, 0b0, 0b1>;
+def VQSUBt2u16 : VADDVSUBt2i<"vqsub", "u16", 0b01, 0b1, 0b1, 0b0, 0b1>;
+def VQSUBt2u32 : VADDVSUBt2i<"vqsub", "u32", 0b10, 0b1, 0b1, 0b0, 0b1>;
+
+def VADDt2i8  : VADDVSUBt2i<"vadd", "i8", 0b00, 0b0, 0b0, 0b1, 0b0>;
+def VADDt2i16 : VADDVSUBt2i<"vadd", "i16", 0b01, 0b0, 0b0, 0b1, 0b0>;
+def VADDt2i32 : VADDVSUBt2i<"vadd", "i32", 0b10, 0b0, 0b0, 0b1, 0b0>;
+
+def VQADDt2s8  : VADDVSUBt2i<"vqadd", "s8", 0b00, 0b1, 0b0, 0b0, 0b0>;
+def VQADDt2s16 : VADDVSUBt2i<"vqadd", "s16", 0b01, 0b1, 0b0, 0b0, 0b0>;
+def VQADDt2s32 : VADDVSUBt2i<"vqadd", "s32", 0b10, 0b1, 0b0, 0b0,  0b0>;
+def VQADDt2u8  : VADDVSUBt2i<"vqadd", "u8", 0b00, 0b1, 0b0, 0b0, 0b1>;
+def VQADDt2u16 : VADDVSUBt2i<"vqadd", "u16", 0b01, 0b1, 0b0, 0b0, 0b1>;
+def VQADDt2u32 : VADDVSUBt2i<"vqadd", "u32", 0b10, 0b1, 0b0, 0b0, 0b1>;
+
+class VQDMULLt2<string iname, string suffix, bit size,
+                bit T, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b0;
+  let Inst{12} = T;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b1;
+}
+
+multiclass VQDMULLt2_half_multi<string suffix, bit size> {
+  def bh : VQDMULLt2<"vqdmullb", suffix, size, 0b0>;
+  def th : VQDMULLt2<"vqdmullt", suffix, size, 0b1>;
+}
+
+defm VQDMULLt2s16 : VQDMULLt2_half_multi<"s16", 0b0>;
+defm VQDMULLt2s32 : VQDMULLt2_half_multi<"s32", 0b1>;
+
+class VADDVSUBt2f<string iname, string suffix, bit size, bit bit_12,
+                  list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VSUBt2f32 : VADDVSUBt2f<"vsub", "f32", 0b0, 0b1>;
+def VSUBt2f16 : VADDVSUBt2f<"vsub", "f16", 0b1, 0b1>;
+
+def VADDt2f32 : VADDVSUBt2f<"vadd", "f32", 0b0, 0b0>;
+def VADDt2f16 : VADDVSUBt2f<"vadd", "f16", 0b1, 0b0>;
+
+class VHSUBVHADDt2<string iname, string suffix, bit U, bits<2> size,
+                   bit bit_12, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b0;
+}
+
+def VHSUBt2s8  : VHSUBVHADDt2<"vhsub", "s8", 0b0, 0b00, 0b1>;
+def VHSUBt2s16 : VHSUBVHADDt2<"vhsub", "s16", 0b0, 0b01, 0b1>;
+def VHSUBt2s32 : VHSUBVHADDt2<"vhsub", "s32", 0b0, 0b10, 0b1>;
+def VHSUBt2u8  : VHSUBVHADDt2<"vhsub", "u8", 0b1, 0b00, 0b1>;
+def VHSUBt2u16 : VHSUBVHADDt2<"vhsub", "u16", 0b1, 0b01, 0b1>;
+def VHSUBt2u32 : VHSUBVHADDt2<"vhsub", "u32", 0b1, 0b10, 0b1>;
+
+def VHADDt2s8  : VHSUBVHADDt2<"vhadd", "s8", 0b0, 0b00, 0b0>;
+def VHADDt2s16 : VHSUBVHADDt2<"vhadd", "s16", 0b0, 0b01, 0b0>;
+def VHADDt2s32 : VHSUBVHADDt2<"vhadd", "s32", 0b0, 0b10, 0b0>;
+def VHADDt2u8  : VHSUBVHADDt2<"vhadd", "u8", 0b1, 0b00, 0b0>;
+def VHADDt2u16 : VHSUBVHADDt2<"vhadd", "u16", 0b1, 0b01, 0b0>;
+def VHADDt2u32 : VHSUBVHADDt2<"vhadd", "u32", 0b1, 0b10, 0b0>;
+
+class VQSHLVSHL<string iname, string suffix, bit U, bits<2> size,
+                bit bit_7, bit bit_17, list<dag> pattern=[]>
+  : MVE_qDest_single_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b100;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b1;
+  let Inst{12-8} = 0b11110;
+  let Inst{7} = bit_7;
+  let Inst{6-4} = 0b110;
+}
+
+multiclass VQSHL_helper<string iname, bit bit_7, bit bit_17> {
+  def s8  : VQSHLVSHL<iname, "s8", 0b0, 0b00, bit_7, bit_17>;
+  def s16 : VQSHLVSHL<iname, "s16", 0b0, 0b01, bit_7, bit_17>;
+  def s32 : VQSHLVSHL<iname, "s32", 0b0, 0b10, bit_7, bit_17>;
+  def u8  : VQSHLVSHL<iname, "u8", 0b1, 0b00, bit_7, bit_17>;
+  def u16 : VQSHLVSHL<iname, "u16", 0b1, 0b01, bit_7, bit_17>;
+  def u32 : VQSHLVSHL<iname, "u32", 0b1, 0b10, bit_7, bit_17>;
+}
+
+defm VQRSHLt2 : VQSHL_helper<"vqrshl", 0b1, 0b1>;
+defm VQSHLt1  : VQSHL_helper<"vqshl", 0b1, 0b0>;
+defm VRSHLt2  : VQSHL_helper<"vrshl", 0b0, 0b1>;
+defm VSHLt2   : VQSHL_helper<"vshl", 0b0, 0b0>;
+
+class VBRSRt1<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VBRSRt18  : VBRSRt1<"vbrsr", "8", 0b00>;
+def VBRSRt116 : VBRSRt1<"vbrsr", "16", 0b01>;
+def VBRSRt132 : VBRSRt1<"vbrsr", "32", 0b10>;
+
+class VMULt2<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VMULt2i8   : VMULt2<"vmul", "i8", 0b00>;
+def VMULt2i16  : VMULt2<"vmul", "i16", 0b01>;
+def VMULt2i32  : VMULt2<"vmul", "i32", 0b10>;
+
+class VMULt2f<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VMULt2f32 : VMULt2f<"vmul", "f32", 0b0>;
+def VMULt2f16 : VMULt2f<"vmul", "f16", 0b1>;
+
+class VQDMULHt3<string iname, string suffix, bits<2> size, bit bit_28,
+                list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def VQDMULHt3s8  : VQDMULHt3<"vqdmulh", "s8", 0b00, 0b0>;
+def VQDMULHt3s16 : VQDMULHt3<"vqdmulh", "s16", 0b01, 0b0>;
+def VQDMULHt3s32 : VQDMULHt3<"vqdmulh", "s32", 0b10, 0b0>;
+
+def VQRDMULHt4s8  : VQDMULHt3<"vqrdmulh", "s8", 0b00, 0b1>;
+def VQRDMULHt4s16 : VQDMULHt3<"vqrdmulh", "s16", 0b01, 0b1>;
+def VQRDMULHt4s32 : VQDMULHt3<"vqrdmulh", "s32", 0b10, 0b1>;
+
+class VFMASt1<string iname, string suffix, bit size, list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VFMASt1f32  : VFMASt1<"vfmas", "f32", 0b0>;
+def VFMASt1f16  : VFMASt1<"vfmas", "f16", 0b1>;
+
+class VMLASt1<string iname, string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def VMLASt1s8   : VMLASt1<"vmlas", "s8", 0b0, 0b00>;
+def VMLASt1s16  : VMLASt1<"vmlas", "s16", 0b0, 0b01>;
+def VMLASt1s32  : VMLASt1<"vmlas", "s32", 0b0, 0b10>;
+def VMLASt1u8   : VMLASt1<"vmlas", "u8", 0b1, 0b00>;
+def VMLASt1u16  : VMLASt1<"vmlas", "u16", 0b1, 0b01>;
+def VMLASt1u32  : VMLASt1<"vmlas", "u32", 0b1, 0b10>;
+
+class VFMAt1<string iname, string suffix, bit size,
+             list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+
+  let Predicates = [HasMVEFloat];
+}
+
+def VFMAt1rf32 : VFMAt1<"vfma", "f32", 0b0>;
+def VFMAt1rf16 : VFMAt1<"vfma", "f16", 0b1>;
+
+class VMLAt1<string iname, string suffix, bit U, bits<2> size,
+             list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def VMLAt1s8  : VMLAt1<"vmla", "s8", 0b0, 0b00>;
+def VMLAt1s16 : VMLAt1<"vmla", "s16", 0b0, 0b01>;
+def VMLAt1s32 : VMLAt1<"vmla", "s32", 0b0, 0b10>;
+def VMLAt1u8  : VMLAt1<"vmla", "u8", 0b1, 0b00>;
+def VMLAt1u16 : VMLAt1<"vmla", "u16", 0b1, 0b01>;
+def VMLAt1u32 : VMLAt1<"vmla", "u32", 0b1, 0b10>;
+
+class VQDMLAH<string iname, string suffix, bit U, bits<2> size,
+               bit bit_5, bit bit_12, list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b0;
+  let Inst{5} = bit_5;
+}
+
+multiclass VQDMLAH_helper<string iname, bit bit_5, bit bit_12> {
+  def s8  : VQDMLAH<iname, "s8", 0b0, 0b00, bit_5, bit_12>;
+  def s16 : VQDMLAH<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
+  def s32 : VQDMLAH<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
+  def u8  : VQDMLAH<iname, "u8", 0b1, 0b00, bit_5, bit_12>;
+  def u16 : VQDMLAH<iname, "u16", 0b1, 0b01, bit_5, bit_12>;
+  def u32 : VQDMLAH<iname, "u32", 0b1, 0b10, bit_5, bit_12>;
+}
+
+defm VQDMLASHt1  : VQDMLAH_helper<"vqdmlash", 0b1, 0b1>;
+defm VQRDMLASHt2 : VQDMLAH_helper<"vqrdmlash", 0b0, 0b1>;
+defm VQDMLAHt1   : VQDMLAH_helper<"vqdmlah", 0b1, 0b0>;
+defm VQRDMLAHt1  : VQDMLAH_helper<"vqrdmlah", 0b0, 0b0>;
+
+class VIDUP<string iname, string suffix, bits<2> size, bit bit_12,
+            list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, tGPROdd:$Rm, powertwo:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $Rm, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<5> Rm;
+  bits<5> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-4} = 0b110;
+  let Inst{3-1} = Rm{3-1};
+  let Inst{0} = imm{0};
+}
+
+def VIWDUPt1u8  : VIDUP<"viwdup", "u8", 0b00, 0b0>;
+def VIWDUPt1u16 : VIDUP<"viwdup", "u16", 0b01, 0b0>;
+def VIWDUPt1u32 : VIDUP<"viwdup", "u32", 0b10, 0b0>;
+
+def VDWDUPt1u8  : VIDUP<"vdwdup", "u8", 0b00, 0b1>;
+def VDWDUPt1u16 : VIDUP<"vdwdup", "u16", 0b01, 0b1>;
+def VDWDUPt1u32 : VIDUP<"vdwdup", "u32", 0b10, 0b1>;
+
+class VIDUPt2<string iname, string suffix, bits<2> size, bit bit_12,
+              list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, powertwo:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<5> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-1} = 0b110111;
+  let Inst{0} = imm{0};
+}
+
+def VIDUPt2u8  : VIDUPt2<"vidup", "u8", 0b00, 0b0>;
+def VIDUPt2u16 : VIDUPt2<"vidup", "u16", 0b01, 0b0>;
+def VIDUPt2u32 : VIDUPt2<"vidup", "u32", 0b10, 0b0>;
+
+def VDDUPt2u8  : VIDUPt2<"vddup", "u8", 0b00, 0b1>;
+def VDDUPt2u16 : VIDUPt2<"vddup", "u16", 0b01, 0b1>;
+def VDDUPt2u32 : VIDUPt2<"vddup", "u32", 0b10, 0b1>;
+
+
+class VCTPt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
+          "$Rn", vpred_n, "", pattern> {
+  bits<4> Rn;
+
+  let Inst{28-27} = 0b10;
+  let Inst{26-22} = 0b00000;
+  let Inst{21-20} = size;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{15-11} = 0b11101;
+  let Inst{10-0}  = 0b00000000001;
+  let Unpredictable{10-0} = 0b11111111111;
+
+  let Constraints = "";
+  let DecoderMethod = "DecodeMveVCTP";
+}
+
+def VCTPt18  : VCTPt1<"8", 0b00>;
+def VCTPt116 : VCTPt1<"16", 0b01>;
+def VCTPt132 : VCTPt1<"32", 0b10>;
+def VCTPt164 : VCTPt1<"64", 0b11>;
+
+// end of mve_qDest_rSrc
+
+// start of coproc mov
+
+class VMOVt1dreg<bit bit_20, dag oops, dag iops, string ops, string cstr>
+  : VMOV<oops, iops, NoItinerary, "vmov", "", ops, cstr, []> {
+  bits<5> Rt;
+  bits<5> Rt2;
+  bits<4> Qd;
+  bit idx;
+  bit idx2;
+
+  let Inst{31-23} = 0b111011000;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b0;
+  let Inst{20} = bit_20;
+  let Inst{19-16} = Rt2{3-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-5} = 0b01111000;
+  let Inst{4} = idx2;
+  let Inst{3-0} = Rt{3-0};
+}
+
+def VMOVt1qtodreg : VMOVt1dreg<0b0, (outs rGPR:$Rt, rGPR:$Rt2), (ins MQPR:$Qd,
+                               MVEPairVectorIndex2:$idx,  MVEPairVectorIndex0:$idx2),
+                               "$Rt, $Rt2, $Qd$idx, $Qd$idx2", ""> {
+  let DecoderMethod = "DecodeMVEVMOVQtoDReg";
+  let AsmMatchConverter = "cvtMVEVMOVQtoDReg";
+}
+
+def VMOVt1dregtoq : VMOVt1dreg<0b1, (outs MQPR:$Qd), (ins MQPR:$QdSrc, rGPR:$Rt, rGPR:$Rt2,
+                               MVEPairVectorIndex2:$idx,  MVEPairVectorIndex0:$idx2),
+                               "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2", "$Qd = $QdSrc"> {
+  let DecoderMethod = "DecodeMVEVMOVDRegtoQ";
+}
+// end of coproc mov
+
+class t2VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
+  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
+  bits<3> fc;
+  bits<4> Mk;
+  bits<3> Qn;
+
+  let Inst{31-23} = 0b111111100;
+  let Inst{22} = Mk{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Mk{2-0};
+  let Inst{12} = fc{2};
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = fc{0};
+  let Inst{4} = 0b0;
+
+  let Defs = [VPR, P0];
+}
+
+class t2VPTt1<string suffix, bits<2> size, dag iops>
+  : t2VPT<suffix, size, iops, "$fc, $Qn, $Qm"> {
+  bits<4> Qm;
+  bits<4> Mk;
+
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = fc{1};
+}
+
+class t2VPTt1i<string suffix, bits<2> size>
+ : t2VPTt1<suffix, size,
+           (ins vpt_mask:$Mk, pred_basic_i:$fc, MQPR:$Qn, MQPR:$Qm)> {
+  let Inst{12} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def t2VPTv4i32 : t2VPTt1i<"i32", 0b10>;
+def t2VPTv8i16 : t2VPTt1i<"i16", 0b01>;
+def t2VPTv16i8 : t2VPTt1i<"i8", 0b00>;
+
+class t2VPTt1u<string suffix, bits<2> size>
+ : t2VPTt1<suffix, size,
+           (ins vpt_mask:$Mk, pred_basic_u:$fc, MQPR:$Qn, MQPR:$Qm)> {
+  let Inst{12} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+def t2VPTv4u32 : t2VPTt1u<"u32", 0b10>;
+def t2VPTv8u16 : t2VPTt1u<"u16", 0b01>;
+def t2VPTv16u8 : t2VPTt1u<"u8", 0b00>;
+
+class t2VPTt1s<string suffix, bits<2> size>
+ : t2VPTt1<suffix, size,
+           (ins vpt_mask:$Mk, pred_basic_s:$fc, MQPR:$Qn, MQPR:$Qm)> {
+  let Inst{12} = 0b1;
+}
+
+def t2VPTv4s32 : t2VPTt1s<"s32", 0b10>;
+def t2VPTv8s16 : t2VPTt1s<"s16", 0b01>;
+def t2VPTv16s8 : t2VPTt1s<"s8", 0b00>;
+
+class t2VPTt2<string suffix, bits<2> size, dag iops>
+  : t2VPT<suffix, size, iops,
+          "$fc, $Qn, $Rm"> {
+  bits<4> Rm;
+  bits<3> fc;
+  bits<4> Mk;
+
+  let Inst{6} = 0b1;
+  let Inst{5} = fc{1};
+  let Inst{3-0} = Rm{3-0};
+}
+
+class t2VPTt2i<string suffix, bits<2> size>
+  : t2VPTt2<suffix, size,
+            (ins vpt_mask:$Mk, pred_basic_i:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
+  let Inst{12} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def t2VPTv4i32r : t2VPTt2i<"i32", 0b10>;
+def t2VPTv8i16r : t2VPTt2i<"i16", 0b01>;
+def t2VPTv16i8r : t2VPTt2i<"i8", 0b00>;
+
+class t2VPTt2u<string suffix, bits<2> size>
+  : t2VPTt2<suffix, size,
+            (ins vpt_mask:$Mk, pred_basic_u:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
+  let Inst{12} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def t2VPTv4u32r : t2VPTt2u<"u32", 0b10>;
+def t2VPTv8u16r : t2VPTt2u<"u16", 0b01>;
+def t2VPTv16u8r : t2VPTt2u<"u8", 0b00>;
+
+class t2VPTt2s<string suffix, bits<2> size>
+  : t2VPTt2<suffix, size,
+            (ins vpt_mask:$Mk, pred_basic_s:$fc, MQPR:$Qn, GPRwithZR:$Rm)> {
+  let Inst{12} = 0b1;
+}
+
+def t2VPTv4s32r : t2VPTt2s<"s32", 0b10>;
+def t2VPTv8s16r : t2VPTt2s<"s16", 0b01>;
+def t2VPTv16s8r : t2VPTt2s<"s8", 0b00>;
+
+
+class t2VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=[]>
+  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm,
+            "", pattern> {
+  bits<3> fc;
+  bits<4> Mk;
+  bits<3> Qn;
+
+  let Inst{31-29} = 0b111;
+  let Inst{28} = size;
+  let Inst{27-23} = 0b11100;
+  let Inst{22} = Mk{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Mk{2-0};
+  let Inst{12} = fc{2};
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = fc{0};
+  let Inst{4} = 0b0;
+
+  let Defs = [P0];
+  let Predicates = [HasMVEFloat];
+}
+
+class t2VPTft1<string suffix, bit size>
+  : t2VPTf<suffix, size, (ins vpt_mask:$Mk, pred_basic_fp:$fc, MQPR:$Qn, MQPR:$Qm),
+          "$fc, $Qn, $Qm"> {
+  bits<3> fc;
+  bits<4> Qm;
+
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = fc{1};
+}
+
+def t2VPTv4f32         : t2VPTft1<"f32", 0b0>;
+def t2VPTv8f16         : t2VPTft1<"f16", 0b1>;
+
+class t2VPTft2<string suffix, bit size>
+  : t2VPTf<suffix, size, (ins vpt_mask:$Mk, pred_basic_fp:$fc, MQPR:$Qn, GPRwithZR:$Rm),
+          "$fc, $Qn, $Rm"> {
+  bits<3> fc;
+  bits<4> Rm;
+
+  let Inst{6} = 0b1;
+  let Inst{5} = fc{1};
+  let Inst{3-0} = Rm{3-0};
+}
+
+def t2VPTv4f32r        : t2VPTft2<"f32", 0b0>;
+def t2VPTv8f16r        : t2VPTft2<"f16", 0b1>;
+
+def t2VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
+       !strconcat("vpst", "${Mk}"), "", "", []> {
+  bits<4> Mk;
+
+  let Inst{31-23} = 0b111111100;
+  let Inst{22} = Mk{3};
+  let Inst{21-16} = 0b110001;
+  let Inst{15-13} = Mk{2-0};
+  let Inst{12-0} = 0b0111101001101;
+  let Unpredictable{12} = 0b1;
+  let Unpredictable{7} = 0b1;
+  let Unpredictable{5} = 0b1;
+
+  let Defs = [P0];
+}
+
+// Register list operands
+def VecList2QAsmOperand : AsmOperandClass {
+  let Name = "VecListTwoMQ";
+  let ParserMethod = "parseVectorList";
+  let RenderMethod = "addMVEVecListOperands";
+}
+
+def VecList2Q : RegisterOperand<QQPR, "printMVEVectorListTwoQ"> {
+  let ParserMatchClass = VecList2QAsmOperand;
+}
+
+def VecList4QAsmOperand : AsmOperandClass {
+  let Name = "VecListFourMQ";
+  let ParserMethod = "parseVectorList";
+  let RenderMethod = "addMVEVecListOperands";
+}
+
+def VecList4Q : RegisterOperand<QQQQPR, "printMVEVectorListFourQ"> {
+  let ParserMatchClass = VecList4QAsmOperand;
+}
+
+class mve_load_store<bit U, bit P, bit A, bit W, bit b12, bit load, dag oops,
+                     dag iops, string asm, string suffix, string ops,
+                     string cstr, list<dag> pattern>
+  : MVE_MI<oops, iops, NoItinerary, !strconcat(asm, suffix),  ops, cstr, pattern> {
+  let Inst{31-29} = 0b111;
+  let Inst{28} = U;
+  let Inst{27-25} = 0b110;
+  let Inst{24} = P;
+  let Inst{23} = A;
+  let Inst{21} = W;
+  let Inst{20} = load;
+  let Inst{12} = b12;
+  let Inst{11-9} = 0b111;
+}
+
+// This class and subsequently named (multi)classes are for the deinterleaved
+// vector loads and stores.
+class mve_vld_vst_de<bit W, bit bit0, bits<2> pat, bits<2> size, bit load,
+                     dag Oops, dag loadIops, dag wbIops, string suffix,
+                     list<dag> pattern=[]>
+  : mve_load_store<1, 0, 1, W, 1, load,
+                   Oops,
+                   !con(loadIops, wbIops),
+                   !strconcat(!if(load, "vld", "vst"), !if(bit0, "4", "2")),
+                   suffix, !if(W, "$VQd, $Rn!", "$VQd, $Rn"),
+                   !if(W, "$Rn.base = $wb", "") #
+                   !if(load, ",$VQdSrc = $VQd", ""), pattern> {
+  bits<4> VQd;
+  bits<4> Rn;
+  let Inst{22} = 0b0;
+  let Inst{21} = W;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{15-13} = VQd{2-0};
+  let Inst{8-7} = size{1-0};
+  let Inst{6-5} = pat{1-0};
+  let Inst{4-1} = 0b0000;
+  let Inst{0} = bit0;
+}
+
+multiclass mve_vld_vst_de_pat<bit W, bits<2> size, bit load, dag wbOops,
+                              dag wbIops, string suffix> {
+  def 2P0 :
+    mve_vld_vst_de<W, 0b0, 0b00, size, load,
+                   !if(load, !con((outs VecList2Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList2Q:$VQdSrc), (ins VecList2Q:$VQd)),
+                   wbIops,
+                   !strconcat("0", suffix)>;
+
+  def 2P1 :
+    mve_vld_vst_de<W, 0b0, 0b01, size, load,
+                   !if(load, !con((outs VecList2Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList2Q:$VQdSrc), (ins VecList2Q:$VQd)),
+                   wbIops,
+                   !strconcat("1", suffix)>;
+
+  def 4P0 :
+    mve_vld_vst_de<W, 0b1, 0b00, size, load,
+                   !if(load, !con((outs VecList4Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList4Q:$VQdSrc), (ins VecList4Q:$VQd)),
+                   wbIops,
+                   !strconcat("0", suffix)>;
+  def 4P1 :
+    mve_vld_vst_de<W, 0b1, 0b01, size, load,
+                   !if(load, !con((outs VecList4Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList4Q:$VQdSrc), (ins VecList4Q:$VQd)),
+                   wbIops,
+                   !strconcat("1", suffix)>;
+  def 4P2 :
+    mve_vld_vst_de<W, 0b1, 0b10, size, load,
+                   !if(load, !con((outs VecList4Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList4Q:$VQdSrc), (ins VecList4Q:$VQd)),
+                   wbIops,
+                   !strconcat("2", suffix)>;
+  def 4P3 :
+    mve_vld_vst_de<W, 0b1, 0b11, size, load,
+                   !if(load, !con((outs VecList4Q:$VQd), wbOops), wbOops),
+                   !if(load, (ins VecList4Q:$VQdSrc), (ins VecList4Q:$VQd)),
+                   wbIops,
+                   !strconcat("3", suffix)>;
+}
+
+multiclass mve_vld_vst_de_size<bit W, bit load, dag wbOops, dag wbIops> {
+  defm d8 : mve_vld_vst_de_pat<W, 0b00, load, wbOops, wbIops, ".8">;
+  defm d16 : mve_vld_vst_de_pat<W, 0b01, load, wbOops, wbIops, ".16">;
+  defm d32 : mve_vld_vst_de_pat<W, 0b10, load, wbOops, wbIops, ".32">;
+}
+
+multiclass mve_vld_vst_de_wb<bit load> {
+  defm NoWriteBack
+    : mve_vld_vst_de_size<0, load, (outs ), (ins t2_addr_offset_none:$Rn)>;
+  defm WriteBack
+    : mve_vld_vst_de_size<1, load, (outs t2rGPR:$wb),
+                          (ins t2_nosp_addr_offset_none:$Rn)>;
+}
+
+let mayLoad = 1 in {
+defm MVE_VST : mve_vld_vst_de_wb<0b0>;
+}
+
+let mayStore = 1 in {
+defm MVE_VLD : mve_vld_vst_de_wb<0b1>;
+}
+
+class mve_load_store_pred<bit U, bit P, bit W, bit load, dag oops, dag iops,
+                          string asm, string suffix, string ops, string cstr,
+                          list<dag> pattern=[]>
+// Always use vpred_n rather than vpred_r, because we never need an
+// 'inactive' parameter: for stores, there isn't an output register,
+// and for loads, predicated loads zero the inactive lanes rather than
+// preserving their input values.
+ : MVE_p<oops, iops, NoItinerary, asm, suffix, ops, vpred_n, cstr, pattern> {
+  let Inst{28} = U;
+  let Inst{25} = 0b0;
+  let Inst{24} = P;
+  let Inst{22} = 0b0;
+  let Inst{21} = W;
+  let Inst{20} = load;
+}
+
+class mve_vldr_vstr_1<bit U, bit P, bit W, bit load, bits<2> size, bit opc1,
+                      dag oops, dag iops, string asm, string suffix, string ops,
+                      string cstr>
+  : mve_load_store_pred<!if(load, U, 0b0), P, W, load, oops, iops, asm, suffix,
+                     ops, cstr> {
+  bits<11> addr;
+  bits<3> Qd;
+  let Inst{23} = addr{7};
+  let Inst{19} = opc1;
+  let Inst{18-16} = addr{10-8};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0111;
+  let Inst{8-7} = size{1-0};
+  let Inst{6-0} = addr{6-0};
+}
+
+// This multiclass is used for the vectore stores and loads from consecutive
+// memory with a size higher than the written/read memory.
+multiclass mve_vldr_vstr_1_addr<bit U, bits<2> size, bit opc1, bit load,
+                                string asm, string suffix, int shift,
+                                AddrMode am> {
+  def _off :
+    mve_vldr_vstr_1<U, 1, 0, load, size, opc1,
+                    !if(load, (outs MQPR:$Qd), (outs)),
+                    !if(load, (ins taddrmode_imm7<shift>:$addr),
+                              (ins MQPR:$Qd, taddrmode_imm7<shift>:$addr)),
+                    asm, suffix, "$Qd, $addr", "" > {
+    let IM = IndexModePost;
+    let AM = am;
+  }
+
+  def _pre :
+    mve_vldr_vstr_1<U, 1, 1, load, size, opc1,
+                    !if(load, (outs tGPR:$wb, MQPR:$Qd), (outs tGPR:$wb)),
+                    !if(load, (ins taddrmode_imm7<shift>:$addr),
+                              (ins MQPR:$Qd, taddrmode_imm7<shift>:$addr)),
+                    asm, suffix, "$Qd, $addr!", "$addr.base = $wb"> {
+    let IM = IndexModePre;
+    let AM = am;
+    let DecoderMethod = "DecodeMVE_MEM_1_pre<"#shift#">";
+  }
+  def _post :
+    mve_vldr_vstr_1<U, 0, 1, load, size, opc1,
+                    !if(load, (outs tGPR:$wb, MQPR:$Qd), (outs tGPR:$wb)),
+                    !if(load, (ins t_addr_offset_none:$Rn,
+                               t2am_imm7_offset<shift>:$addr),
+                              (ins MQPR:$Qd, t_addr_offset_none:$Rn,
+                               t2am_imm7_offset<shift>:$addr)),
+                    asm, suffix, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
+   bits<4> Rn;
+   let Inst{18-16} = Rn{2-0};
+   let IM = IndexModePost;
+   let AM = am;
+ }
+}
+
+let mayLoad = 1 in {
+defm MVE_VLDRBS16
+  : mve_vldr_vstr_1_addr<0b0, 0b01, 0b0, 0b1, "vldrb", "s16", 0,
+                         AddrModeT2_i7>;
+defm MVE_VLDRBS32
+  : mve_vldr_vstr_1_addr<0b0, 0b10, 0b0, 0b1, "vldrb", "s32", 0,
+                         AddrModeT2_i7>;
+defm MVE_VLDRBU16
+  : mve_vldr_vstr_1_addr<0b1, 0b01, 0b0, 0b1, "vldrb", "u16", 0,
+                         AddrModeT2_i7>;
+defm MVE_VLDRBU32
+  : mve_vldr_vstr_1_addr<0b1, 0b10, 0b0, 0b1, "vldrb", "u32", 0,
+                         AddrModeT2_i7>;
+defm MVE_VLDRHS32
+  : mve_vldr_vstr_1_addr<0b0, 0b10, 0b1, 0b1, "vldrh", "s32", 1,
+                         AddrModeT2_i7s2>;
+defm MVE_VLDRHU32
+  : mve_vldr_vstr_1_addr<0b1, 0b10, 0b1, 0b1, "vldrh", "u32", 1,
+                         AddrModeT2_i7s2>;
+} // let mayLoad = 1
+
+let mayStore = 1 in {
+defm MVE_VSTRB16
+  : mve_vldr_vstr_1_addr<0b0, 0b01, 0b0, 0b0, "vstrb", "16", 0,
+                         AddrModeT2_i7>;
+defm MVE_VSTRB32
+  : mve_vldr_vstr_1_addr<0b0, 0b10, 0b0, 0b0, "vstrb", "32", 0,
+                         AddrModeT2_i7>;
+defm MVE_VSTRH32
+  : mve_vldr_vstr_1_addr<0b0, 0b10, 0b1, 0b0, "vstrh", "32", 1,
+                         AddrModeT2_i7s2>;
+} // let mayStore = 1
+
+// This multiclass is used for the vector stores and loads from consecutive
+// memory with a size equal to the written/read memory.
+class mve_vldr_vstr_2<bit P, bit W, bit load, bits<2> size, dag oops,
+                      dag iops, string asm, string suffix, string ops,
+                      string cstr>
+  : mve_load_store_pred<0b0, P, W, load, oops, iops, asm, suffix, ops, cstr> {
+  bits<12> addr;
+  bits<3> Qd;
+  let Inst{23} = addr{7};
+  let Inst{19-16} = addr{11-8};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b1111;
+  let Inst{8-7} = size{1-0};
+  let Inst{6-0} = addr{6-0};
+}
+multiclass mve_vldr_vstr_2_addr<bits<2> size, bit load, string asm,
+                                string suffix, int shift, AddrMode am> {
+  def _off :
+    mve_vldr_vstr_2<1, 0, load, size,
+                    !if(load, (outs MQPR:$Qd), (outs)),
+                    !if(load, (ins t2addrmode_imm7<shift>:$addr),
+                              (ins MQPR:$Qd, t2addrmode_imm7<shift>:$addr)),
+                    asm, suffix, "$Qd, $addr", "" > {
+    let IM = IndexModePost;
+    let AM = am;
+  }
+
+  def _pre :
+    mve_vldr_vstr_2<1, 1, load, size,
+                    !if(load, (outs t2rGPR:$wb, MQPR:$Qd), (outs t2rGPR:$wb)),
+                    !if(load, (ins t2addrmode_imm7_pre<shift>:$addr),
+                              (ins MQPR:$Qd, t2addrmode_imm7_pre<shift>:$addr)),
+                    asm, suffix, "$Qd, $addr!", "$addr.base = $wb"> {
+    let IM = IndexModePre;
+    let AM = am;
+    let DecoderMethod = "DecodeMVE_MEM_2_pre<"#shift#">";
+  }
+
+  def _post :
+    mve_vldr_vstr_2<0, 1, load, size,
+                    !if(load, (outs t2rGPR:$wb, MQPR:$Qd), (outs t2rGPR:$wb)),
+                    !if(load, (ins t2_addr_offset_none:$Rn,
+                               t2am_imm7_offset<shift>:$addr),
+                              (ins MQPR:$Qd, t2_nosp_addr_offset_none:$Rn,
+                               t2am_imm7_offset<shift>:$addr)),
+                    asm, suffix, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
+   bits<4> Rn;
+   let Inst{19-16} = Rn{3-0};
+   let IM = IndexModePost;
+   let AM = am;
+ }
+}
+
+let mayLoad = 1 in {
+defm MVE_VLDRBU8  : mve_vldr_vstr_2_addr<0b00, 0b1, "vldrb", "u8", 0, AddrModeT2_i7>;
+defm MVE_VLDRHU16 : mve_vldr_vstr_2_addr<0b01, 0b1, "vldrh", "u16", 1, AddrModeT2_i7s2>;
+defm MVE_VLDRWU32 : mve_vldr_vstr_2_addr<0b10, 0b1, "vldrw", "u32", 2, AddrModeT2_i7s4>;
+} // let mayLoad = 1
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s8", ".8", ".f8"] in {
+    def : MnemonicAlias<!strconcat("vldrb", cond , suffix),
+                        !strconcat("vldrb", cond, ".u8")>;
+  }
+}
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s16", ".16", ".f16"] in {
+    def : MnemonicAlias<!strconcat("vldrh", cond , suffix),
+                        !strconcat("vldrh", cond, ".u16")>;
+  }
+}
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s32", ".32", ".f32"] in {
+    def : MnemonicAlias<!strconcat("vldrw", cond , suffix),
+                        !strconcat("vldrw", cond, ".u32")>;
+  }
+}
+
+let mayStore = 1 in {
+defm MVE_VSTRBU8  : mve_vldr_vstr_2_addr<0b00, 0b0, "vstrb", "8", 0, AddrModeT2_i7>;
+defm MVE_VSTRHU16 : mve_vldr_vstr_2_addr<0b01, 0b0, "vstrh", "16", 1, AddrModeT2_i7s2>;
+defm MVE_VSTRWU32 : mve_vldr_vstr_2_addr<0b10, 0b0, "vstrw", "32", 2, AddrModeT2_i7s4>;
+} // let mayStore = 1
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s8", ".8", ".f8"] in {
+    def : MnemonicAlias<!strconcat("vstrb", cond , suffix),
+                        !strconcat("vstrb", cond, ".8")>;
+  }
+}
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s16", ".16", ".f16"] in {
+    def : MnemonicAlias<!strconcat("vstrh", cond , suffix),
+                        !strconcat("vstrh", cond, ".16")>;
+  }
+}
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s32", ".32", ".f32"] in {
+    def : MnemonicAlias<!strconcat("vstrw", cond , suffix),
+                        !strconcat("vstrw", cond, ".32")>;
+  }
+}
+
+class MemRegRQOffsetAsmOperand<int shift> : AsmOperandClass {
+  let Name = "MemRegRQS"#shift#"Offset";
+  let PredicateMethod = "isMemRegRQOffset<"#shift#">";
+  let RenderMethod = "addMemRegRQOffsetOperands";
+}
+
+def MemRegRQS0OffsetAsmOperand : MemRegRQOffsetAsmOperand<0>;
+def MemRegRQS1OffsetAsmOperand : MemRegRQOffsetAsmOperand<1>;
+def MemRegRQS2OffsetAsmOperand : MemRegRQOffsetAsmOperand<2>;
+def MemRegRQS3OffsetAsmOperand : MemRegRQOffsetAsmOperand<3>;
+
+// mve_addr_rq_shift  := reg + vreg{ << UXTW #shift}
+class mve_addr_rq_shift<int shift> : MemOperand {
+  let EncoderMethod = "getMveAddrModeRQOpValue";
+  let PrintMethod = "printMveAddrModeRQOperand<"#shift#">";
+  let ParserMatchClass =
+    !cast<AsmOperandClass>("MemRegRQS"#shift#"OffsetAsmOperand");
+  let DecoderMethod = "DecodeMveAddrModeRQ";
+  let MIOperandInfo = (ops GPRnopc:$base, MQPR:$offsreg);
+}
+
+class MemRegQOffsetAsmOperand<int shift> : AsmOperandClass {
+  let Name = "MemRegQS"#shift#"Offset";
+  let PredicateMethod = "isMemRegQOffset<"#shift#">";
+  let RenderMethod = "addMemRegQOffsetOperands";
+}
+
+def MemRegQS2OffsetAsmOperand : MemRegQOffsetAsmOperand<2>;
+def MemRegQS3OffsetAsmOperand : MemRegQOffsetAsmOperand<3>;
+
+// mve_addr_q_shift  := vreg {+ #imm7s2/4}
+class mve_addr_q_shift<int shift> : MemOperand {
+  let EncoderMethod = "getMveAddrModeQOpValue<"#shift#">";
+  // Can be printed same way as other reg + imm operands
+  let PrintMethod = "printT2AddrModeImm8Operand<false>";
+  let ParserMatchClass =
+    !cast<AsmOperandClass>("MemRegQS"#shift#"OffsetAsmOperand");
+  let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">";
+  let MIOperandInfo = (ops MQPR:$base, i32imm:$imm);
+}
+
+// This multiclass is used for the vector scatter stores and loads from
+// consecutive memory with a size larger than the written/read memory.
+class mve_vldr_vstr_sc1<bit U, bit load, bits<2> size, bits<2> opc1, bit os,
+                        dag addrOps, string asm, string suffix>
+  : mve_load_store_pred<!if(load, U, 0b0), 0b0, 0b0, load,
+                        !if(load, (outs MQPR:$Qd), (outs)),
+                        !con(!if(load, (ins ), (ins MQPR:$Qd)),
+                                                addrOps), asm, suffix,
+                        "$Qd, $addr", !if(load, "@earlyclobber $Qd", "")> {
+  bits<7> addr;
+  bits<3> Qd;
+  let Inst{23} = 0b1;
+  let Inst{19-16} = addr{6-3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0111;
+  let Inst{8-7} = size{1-0};
+  let Inst{6} = opc1{1};
+  let Inst{5} = 0;
+  let Inst{4} = opc1{0};
+  let Inst{3-1} = addr{2-0};
+  let Inst{0} = os;
+}
+
+let mayStore = 1 in {
+def mveVSTRB8noShift
+ : mve_vldr_vstr_sc1<0b0, 0b0, 0b00, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vstrb", "8">;
+def mveVSTRB16noShift
+ : mve_vldr_vstr_sc1<0b0, 0b0, 0b01, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vstrb", "16">;
+def mveVSTRB32noShift
+ : mve_vldr_vstr_sc1<0b0, 0b0, 0b10, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vstrb", "32">;
+} // let mayStore = 1
+
+multiclass mve_vldr_vstr_sc1_shift<bit U, bit load, bits<2> size, bits<2> opc1,
+                                   int shift, string asm, string suffix> {
+def noShift
+  : mve_vldr_vstr_sc1<U, load, size, opc1, 0b0,
+                      (ins mve_addr_rq_shift<0>:$addr), asm, suffix>;
+
+def Shift
+  : mve_vldr_vstr_sc1<U, load, size, opc1, 0b1,
+                      (ins mve_addr_rq_shift<shift>:$addr), asm, suffix>;
+}
+
+let mayLoad = 1 in {
+def MVE_VLDRBU8noShift
+ : mve_vldr_vstr_sc1<0b1, 0b1, 0b00, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u8">;
+def MVE_VLDRBU16noShift
+ : mve_vldr_vstr_sc1<0b1, 0b1, 0b01, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u16">;
+def MVE_VLDRBS16noShift
+ : mve_vldr_vstr_sc1<0b0, 0b1, 0b01, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vldrb", "s16">;
+def MVE_VLDRBU32noShift
+ : mve_vldr_vstr_sc1<0b1, 0b1, 0b10, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vldrb", "u32">;
+def MVE_VLDRBS32noShift
+ : mve_vldr_vstr_sc1<0b0, 0b1, 0b10, 0b00, 0b0,
+                     (ins mve_addr_rq_shift<0>:$addr), "vldrb", "s32">;
+defm MVE_VLDRHU16
+ : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b01, 0b01, 1, "vldrh", "u16">;
+defm MVE_VLDRHU32
+ : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b10, 0b01, 1, "vldrh", "u32">;
+defm MVE_VLDRHS32
+ : mve_vldr_vstr_sc1_shift<0b0, 0b1, 0b10, 0b01, 1, "vldrh", "s32">;
+defm MVE_VLDRWU32
+ : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b10, 0b10, 2, "vldrw", "u32">;
+defm MVE_VLDRDU64
+ : mve_vldr_vstr_sc1_shift<0b1, 0b1, 0b11, 0b11, 3, "vldrd", "u64">;
+} // let mayLoad = 1
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s64", ".64", ".f64"] in {
+    def : MnemonicAlias<!strconcat("vldrd", cond , suffix),
+                        !strconcat("vldrd", cond, ".u64")>;
+  }
+}
+
+let mayStore = 1 in {
+defm MVE_VSTRH16
+ : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b01, 0b01, 1, "vstrh", "16">;
+defm MVE_VSTRH32
+ : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b10, 0b01, 1, "vstrh", "32">;
+defm MVE_VSTRW32
+ : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b10, 0b10, 2, "vstrw", "32">;
+defm MVE_VSTRD64
+ : mve_vldr_vstr_sc1_shift<0b0, 0b0, 0b11, 0b11, 3, "vstrd", "64">;
+} // let mayStore = 1
+
+foreach cond = ["", "t", "e"] in {
+  foreach suffix = [".s64", ".64", ".f64"] in {
+    def : MnemonicAlias<!strconcat("vstrd", cond , suffix),
+                        !strconcat("vstrd", cond, ".64")>;
+  }
+}
+
+// This multiclass is used for the vector scatter stores and loads from
+// consecutive memory with a size equal to the written/read memory.
+class mve_vldr_vstr_sc2<bit W, bit load, bit opc1, dag wbops, dag addrOps,
+                        string asm, string ops, string suffix, string cstr>
+  : mve_load_store_pred<0b1, 0b1, W, load,
+                        !if(load, !con(wbops, (outs MQPR:$Qd)), wbops),
+                        !if(load, addrOps, !con((ins MQPR:$Qd), addrOps)),
+                        asm, suffix, ops,
+                        !if(load, !strconcat (cstr, ",@earlyclobber $Qd"),
+                                  cstr)> {
+  bits<11> addr;
+  bits<3> Qd;
+  let Inst{23} = addr{7};
+  let Inst{19-17} = addr{10-8};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b1111;
+  let Inst{8} = opc1;
+  let Inst{7} = 0b0;
+  let Inst{6-0} = addr{6-0};
+}
+
+
+multiclass mve_vldr_vstr_sc2_addr<bit load, bit opc1, dag addrOps, string asm,
+                                  string suffix, int shift> {
+  def NoWriteBack
+   : mve_vldr_vstr_sc2<0b0, load, opc1, (outs), addrOps, asm,
+                       "$Qd, $addr", suffix, "">;
+  let DecoderMethod="DecodeMVE_MEM_3_pre<"#shift#">" in {
+    def WriteBack
+      : mve_vldr_vstr_sc2<0b1, load, opc1, (outs MQPR:$wb), addrOps,
+                          asm, "$Qd, $addr!", suffix, "$addr.base = $wb">;
+ }
+}
+
+let mayLoad = 1 in {
+defm MVE_VLDRWU32
+  : mve_vldr_vstr_sc2_addr<0b1, 0b0, (ins mve_addr_q_shift<2>:$addr), "vldrw",
+                           "u32", 2>;
+defm MVE_VLDRDU64
+  : mve_vldr_vstr_sc2_addr<0b1, 0b1, (ins mve_addr_q_shift<3>:$addr), "vldrd",
+                           "u64", 3>;
+} // let mayLoad = 1
+
+let mayStore = 1 in {
+defm MVE_VSTRW32
+  : mve_vldr_vstr_sc2_addr<0b0, 0b0, (ins mve_addr_q_shift<2>:$addr), "vstrw",
+                           "32", 2>;
+defm MVE_VSTRD64
+  : mve_vldr_vstr_sc2_addr<0b0, 0b1, (ins mve_addr_q_shift<3>:$addr), "vstrd",
+                           "64", 3>;
+} // let mayStore = 1
+
+class loloop_start_tp<dag oops, dag iops, string asm, string ops, bit opc1,
+                      bits<2> size>
+  : t2LOL<oops, iops, asm, ops> {
+  bits<4> Rn;
+  bits<11> label;
+  let Predicates = [HasMVEInt];
+  let Inst{22} = 0b0;
+  let Inst{21-20} = size;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{13} = opc1;
+  let Inst{12} = 0b0;
+  let Inst{11} = !if(opc1, 0b0, label{0});
+  let Inst{10-1} = !if(opc1, 0b0000000000, label{10-1});
+  let Unpredictable{9-1} = !if(opc1, 0b111111111, 0b000000000);
+}
+
+multiclass loloop_start_tp_size <dag oops, dag iops, string asm, string ops,
+                                 bit opc1> {
+  def TP8  : loloop_start_tp<oops, iops, !strconcat(asm, ".8"), ops, opc1, 0b00>;
+  def TP16 : loloop_start_tp<oops, iops, !strconcat(asm, ".16"), ops, opc1, 0b01>;
+  def TP32 : loloop_start_tp<oops, iops, !strconcat(asm, ".32"), ops, opc1, 0b10>;
+  def TP64 : loloop_start_tp<oops, iops, !strconcat(asm, ".64"), ops, opc1, 0b11>;
+}
+
+defm MVE_WLS
+  : loloop_start_tp_size<(outs GPRlr:$LR), (ins rGPR:$Rn, wlslabel_u11:$label),
+                         "wlstp", "$LR, $Rn, $label", 0b0>;
+defm MVE_DLS
+  : loloop_start_tp_size<(outs GPRlr:$LR), (ins rGPR:$Rn),
+                         "dlstp", "$LR, $Rn", 0b1>;
+
+class loloop_end_tp<dag oops, dag iops, string asm, string ops,
+                    bit opc1>
+  : t2LOL<oops, iops, asm, ops> {
+  bits<11> label;
+  let Predicates = [HasMVEInt];
+  let Inst{22-16} = !if(opc1, 0b0001111, 0b0011111);
+  let Unpredictable{21-20} = !if(opc1, 0b11, 0b00);
+  let Inst{13} = opc1;
+  let Inst{12} = 0b0;
+  let Inst{11} = !if(opc1, 0b0, label{0});
+  let Inst{10-1} = !if(opc1, 0b0000000000, label{10-1});
+  let Unpredictable{10-1} = !if(opc1, 0b1111111111, 0b0000000000);
+}
+
+def MVE_LEUpdateTP : loloop_end_tp<(outs GPRlr:$LRout),
+                                    (ins GPRlr:$LRin, lelabel_u11:$label),
+                                    "letp", "$LRin, $label", 0b0>;
+
+def MVE_LCTP : loloop_end_tp<(outs ), (ins pred:$p), "lctp${p}", "", 0b1> {
+  let Unpredictable{20-21} = 0b11;
+  let Unpredictable{11-0} = 0b111111111111;
+}
+
+def VPNOTt1 : MVE_p<(outs ), (ins ), NoItinerary,
+       "vpnot", "", "", vpred_n, "", []> {
+  let Inst{31-0} = 0b11111110001100010000111101001101;
+  let Unpredictable{19-17} = 0b111;
+  let Unpredictable{12} = 0b1;
+  let Unpredictable{7} = 0b1;
+  let Unpredictable{5} = 0b1;
+  let Defs = [P0];
+  let Uses = [P0];
+
+  let Constraints = "";
+}
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -39,6 +39,16 @@
   let DecoderMethod = "DecodeT2ShifterImmOperand";
 }
 
+def mve_shift_imm : AsmOperandClass {
+  let Name = "MVELongShift";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticString = "operand must be an immediate in the range [1,32]";
+}
+def long_shift : Operand<i32> {
+  let ParserMatchClass = mve_shift_imm;
+  let DecoderMethod = "DecodeLongShiftOperand";
+}
+
 // Shifted operands. No register controlled shifts for Thumb2.
 // Note: We do not support rrx shifted operands yet.
 def t2_so_reg : Operand<i32>,    // reg imm
@@ -150,6 +160,26 @@
 
 // Define Thumb2 specific addressing modes.
 
+// t2_addr_offset_none := reg
+def MemNoOffsetT2AsmOperand
+  : AsmOperandClass { let Name = "MemNoOffsetT2"; }
+def t2_addr_offset_none : MemOperand {
+  let PrintMethod = "printAddrMode7Operand";
+  let DecoderMethod = "DecodeGPRnopcRegisterClass";
+  let ParserMatchClass = MemNoOffsetT2AsmOperand;
+  let MIOperandInfo = (ops GPRnopc:$base);
+}
+
+// t2_nosp_addr_offset_none := reg
+def MemNoOffsetT2NoSpAsmOperand
+  : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
+def t2_nosp_addr_offset_none : MemOperand {
+  let PrintMethod = "printAddrMode7Operand";
+  let DecoderMethod = "Decodet2rGPRRegisterClass";
+  let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
+  let MIOperandInfo = (ops t2rGPR:$base);
+}
+
 // t2addrmode_imm12  := reg + imm12
 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
 def t2addrmode_imm12 : MemOperand,
@@ -251,6 +281,103 @@
   let DecoderMethod = "DecodeT2Imm8S4";
 }
 
+// t2addrmode_imm7s4  := reg +/- (imm7 << 2)
+def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";}
+class T2AddrMode_Imm7s4 : MemOperand {
+  let EncoderMethod = "getT2AddrModeImm7s4OpValue";
+  let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";
+  let ParserMatchClass = MemImm7s4OffsetAsmOperand;
+  let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
+}
+
+def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
+}
+
+def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
+}
+
+def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; }
+def t2am_imm7s4_offset : MemOperand {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
+  let ParserMatchClass = t2am_imm7s4_offset_asmoperand;
+  let EncoderMethod = "getT2Imm7s4OpValue";
+  let DecoderMethod = "DecodeT2Imm7S4";
+}
+
+// taddrmode_imm7  := reg[r0-r7] +/- (imm7 << shift)
+class TMemImm7ShiftOffsetAsmOperand<int shift>
+  : AsmOperandClass {let Name = "TMemImm7Shift"#shift#"Offset";}
+
+def TMemImm7Shift0OffsetAsmOperand : TMemImm7ShiftOffsetAsmOperand<0>;
+def TMemImm7Shift1OffsetAsmOperand : TMemImm7ShiftOffsetAsmOperand<1>;
+
+class taddrmode_imm7<int shift> : MemOperand {
+  let ParserMatchClass =
+   !cast<AsmOperandClass>("TMemImm7Shift"#shift#"OffsetAsmOperand");
+  // They are printed the same way as the T2 imm8 version
+  let PrintMethod = "printT2AddrModeImm8Operand<false>";
+  // This can also be the same as the T2 version.
+  let EncoderMethod = "getT2AddrModeImm7OpValue<"#shift#">";
+  let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">";
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
+}
+
+// t2addrmode_imm7  := reg +/- (imm7)
+class MemImm7ShiftOffsetAsmOperand<int shift>
+: AsmOperandClass {let Name = "MemImm7Shift"#shift#"Offset"; }
+
+def MemImm7Shift0OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<0>;
+def MemImm7Shift1OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<1>;
+def MemImm7Shift2OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<2>;
+class T2AddrMode_Imm7<int shift> : MemOperand,
+      ComplexPattern<i32, 2, "SelectT2AddrModeImm7<"#shift#">", []> {
+  let EncoderMethod = "getT2AddrModeImm7OpValue<"#shift#">";
+  let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 0>";
+  let ParserMatchClass =
+    !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetAsmOperand");
+  let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
+}
+
+class t2addrmode_imm7<int shift> : T2AddrMode_Imm7<shift> {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8Operand<false>";
+}
+
+class MemImm7ShiftOffsetWBAsmOperand<int shift>
+: AsmOperandClass {let Name = "MemImm7Shift"#shift#"OffsetWB"; }
+
+def MemImm7Shift0OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<0>;
+def MemImm7Shift1OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<1>;
+def MemImm7Shift2OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<2>;
+
+class t2addrmode_imm7_pre<int shift> : T2AddrMode_Imm7<shift> {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8Operand<true>";
+  let ParserMatchClass =
+    !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetWBAsmOperand");
+  let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 1>";
+  let MIOperandInfo = (ops rGPR:$base, i32imm:$offsim);
+}
+
+class t2am_imm7shiftOffsetAsmOperand<int shift>
+  : AsmOperandClass { let Name = "Imm7Shift"#shift; }
+def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
+def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
+def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
+
+class t2am_imm7_offset<int shift> : MemOperand {
+  // They are printed the same way as the imm8 version
+  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
+  let ParserMatchClass =
+    !cast<AsmOperandClass>("t2am_imm7shift"#shift#"OffsetAsmOperand");
+  let EncoderMethod = "getT2Imm7OpValue<"#shift#">";
+  let DecoderMethod = "DecodeT2Imm7<"#shift#">";
+}
 // t2addrmode_imm0_1020s4  := reg + (imm8 << 2)
 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
   let Name = "MemImm0_1020s4Offset";
@@ -289,6 +416,55 @@
   let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
 }
 
+// Define ARMv8.1-M specific addressing modes.
+
+// Label operands for BF/BFL/WLS/DLS/LE
+class BFLabelOp<string signed, string isNeg, string size, string fixup>
+  : Operand<OtherVT> {
+  let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",
+                                 fixup, ">");
+  let OperandType = "OPERAND_PCREL";
+  let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",
+                                 isNeg, ", ", size, ">");
+}
+def bflabel_u4  : BFLabelOp<"false", "false", "4",  "ARM::fixup_bf_branch">;
+def bflabel_s12 : BFLabelOp<"true",  "false", "12", "ARM::fixup_bfc_target">;
+def bflabel_s16 : BFLabelOp<"true",  "false", "16", "ARM::fixup_bf_target">;
+def bflabel_s18 : BFLabelOp<"true",  "false", "18", "ARM::fixup_bfl_target">;
+def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls">;
+def lelabel_u11 : BFLabelOp<"false", "true",  "11", "ARM::fixup_le">;
+
+def bfafter_target : Operand<OtherVT> {
+    let EncoderMethod = "getBFAfterTargetOpValue";
+    let OperandType = "OPERAND_PCREL";
+    let DecoderMethod = "DecodeBFAfterTargetOperand";
+}
+
+// pred operand excluding AL
+def pred_noal_asmoperand : AsmOperandClass {
+  let Name = "CondCodeNoAL";
+  let RenderMethod = "addITCondCodeOperands";
+  let PredicateMethod = "isITCondCodeNoAL";
+  let ParserMethod = "parseITCondCode";
+}
+def pred_noal : Operand<i32> {
+  let PrintMethod = "printMandatoryPredicateOperand";
+  let ParserMatchClass = pred_noal_asmoperand;
+  let DecoderMethod = "DecodePredNoALOperand";
+}
+
+
+// CSEL aliases inverted predicate
+def pred_noal_inv_asmoperand : AsmOperandClass {
+  let Name = "CondCodeNoALInv";
+  let RenderMethod = "addITCondCodeInvOperands";
+  let PredicateMethod = "isITCondCodeNoAL";
+  let ParserMethod = "parseITCondCode";
+}
+def pred_noal_inv : Operand<i32> {
+  let PrintMethod = "printMandatoryInvertedPredicateOperand";
+  let ParserMatchClass = pred_noal_inv_asmoperand;
+}
 //===----------------------------------------------------------------------===//
 // Multiclass helpers...
 //
@@ -4897,3 +5073,209 @@
 def : InstAlias<"pli${p} $addr",
                  (t2PLIpci  t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
       Requires<[IsThumb2,HasV7]>;
+
+
+//===----------------------------------------------------------------------===//
+// ARMv8.1m instructions
+//
+
+class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
+             string ops, string cstr, list<dag> pattern>
+  : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr,
+             pattern>,
+    Requires<[HasV8_1MMainline]>;
+
+def t2CLRM : V8_1MI<(outs),
+                    (ins pred:$p, reglist_with_apsr:$regs, variable_ops),
+                    AddrModeNone, NoItinerary, "clrm", "${p}\t$regs", "", []> {
+  bits<16> regs;
+
+  let Inst{31-16} = 0b1110100010011111;
+  let Inst{15-14} = regs{15-14};
+  let Inst{13} = 0b0;
+  let Inst{12-0} = regs{12-0};
+}
+
+class t2BF<dag iops, string asm, string ops>
+  : V8_1MI<(outs ), iops, AddrMode_bf, NoItinerary, asm, ops, "", []> {
+
+  let Inst{31-27} = 0b11110;
+  let Inst{15-14} = 0b11;
+  let Inst{12} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+def t2BF_LabelPseudo
+  : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []>,
+    Requires<[HasV8_1MMainline]> {
+  let isTerminator = 1;
+}
+
+def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),
+                 !strconcat("bf", "${p}"), "$b_label, $label"> {
+  bits<4> b_label;
+  bits<16> label;
+
+  let Inst{26-23} = b_label{3-0};
+  let Inst{22-21} = 0b10;
+  let Inst{20-16} = label{15-11};
+  let Inst{13} = 0b1;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,
+                   bfafter_target:$ba_label, pred_noal:$bcond), "bfcsel",
+                  "$b_label, $label, $ba_label, $bcond"> {
+  bits<4> bcond;
+  bits<12> label;
+  bits<1> ba_label;
+  bits<4> b_label;
+
+  let Inst{26-23} = b_label{3-0};
+  let Inst{22} = 0b0;
+  let Inst{21-18} = bcond{3-0};
+  let Inst{17} = ba_label{0};
+  let Inst{16} = label{11};
+  let Inst{13} = 0b1;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
+                 !strconcat("bfx", "${p}"), "$b_label, $Rn"> {
+  bits<4> b_label;
+  bits<4> Rn;
+
+  let Inst{26-23} = b_label{3-0};
+  let Inst{22-20} = 0b110;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{13-1} = 0b1000000000000;
+}
+
+def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),
+                  !strconcat("bfl", "${p}"), "$b_label, $label"> {
+  bits<4> b_label;
+  bits<18> label;
+
+  let Inst{26-23} = b_label{3-0};
+  let Inst{22-16} = label{17-11};
+  let Inst{13} = 0b0;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),
+                  !strconcat("bflx", "${p}"), "$b_label, $Rn"> {
+  bits<4> b_label;
+  bits<4> Rn;
+
+  let Inst{26-23} = b_label{3-0};
+  let Inst{22-20} = 0b111;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{13-1} = 0b1000000000000;
+}
+
+class t2LOL<dag oops, dag iops, string asm, string ops>
+  : V8_1MI<oops, iops, AddrMode_bf, NoItinerary, asm, ops, "", [] > {
+  let Inst{31-23} = 0b111100000;
+  let Inst{15-14} = 0b11;
+  let Inst{0} = 0b1;
+  let isBranch = 1;
+  let isTerminator = 1;
+  let DecoderMethod = "DecodeLOLoop";
+}
+
+def t2WLS : t2LOL<(outs GPRlr:$LR),
+                  (ins rGPR:$Rn, wlslabel_u11:$label),
+                  "wls", "$LR, $Rn, $label"> {
+  bits<4> Rn;
+  bits<11> label;
+  let Inst{22-20} = 0b100;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{13-12} = 0b00;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+  let usesCustomInserter = 1;
+}
+
+def t2DLS : t2LOL<(outs GPRlr:$LR), (ins rGPR:$Rn),
+                  "dls", "$LR, $Rn"> {
+  bits<4> Rn;
+  let isBranch = 0;
+  let Inst{22-20} = 0b100;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{13-1} = 0b1000000000000;
+  let usesCustomInserter = 1;
+}
+
+def t2LEUpdate : t2LOL<(outs GPRlr:$LRout),
+                       (ins GPRlr:$LRin, lelabel_u11:$label),
+                       "le", "$LRin, $label"> {
+  bits<11> label;
+  let Inst{22-16} = 0b0001111;
+  let Inst{13-12} = 0b00;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+  let usesCustomInserter = 1;
+}
+
+def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> {
+  bits<11> label;
+  let Inst{22-16} = 0b0101111;
+  let Inst{13-12} = 0b00;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+let Uses = [CPSR] in {
+class CS<string iname, list<dag> pattern=[]>
+  : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZR:$Rm, pred_noal:$fcond),
+           AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
+  bits<4> Rd;
+  bits<4> Rm;
+  bits<4> Rn;
+  bits<4> fcond;
+
+  let Inst{31-20} = 0b111010100101;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{11-8} = Rd{3-0};
+  let Inst{7-4} = fcond{3-0};
+  let Inst{3-0} = Rm{3-0};
+}
+}
+
+def t2CSEL : CS<"csel"> {
+  let Inst{15-12} = 0b1000;
+}
+
+def t2CSINC : CS<"csinc"> {
+  let Inst{15-12} = 0b1001;
+}
+
+def t2CSINV : CS<"csinv"> {
+  let Inst{15-12} = 0b1010;
+}
+
+def t2CSNEG : CS<"csneg"> {
+  let Inst{15-12} = 0b1011;
+}
+
+
+// CS aliases.
+let Predicates = [HasV8_1MMainline] in {
+  def : MVEInstAlias<"csetm\t$Rd, $fcond",
+                    (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
+
+  def : MVEInstAlias<"cset\t$Rd, $fcond",
+                    (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
+
+  def : MVEInstAlias<"cinc\t$Rd, $Rn, $fcond",
+                    (t2CSINC rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
+
+  def : MVEInstAlias<"cinv\t$Rd, $Rn, $fcond",
+                    (t2CSINV rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
+
+  def : MVEInstAlias<"cneg\t$Rd, $Rn, $fcond",
+                    (t2CSNEG rGPR:$Rd, GPRwithZR:$Rn, GPRwithZR:$Rn, pred_noal_inv:$fcond)>;
+}
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2294,16 +2294,17 @@
   let Inst{6-5}   = 0b00;
   let Inst{4}     = 1;
   let Inst{3-0}   = 0b0000;
+  let Predicates = [HasVFP2];
 }
 
-// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
-// to APSR.
-let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
-    Rt = 0b1111 /* apsr_nzcv */ in
-def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
-                        "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
-
 let DecoderMethod = "DecodeForVMRSandVMSR" in {
+ // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
+ // to APSR.
+ let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
+     Rt = 0b1111 /* apsr_nzcv */ in
+ def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
+                         "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
+
  // Application level FPSCR -> GPR
  let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in
  def VMRS :  MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
@@ -2328,6 +2329,33 @@
                                 "vmrs", "\t$Rt, fpinst", []>;
    def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),
                                  (ins), "vmrs", "\t$Rt, fpinst2", []>;
+   let Predicates = [HasV8_1MMainline, HasFPRegs] in {
+     // System level FPSCR_NZCVQC -> GPR
+     def VMRS_FPSCR_NZCVQC
+       : MovFromVFP<0b0010 /* fpscr_nzcvqc */,
+                    (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in),
+                    "vmrs", "\t$Rt, fpscr_nzcvqc", []>;
+   }
+ }
+ let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+   // System level FPSCR -> GPR, with context saving for security extensions
+   def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins),
+                                 "vmrs", "\t$Rt, fpcxtns", []>;
+ }
+ let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+   // System level FPSCR -> GPR, with context saving for security extensions
+   def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins),
+                                "vmrs", "\t$Rt, fpcxts", []>;
+ }
+
+ let Predicates = [HasV8_1MMainline, HasMVEInt] in {
+   // System level VPR/P0 -> GPR
+   let Uses = [VPR] in
+   def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins),
+                             "vmrs", "\t$Rt, vpr", []>;
+
+   def VMRS_P0  : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond),
+                             "vmrs", "\t$Rt, p0", []>;
  }
 }
 
@@ -2350,6 +2378,7 @@
   let Inst{11-8}  = 0b1010;
   let Inst{7}     = 0;
   let Inst{4}     = 1;
+  let Predicates = [HasVFP2];
 }
 
 let DecoderMethod = "DecodeForVMRSandVMSR" in {
@@ -2370,6 +2399,33 @@
    def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
                                "vmsr", "\tfpinst2, $src", []>;
  }
+ let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+   // System level GPR -> FPSCR with context saving for security extensions
+   def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$src),
+                               "vmsr", "\tfpcxtns, $src", []>;
+ }
+ let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+   // System level GPR -> FPSCR with context saving for security extensions
+   def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$src),
+                              "vmsr", "\tfpcxts, $src", []>;
+ }
+ let Predicates = [HasV8_1MMainline, HasFPRegs] in {
+   // System level GPR -> FPSCR_NZCVQC
+   def VMSR_FPSCR_NZCVQC
+     : MovToVFP<0b0010 /* fpscr_nzcvqc */,
+                (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$src),
+                "vmsr", "\tfpscr_nzcvqc, $src", []>;
+ }
+
+ let Predicates = [HasV8_1MMainline, HasMVEInt] in {
+   // System level GPR -> VPR/P0
+   let Defs = [VPR] in
+   def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$src),
+                           "vmsr", "\tvpr, $src", []>;
+
+   def VMSR_P0  : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$src),
+                           "vmsr", "\tp0, $src", []>;
+ }
 }
 
 //===----------------------------------------------------------------------===//
@@ -2546,3 +2602,126 @@
                     (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
                     (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;
+
+def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops),
+                      AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,
+                      "vscclrm{$p}\t$regs", "", []>, Sched<[]> {
+  bits<13> regs;
+  let Inst{31-23} = 0b111011001;
+  let Inst{22} = regs{12};
+  let Inst{21-16} = 0b011111;
+  let Inst{15-12} = regs{11-8};
+  let Inst{11-8} = 0b1011;
+  let Inst{7-0} = regs{7-0};
+
+  let DecoderMethod = "DecodeVSCCLRM";
+
+  list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt];
+}
+
+def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops),
+                      AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,
+                      "vscclrm{$p}\t$regs", "", []>, Sched<[]> {
+  bits<13> regs;
+  let Inst{31-23} = 0b111011001;
+  let Inst{22} = regs{8};
+  let Inst{21-16} = 0b011111;
+  let Inst{15-12} = regs{12-9};
+  let Inst{11-8} = 0b1010;
+  let Inst{7-0} = regs{7-0};
+
+  let DecoderMethod = "DecodeVSCCLRM";
+
+  list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt];
+}
+
+//===----------------------------------------------------------------------===//
+// Store VFP System Register to memory.
+//
+
+class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg,
+                  dag oops, dag iops, IndexMode im, string Dest, string cstr>
+    : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT,
+           !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>,
+      Sched<[]> {
+  bits<12> addr;
+  let Inst{27-25} = 0b110;
+  let Inst{24} = P;
+  let Inst{23} = addr{7};
+  let Inst{22} = SysReg{3};
+  let Inst{21} = W;
+  let Inst{20} = opc;
+  let Inst{19-16} = addr{11-8};
+  let Inst{15-13} = SysReg{2-0};
+  let Inst{12-7} = 0b011111;
+  let Inst{6-0} = addr{6-0};
+  list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline];
+  let mayLoad = opc;
+  let mayStore = !if(opc, 0b0, 0b1);
+  let hasSideEffects = 1;
+}
+
+multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg,
+                              dag oops=(outs), dag iops=(ins)> {
+  def _off :
+    vfp_vstrldr<opc, 1, 0, SysReg, sysreg,
+                oops, !con(iops, (ins t2addrmode_imm7s4:$addr)),
+                IndexModePost, "$addr", "" > {
+    let DecoderMethod = "DecodeVSTRVLDR_SYSREG_off";
+  }
+
+  def _pre :
+    vfp_vstrldr<opc, 1, 1, SysReg, sysreg,
+                !con(oops, (outs GPRnopc:$wb)),
+                !con(iops, (ins t2addrmode_imm7s4_pre:$addr)),
+                IndexModePre, "$addr!", "$addr.base = $wb"> {
+    let DecoderMethod = "DecodeVSTRVLDR_SYSREG_pre";
+  }
+
+  def _post :
+    vfp_vstrldr<opc, 0, 1, SysReg, sysreg,
+                !con(oops, (outs GPRnopc:$wb)),
+                !con(iops, (ins t2_addr_offset_none:$Rn,
+                                t2am_imm7s4_offset:$addr)),
+                IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {
+   bits<4> Rn;
+   let Inst{19-16} = Rn{3-0};
+   let DecoderMethod = "DecodeVSTRVLDR_SYSREG_post";
+ }
+}
+
+let Defs = [FPSCR] in {
+  defm VSTR_FPSCR          : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;
+  defm VSTR_FPSCR_NZCVQC   : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">;
+
+  let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+    defm VSTR_FPCXTNS      : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">;
+    defm VSTR_FPCXTS       : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">;
+  }
+}
+
+let Predicates = [HasV8_1MMainline, HasMVEInt] in {
+  let Uses = [VPR] in {
+    defm VSTR_VPR          : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">;
+  }
+  defm VSTR_P0             : vfp_vstrldr_sysreg<0b0,0b1101, "p0",
+                                                (outs), (ins VCCR:$P0)>;
+}
+
+let Uses = [FPSCR] in {
+  defm VLDR_FPSCR          : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">;
+  defm VLDR_FPSCR_NZCVQC   : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">;
+
+  let Predicates = [HasV8_1MMainline, Has8MSecExt] in {
+    defm VLDR_FPCXTNS      : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;
+    defm VLDR_FPCXTS       : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">;
+  }
+}
+
+let Predicates = [HasV8_1MMainline, HasMVEInt] in {
+  let Defs = [VPR] in {
+    defm VLDR_VPR          : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">;
+  }
+  defm VLDR_P0             : vfp_vstrldr_sysreg<0b1,0b1101, "p0",
+                                                (outs VCCR:$P0), (ins)>;
+}
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -160,6 +160,10 @@
          "Subclass not added?");
   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
          "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
+         "Subclass not added?");
+  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
+         "Subclass not added?");
   assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
 
 #ifndef NDEBUG
@@ -181,6 +185,10 @@
   case tGPR_and_tcGPRRegClassID:
   case tcGPRRegClassID:
   case tGPRRegClassID:
+  case tGPREven_and_tGPR_and_tcGPRRegClassID:
+  case tGPROdd_and_tcGPRRegClassID:
+  case tGPR_and_tGPREvenRegClassID:
+  case tGPR_and_tGPROddRegClassID:
     return getRegBank(ARM::GPRRegBankID);
   case HPRRegClassID:
   case SPR_8RegClassID:
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -197,6 +197,17 @@
 def FPEXC   : ARMReg<8,  "fpexc">;
 def FPINST  : ARMReg<9,  "fpinst">;
 def FPINST2 : ARMReg<10, "fpinst2">;
+// These encodings aren't actual instruction encodings, their encoding depends
+// on the instruction they are used in and for VPR 32 was chosen such that it
+// always comes last in spr_reglist_with_vpr.
+def VPR     : ARMReg<32, "vpr">;
+def FPSCR_NZCVQC
+            : ARMReg<2, "fpscr_nzcvqc">;
+def P0      : ARMReg<13, "p0">;
+def FPCXTNS : ARMReg<14, "fpcxtns">;
+def FPCXTS  : ARMReg<15, "fpcxts">;
+
+def ZR  : ARMReg<15, "zr">,  DwarfRegNum<[15]>;
 
 // Register classes.
 //
@@ -245,6 +256,21 @@
   let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
 }
 
+// GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
+def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
+  let isAllocatable = 0;
+}
+
+def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
+                                              LR, ZR)> {
+
+  let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)];
+  let AltOrderSelect = [{
+      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+  }];
+  let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr";
+}
+
 // GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
 // implied SP argument list.
 // FIXME: It would be better to not use this at all and refactor the
@@ -254,6 +280,10 @@
   let DiagnosticString = "operand must be a register sp";
 }
 
+// GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions
+// where LR is the only legal loop counter register.
+def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
+
 // restricted GPR register class. Many Thumb2 instructions allow the full
 // register range for operands, but have undefined behaviours when PC
 // or SP (R13 or R15) are used. The ARM ISA refers to these operands
@@ -266,6 +296,15 @@
   let DiagnosticType = "rGPR";
 }
 
+// t2rGPR : All Thumb 2 registers with the exception of SP and PC.
+def t2rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
+  let AltOrders = [(add LR, t2rGPR), (trunc t2rGPR, 8)];
+  let AltOrderSelect = [{
+      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+  }];
+  let DiagnosticType = "rGPR";
+}
+
 // Thumb registers are R0-R7 normally. Some instructions can still use
 // the general GPR register class above (MOV, e.g.)
 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
@@ -292,12 +331,36 @@
   }];
 }
 
+def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {
+  let AltOrders = [(and tGPROdd, tGPR)];
+  let AltOrderSelect = [{
+      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+  }];
+}
+
+def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
+  let AltOrders = [(and tGPREven, tGPR)];
+  let AltOrderSelect = [{
+      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+  }];
+}
+
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
   let CopyCost = -1;  // Don't allow copying of status registers.
   let isAllocatable = 0;
 }
 
+// MVE Condition code register.
+def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
+//  let CopyCost = -1;  // Don't allow copying of status registers.
+  let AltOrders = [(add VPR)];
+}
+
+// FPSCR, when the flags at the top of it are used as the input or
+// output to an instruction such as MVE VADC.
+def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
+
 // Scalar single precision floating point register class..
 // FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack
 // to avoid partial-write dependencies on D or Q (depending on platform)
@@ -348,6 +411,13 @@
   let DiagnosticType = "DPR";
 }
 
+// Scalar single and double precision floating point and VPR register class,
+// this is only used for parsing, don't use it anywhere else as the size and
+// types don't match!
+def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
+    let isAllocatable = 0;
+}
+
 // Subset of DPR that are accessible with VFP2 (and so that also have
 // 32-bit SPR subregs).
 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
@@ -366,8 +436,10 @@
 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
                         (sequence "Q%u", 0, 15)> {
   // Allocate non-VFP2 aliases Q8-Q15 first.
-  let AltOrders = [(rotl QPR, 8)];
-  let AltOrderSelect = [{ return 1; }];
+  let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)];
+  let AltOrderSelect = [{
+    return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
+  }];
   let DiagnosticString = "operand must be a register in range [q0, q15]";
 }
 
@@ -383,6 +455,12 @@
   let DiagnosticString = "operand must be a register in range [q0, q3]";
 }
 
+// MVE 128-bit vector register class. This class is only really needed for
+// parsing assembly, since we still have to truncate the register set in the QPR
+// class anyway.
+def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16],
+                         128, (trunc QPR, 8)>;
+
 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
 // pairs are already represented by the Q registers.
 // These are needed by NEON instructions requiring two consecutive D registers.
@@ -397,8 +475,11 @@
                           128, (interleave QPR, TuplesOE2D)> {
   // Allocate starting at non-VFP2 registers D16-D31 first.
   // Prefer even-odd pairs as they are easier to copy.
-  let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
-  let AltOrderSelect = [{ return 1; }];
+  let AltOrders = [(add (rotl QPR, 8),  (rotl DPair, 16)),
+                   (add (trunc QPR, 8), (trunc DPair, 16))];
+  let AltOrderSelect = [{
+    return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
+  }];
 }
 
 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -94,6 +94,9 @@
 
   // FIXME: Remove when all errors have been fixed.
   let FullInstRWOverlapCheck = 0;
+
+  let UnsupportedFeatures = [HasV8_1MMainline, HasMVEInt, HasMVEFloat,
+                             HasFPRegsV8_1M];
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -68,6 +68,10 @@
 
 using namespace llvm;
 
+namespace llvm {
+extern const MCInstrDesc ARMInsts[];
+} // end namespace llvm
+
 namespace {
 
 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
@@ -363,6 +367,18 @@
     ITState.IsExplicit = true;
   }
 
+  struct {
+    unsigned Mask : 4;
+    unsigned CurPosition;
+  } VPTState;
+  bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
+  void forwardVPTPosition() {
+    if (!inVPTBlock()) return;
+    unsigned TZ = countTrailingZeros(VPTState.Mask);
+    if (++VPTState.CurPosition == 5 - TZ)
+      VPTState.CurPosition = ~0U;
+  }
+
   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
     return getParser().Note(L, Msg, Range);
   }
@@ -421,12 +437,15 @@
   bool parseDirectiveAlign(SMLoc L);
   bool parseDirectiveThumbSet(SMLoc L);
 
-  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
-                          bool &CarrySetting, unsigned &ProcessorIMod,
-                          StringRef &ITMask);
-  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
-                             bool &CanAcceptCarrySet,
-                             bool &CanAcceptPredicationCode);
+  bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
+  StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
+                          unsigned &PredicationCode,
+                          unsigned &VPTPredicationCode, bool &CarrySetting,
+                          unsigned &ProcessorIMod, StringRef &ITMask);
+  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
+                             StringRef FullInst, bool &CanAcceptCarrySet,
+                             bool &CanAcceptPredicationCode,
+                             bool &CanAcceptVPTPredicationCode);
 
   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
                                      OperandVector &Operands);
@@ -478,7 +497,21 @@
   bool hasV8MMainline() const {
     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
   }
-
+  bool hasV8_1MMainline() const {
+    return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
+  }
+  bool hasMVEInt() const {
+    return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
+  }
+  bool hasMVEFloat() const {
+    return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
+  }
+  bool hasVFP2() const {
+      return getSTI().getFeatureBits()[ARM::FeatureVFP2];
+  }
+  bool hasMVE() const {
+    return hasMVEInt() || hasMVEFloat();
+  }
   bool has8MSecExt() const {
     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
   }
@@ -556,11 +589,13 @@
   // Asm Match Converter Methods
   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
+  void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
 
   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
+  bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
   bool isITBlockTerminator(MCInst &Inst) const;
   void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
   bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
@@ -597,6 +632,8 @@
     // Not in an ITBlock to start with.
     ITState.CurPosition = ~0U;
 
+    VPTState.CurPosition = ~0U;
+
     NextSymbolIsThumb = false;
   }
 
@@ -642,6 +679,7 @@
 class ARMOperand : public MCParsedAsmOperand {
   enum KindTy {
     k_CondCode,
+    k_VPTPred,
     k_CCOut,
     k_ITCondMask,
     k_CoprocNum,
@@ -659,8 +697,11 @@
     k_VectorIndex,
     k_Register,
     k_RegisterList,
+    k_RegisterListWithAPSR,
     k_DPRRegisterList,
     k_SPRRegisterList,
+    k_FPSRegisterListWithVPR,
+    k_FPDRegisterListWithVPR,
     k_VectorList,
     k_VectorListAllLanes,
     k_VectorListIndexed,
@@ -681,6 +722,10 @@
     ARMCC::CondCodes Val;
   };
 
+  struct VCCOp {
+    ARMVCC::VPTCodes Val;
+  };
+
   struct CopOp {
     unsigned Val;
   };
@@ -797,6 +842,7 @@
 
   union {
     struct CCOp CC;
+    struct VCCOp VCC;
     struct CopOp Cop;
     struct CoprocOptionOp CoprocOption;
     struct MBOptOp MBOpt;
@@ -845,6 +891,11 @@
     return CC.Val;
   }
 
+  ARMVCC::VPTCodes getVPTPred() const {
+    assert(isVPTPred() && "Invalid access!");
+    return VCC.Val;
+  }
+
   unsigned getCoproc() const {
     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
     return Cop.Val;
@@ -861,8 +912,11 @@
   }
 
   const SmallVectorImpl<unsigned> &getRegList() const {
-    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
-            Kind == k_SPRRegisterList) && "Invalid access!");
+    assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
+            Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
+            Kind == k_FPSRegisterListWithVPR ||
+            Kind == k_FPDRegisterListWithVPR) &&
+           "Invalid access!");
     return Registers;
   }
 
@@ -915,6 +969,7 @@
   bool isCoprocReg() const { return Kind == k_CoprocReg; }
   bool isCoprocOption() const { return Kind == k_CoprocOption; }
   bool isCondCode() const { return Kind == k_CondCode; }
+  bool isVPTPred() const { return Kind == k_VPTPred; }
   bool isCCOut() const { return Kind == k_CCOut; }
   bool isITMask() const { return Kind == k_ITCondMask; }
   bool isITCondCode() const { return Kind == k_CondCode; }
@@ -982,7 +1037,7 @@
       if (!CE) return false;
       Val = CE->getValue();
     }
-    else if (isMem()) {
+    else if (isGPRMem()) {
       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
       if(Memory.BaseRegNum != ARM::PC) return false;
       Val = Memory.OffsetImm->getValue();
@@ -1016,7 +1071,14 @@
     int64_t Value = CE->getValue();
     return ((Value & 3) == 0) && Value >= N && Value <= M;
   }
-
+  template<int64_t N, int64_t M>
+  bool isImmediateS2() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ((Value & 1) == 0) && Value >= N && Value <= M;
+  }
   bool isFBits16() const {
     return isImmediate<0, 17>();
   }
@@ -1026,6 +1088,21 @@
   bool isImm8s4() const {
     return isImmediateS4<-1020, 1020>();
   }
+  bool isImm7s4() const {
+    return isImmediateS4<-508, 508>();
+  }
+  bool isImm7Shift0() const {
+    return isImmediate<-127, 127>();
+  }
+  bool isImm7Shift1() const {
+    return isImmediateS2<-255, 255>();
+  }
+  bool isImm7Shift2() const {
+    return isImmediateS4<-511, 511>();
+  }
+  bool isImm7() const {
+    return isImmediate<-127, 127>();
+  }
   bool isImm0_1020s4() const {
     return isImmediateS4<0, 1020>();
   }
@@ -1098,6 +1175,34 @@
     return isImmediate<1, 33>();
   }
 
+  template<int shift>
+  bool isExpImmValue(uint64_t Value) const {
+    uint64_t mask = (1 << shift) - 1;
+    if ((Value & mask) != 0 || (Value >> shift) > 0xff)
+      return false;
+    return true;
+  }
+
+  template<int shift>
+  bool isExpImm() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+
+    return isExpImmValue<shift>(CE->getValue());
+  }
+
+  template<int shift, int size>
+  bool isInvertedExpImm() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+
+    uint64_t OriginalValue = CE->getValue();
+    uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
+    return isExpImmValue<shift>(InvertedValue);
+  }
+
   bool isPKHLSLImm() const {
     return isImmediate<0, 32>();
   }
@@ -1167,13 +1272,34 @@
 
   bool isReg() const override { return Kind == k_Register; }
   bool isRegList() const { return Kind == k_RegisterList; }
+  bool isRegListWithAPSR() const {
+    return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
+  }
   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
+  bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
+  bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
   bool isToken() const override { return Kind == k_Token; }
   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
   bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
   bool isMem() const override {
+      return isGPRMem() || isMVEMem();
+  }
+  bool isMVEMem() const {
+    if (Kind != k_Memory)
+      return false;
+    if (Memory.BaseRegNum &&
+        !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
+        !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
+      return false;
+    if (Memory.OffsetRegNum &&
+        !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+            Memory.OffsetRegNum))
+      return false;
+    return true;
+  }
+  bool isGPRMem() const {
     if (Kind != k_Memory)
       return false;
     if (Memory.BaseRegNum &&
@@ -1198,6 +1324,27 @@
                RegShiftedImm.SrcReg);
   }
   bool isRotImm() const { return Kind == k_RotateImmediate; }
+  bool isVCMLARotImm() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value == 0 || Value == 90 || Value == 180 || Value == 270;
+  }
+  bool isVCADDRotImm() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value == 90 || Value == 270;
+  }
+  bool isPowerTwo() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value == 1 || Value == 2 || Value == 4 || Value == 8;
+  }
   bool isModImm() const { return Kind == k_ModifiedImmediate; }
 
   bool isModImmNot() const {
@@ -1243,14 +1390,50 @@
     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
   }
   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
-    if (!isMem())
+    if (!isGPRMem())
+      return false;
+    // No offset of any kind.
+    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
+     (alignOK || Memory.Alignment == Alignment);
+  }
+  bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
+    if (!isGPRMem())
+      return false;
+
+    if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+
+    // No offset of any kind.
+    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
+     (alignOK || Memory.Alignment == Alignment);
+  }
+  bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
+    if (!isGPRMem())
+      return false;
+
+    if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+
+    // No offset of any kind.
+    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
+     (alignOK || Memory.Alignment == Alignment);
+  }
+  bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
+    if (!isGPRMem())
       return false;
+
+    if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+
     // No offset of any kind.
     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
      (alignOK || Memory.Alignment == Alignment);
   }
   bool isMemPCRelImm12() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base register must be PC.
     if (Memory.BaseRegNum != ARM::PC)
@@ -1337,7 +1520,7 @@
   }
 
   bool isAddrMode2() const {
-    if (!isMem() || Memory.Alignment != 0) return false;
+    if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return true;
     // Immediate offset in range [-4095, 4095].
@@ -1362,7 +1545,7 @@
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
-    if (!isMem() || Memory.Alignment != 0) return false;
+    if (!isGPRMem() || Memory.Alignment != 0) return false;
     // No shifts are legal for AM3.
     if (Memory.ShiftType != ARM_AM::no_shift) return false;
     // Check for register offset.
@@ -1396,7 +1579,7 @@
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
-    if (!isMem() || Memory.Alignment != 0) return false;
+    if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return false;
     // Immediate offset in range [-1020, 1020] and a multiple of 4.
@@ -1412,7 +1595,7 @@
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
-    if (!isMem() || Memory.Alignment != 0) return false;
+    if (!isGPRMem() || Memory.Alignment != 0) return false;
     // Check for register offset.
     if (Memory.OffsetRegNum) return false;
     // Immediate offset in range [-510, 510] and a multiple of 2.
@@ -1423,14 +1606,14 @@
   }
 
   bool isMemTBB() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
       return false;
     return true;
   }
 
   bool isMemTBH() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
         Memory.Alignment != 0 )
       return false;
@@ -1438,13 +1621,13 @@
   }
 
   bool isMemRegOffset() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
+    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
       return false;
     return true;
   }
 
   bool isT2MemRegOffset() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
       return false;
     // Only lsl #{0, 1, 2, 3} allowed.
@@ -1458,7 +1641,7 @@
   bool isMemThumbRR() const {
     // Thumb reg+reg addressing is simple. Just two registers, a base and
     // an offset. No shifts, negations or any other complicating factors.
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
       return false;
     return isARMLowRegister(Memory.BaseRegNum) &&
@@ -1466,7 +1649,7 @@
   }
 
   bool isMemThumbRIs4() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 ||
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 124].
@@ -1476,7 +1659,7 @@
   }
 
   bool isMemThumbRIs2() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 ||
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 62].
@@ -1486,7 +1669,7 @@
   }
 
   bool isMemThumbRIs1() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 ||
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 31].
@@ -1496,7 +1679,7 @@
   }
 
   bool isMemThumbSPI() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 ||
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
       return false;
     // Immediate offset, multiple of 4 in range [0, 1020].
@@ -1511,7 +1694,7 @@
     // and we reject it.
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset a multiple of 4 in range [-1020, 1020].
     if (!Memory.OffsetImm) return true;
@@ -1520,9 +1703,24 @@
     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
            Val == std::numeric_limits<int32_t>::min();
   }
-
+  bool isMemImm7s4Offset() const {
+    // If we have an immediate that's not a constant, treat it as a label
+    // reference needing a fixup. If it is a constant, it's something else
+    // and we reject it.
+    if (isImm() && !isa<MCConstantExpr>(getImm()))
+      return true;
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset a multiple of 4 in range [-508, 508].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    // Special case, #-0 is INT32_MIN.
+    return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
+  }
   bool isMemImm0_1020s4Offset() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset a multiple of 4 in range [0, 1020].
     if (!Memory.OffsetImm) return true;
@@ -1531,7 +1729,7 @@
   }
 
   bool isMemImm8Offset() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base reg of PC isn't allowed for these encodings.
     if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1541,9 +1739,136 @@
     return (Val == std::numeric_limits<int32_t>::min()) ||
            (Val > -256 && Val < 256);
   }
+  bool isTMemImm7Shift0Offset() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(Memory.BaseRegNum))
+      return false;
+    // Immediate offset in range [-127, 127].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) || (Val > -128 && Val < 128);
+  }
+  bool isTMemImm7Shift1Offset() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(Memory.BaseRegNum))
+      return false;
+    // Immediate offset is multiple of 2 and in range [-254, 254].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) ||
+           (Val > -256 && Val < 256 && ((Val & 0x1) == 0));
+  }
+  bool isMemImm7Shift0Offset() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset in range [-127, 127].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) || (Val > -128 && Val < 128);
+  }
+  bool isMemImm7Shift1Offset() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset is multiple of 2 and in range [-254, 254].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) ||
+           (Val > -256 && Val < 256 && ((Val & 0x1) == 0));
+  }
+  bool isMemImm7Shift2Offset() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset is multiple of 4 in range [-508, 508].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) ||
+           (Val > -512 && Val < 512 && ((Val & 0x3) == 0));
+  }
+  bool isMemImm7Shift0OffsetWB() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset in range [-127, 127].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) || (Val > -128 && Val < 128);
+  }
+  bool isMemImm7Shift1OffsetWB() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset is multiple of 2 and in range [-254, 254].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) ||
+           (Val > -256 && Val < 256 && ((Val & 0x1) == 0));
+  }
+  bool isMemImm7Shift2OffsetWB() const {
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+        !ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    // Immediate offset is multiple of 4 in range [-508, 508].
+    if (!Memory.OffsetImm) return true;
+    int64_t Val = Memory.OffsetImm->getValue();
+    return (Val == INT32_MIN) ||
+           (Val > -512 && Val < 512 && ((Val & 0x3) == 0));
+  }
+  template <int shift> bool isMemRegRQOffset() const {
+    if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
+      return false;
+
+    if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+    if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+            Memory.OffsetRegNum))
+      return false;
+
+    if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
+      return false;
+
+    if (shift > 0 &&
+        (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
+      return false;
+
+    return true;
+  }
+
+  template <int shift> bool isMemRegQOffset() const {
+    if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+      return false;
+
+    if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+            Memory.BaseRegNum))
+      return false;
+
+    if(!Memory.OffsetImm) return true;
+    static_assert(shift < 56,
+                  "Such that we dont shift by a value higher than 62");
+    int64_t Val = Memory.OffsetImm->getValue();
+
+    // The value must be a multiple of (1 << shift)
+    if ((Val & ((1U << shift) - 1)) != 0)
+      return false;
+
+    // And be in the right range, depending on the amount that it is shifted
+    // by.  Shift 0, is equal to 7 unsigned bits, the sign bit is set
+    // separately.
+    int64_t Range = (1U << (7+shift)) - 1;
+    return (Val == INT32_MIN) || (Val > -Range && Val < Range);
+  }
 
   bool isMemPosImm8Offset() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 255].
     if (!Memory.OffsetImm) return true;
@@ -1552,7 +1877,7 @@
   }
 
   bool isMemNegImm8Offset() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Base reg of PC isn't allowed for these encodings.
     if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1564,7 +1889,7 @@
   }
 
   bool isMemUImm12Offset() const {
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 4095].
     if (!Memory.OffsetImm) return true;
@@ -1580,7 +1905,7 @@
     if (isImm() && !isa<MCConstantExpr>(getImm()))
       return true;
 
-    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [-4095, 4095].
     if (!Memory.OffsetImm) return true;
@@ -1631,6 +1956,12 @@
     return VectorList.Count == 1;
   }
 
+  bool isVecListTwoMQ() const {
+    return isSingleSpacedVectorList() && VectorList.Count == 2 &&
+           ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+               VectorList.RegNum);
+  }
+
   bool isVecListDPair() const {
     if (!isSingleSpacedVectorList()) return false;
     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
@@ -1664,6 +1995,12 @@
     return VectorList.Count == 4;
   }
 
+  bool isVecListFourMQ() const {
+    return isSingleSpacedVectorList() && VectorList.Count == 4 &&
+           ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+               VectorList.RegNum);
+  }
+
   bool isSingleSpacedVectorAllLanes() const {
     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
   }
@@ -1806,6 +2143,8 @@
     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
   }
 
+  bool isVectorIndex() const { return Kind == k_VectorIndex; }
+
   bool isVectorIndex8() const {
     if (Kind != k_VectorIndex) return false;
     return VectorIndex.Val < 8;
@@ -1825,6 +2164,30 @@
     return VectorIndex.Val < 1;
   }
 
+  template <int size>
+  bool isMVEVectorIndex() const {
+    if (Kind != k_VectorIndex) return false;
+    return VectorIndex.Val < size;
+  }
+
+  template<int start, int end>
+  bool isMVEPairVectorIndex() const {
+    if (Kind != k_VectorIndex) return false;
+    return VectorIndex.Val == start || VectorIndex.Val == end;
+  }
+
+  bool isMVEi64splat() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    // Must be a constant.
+    if (!CE) return false;
+    uint64_t Value = CE->getValue();
+    // i64 value with each byte being either 0 or 0xff.
+    for (unsigned i = 0 ; i < 8; ++i)
+      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
+    return true;
+  }
+
   bool isNEONi8splat() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
@@ -1992,6 +2355,51 @@
     return (Value % Angle == Remainder && Value <= 270);
   }
 
+  bool isMVELongShift() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    // Must be a constant.
+    if (!CE) return false;
+    uint64_t Value = CE->getValue();
+    return Value >= 1 && Value <= 32;
+  }
+
+  bool isITCondCodeNoAL() const {
+    if (!isITCondCode()) return false;
+    auto CC = (ARMCC::CondCodes) getCondCode();
+    return CC != ARMCC::AL;
+  }
+
+  bool isITCondCodeRestrictedI() const {
+    if (!isITCondCode())
+      return false;
+    ARMCC::CondCodes CC = (ARMCC::CondCodes)getCondCode();
+    return CC == ARMCC::EQ || CC == ARMCC::NE;
+  }
+
+  bool isITCondCodeRestrictedS() const {
+    if (!isITCondCode())
+      return false;
+    ARMCC::CondCodes CC = (ARMCC::CondCodes)getCondCode();
+    return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
+           CC == ARMCC::GE;
+  }
+
+  bool isITCondCodeRestrictedU() const {
+    if (!isITCondCode())
+      return false;
+    ARMCC::CondCodes CC = (ARMCC::CondCodes)getCondCode();
+    return CC == ARMCC::HS || CC == ARMCC::HI;
+  }
+
+  bool isITCondCodeRestrictedFP() const {
+    if (!isITCondCode())
+      return false;
+    ARMCC::CondCodes CC = (ARMCC::CondCodes)getCondCode();
+    return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
+           CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
+  }
+
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     // Add as immediates when possible.  Null MCExpr = 0.
     if (!Expr)
@@ -2019,6 +2427,30 @@
     Inst.addOperand(MCOperand::createReg(RegNum));
   }
 
+  void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
+    unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
+    Inst.addOperand(MCOperand::createReg(RegNum));
+  }
+
+  void addVPTPredROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 3 && "Invalid number of operands!");
+    addVPTPredNOperands(Inst, N-1);
+    unsigned RegNum;
+    if (getVPTPred() == ARMVCC::None) {
+      RegNum = 0;
+    } else {
+      unsigned NextOpIndex = Inst.getNumOperands();
+      const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
+      int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
+      assert(TiedOp >= 0 &&
+             "Inactive register in vpred_r is not tied to an output!");
+      RegNum = Inst.getOperand(TiedOp).getReg();
+    }
+    Inst.addOperand(MCOperand::createReg(RegNum));
+  }
+
   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(getCoproc()));
@@ -2044,6 +2476,11 @@
     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
   }
 
+  void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
+  }
+
   void addCCOutOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
@@ -2089,6 +2526,14 @@
       Inst.addOperand(MCOperand::createReg(*I));
   }
 
+  void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const SmallVectorImpl<unsigned> &RegList = getRegList();
+    for (SmallVectorImpl<unsigned>::const_iterator
+           I = RegList.begin(), E = RegList.end(); I != E; ++I)
+      Inst.addOperand(MCOperand::createReg(*I));
+  }
+
   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
     addRegListOperands(Inst, N);
   }
@@ -2097,6 +2542,14 @@
     addRegListOperands(Inst, N);
   }
 
+  void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
+    addRegListOperands(Inst, N);
+  }
+
+  void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
+    addRegListOperands(Inst, N);
+  }
+
   void addRotImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // Encoded as val>>3. The printer handles display as 8, 16, 24.
@@ -2184,6 +2637,38 @@
     Inst.addOperand(MCOperand::createImm(CE->getValue()));
   }
 
+  void addImm7s4Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
+    // instruction don't encode operands that way yet.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
+  void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
+  void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
+  void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
+  void addImm7Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate is scaled by four in the encoding and is stored
@@ -2293,7 +2778,7 @@
       return;
     }
 
-    assert(isMem()  && "Unknown value type!");
+    assert(isGPRMem()  && "Unknown value type!");
     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
   }
@@ -2318,6 +2803,21 @@
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
   }
 
+  void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+  }
+
+  void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+  }
+
+  void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+  }
+
   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     int32_t Imm = Memory.OffsetImm->getValue();
@@ -2519,7 +3019,23 @@
     Inst.addOperand(MCOperand::createImm(Val));
   }
 
-  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
+  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    // If we have an immediate that's not a constant, treat it as a label
+    // reference needing a fixup. If it is a constant, it's something else
+    // and we reject it.
+    if (isImm()) {
+      Inst.addOperand(MCOperand::createExpr(getImm()));
+      Inst.addOperand(MCOperand::createImm(0));
+      return;
+    }
+
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
@@ -2558,6 +3074,62 @@
     addMemImm8OffsetOperands(Inst, N);
   }
 
+  void addTMemImm7Shift0OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addTMemImm7Shift1OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift0OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift1OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift2OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift0OffsetWBOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift1OffsetWBOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
+  void addMemImm7Shift2OffsetWBOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If this is an immediate, it's a label reference.
@@ -2618,6 +3190,19 @@
     Inst.addOperand(MCOperand::createImm(Val));
   }
 
+  void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+  }
+
+  void addMemRegQOffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+    Inst.addOperand(MCOperand::createImm(Val));
+  }
+
   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 3 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
@@ -2699,6 +3284,12 @@
     Inst.addOperand(MCOperand::createImm(Imm));
   }
 
+  void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::createImm(CE->getValue()));
+  }
+
   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
@@ -2719,6 +3310,37 @@
     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
   }
 
+  void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+
+    // When we come here, the VectorList field will identify a range
+    // of q-registers by its base register and length, and it will
+    // have already been error-checked to be the expected length of
+    // range and contain only q-regs in the range q0-q7. So we can
+    // count on the base register being in the range q0-q6 (for 2
+    // regs) or q0-q4 (for 4)
+    //
+    // The MVE instructions taking a register range of this kind will
+    // need an operand in the QQPR or QQQQPR class, representing the
+    // entire range as a unit. So we must translate into that class,
+    // by finding the index of the base register in the MQPR reg
+    // class, and returning the super-register at the corresponding
+    // index in the target class.
+
+    const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
+    const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
+      &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
+      &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
+
+    unsigned I, E = RC_out->getNumRegs();
+    for (I = 0; I < E; I++)
+      if (RC_in->getRegister(I) == VectorList.RegNum)
+        break;
+    assert(I < E && "Invalid vector list start register!");
+
+    Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
+  }
+
   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
@@ -2745,6 +3367,26 @@
     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
   }
 
+  void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
+  }
+
+  void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
+  }
+
+  void addMVEi64splatOperands(MCInst &Inst, unsigned N) const {
+     assert(N == 1 && "Invalid number of operands!");
+     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+     uint64_t Value = CE->getValue();
+     unsigned Imm = 0;
+     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
+       Imm |= (Value & 1) << i;
+     Inst.addOperand(MCOperand::createImm(Imm));
+  }
+
   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate encodes the type of constant as well as the value.
@@ -2913,6 +3555,15 @@
     return Op;
   }
 
+  static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
+                                                   SMLoc S) {
+    auto Op = make_unique<ARMOperand>(k_VPTPred);
+    Op->VCC.Val = CC;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
     auto Op = make_unique<ARMOperand>(k_CoprocNum);
     Op->Cop.Val = CopVal;
@@ -3044,19 +3695,31 @@
     assert(Regs.size() > 0 && "RegList contains no registers?");
     KindTy Kind = k_RegisterList;
 
-    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
-      Kind = k_DPRRegisterList;
-    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
-             contains(Regs.front().second))
-      Kind = k_SPRRegisterList;
+    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
+            Regs.front().second)) {
+      if (Regs.back().second == ARM::VPR)
+        Kind = k_FPDRegisterListWithVPR;
+      else
+        Kind = k_DPRRegisterList;
+    } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
+                   Regs.front().second)) {
+      if (Regs.back().second == ARM::VPR)
+        Kind = k_FPSRegisterListWithVPR;
+      else
+        Kind = k_SPRRegisterList;
+    }
 
     // Sort based on the register encoding values.
     array_pod_sort(Regs.begin(), Regs.end());
 
+    if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
+      Kind = k_RegisterListWithAPSR;
+
     auto Op = make_unique<ARMOperand>(Kind);
     for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
            I = Regs.begin(), E = Regs.end(); I != E; ++I)
       Op->Registers.push_back(I->second);
+
     Op->StartLoc = StartLoc;
     Op->EndLoc = EndLoc;
     return Op;
@@ -3217,6 +3880,9 @@
   case k_CondCode:
     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
     break;
+  case k_VPTPred:
+    OS << "<ARMCC::" << ARMVPTPredToString(getVPTPred()) << ">";
+    break;
   case k_CCOut:
     OS << "<ccout " << RegName(getReg()) << ">";
     break;
@@ -3324,8 +3990,11 @@
        << ", width: " << Bitfield.Width << ">";
     break;
   case k_RegisterList:
+  case k_RegisterListWithAPSR:
   case k_DPRRegisterList:
-  case k_SPRRegisterList: {
+  case k_SPRRegisterList:
+  case k_FPSRegisterListWithVPR:
+  case k_FPDRegisterListWithVPR: {
     OS << "<register_list ";
 
     const SmallVectorImpl<unsigned> &RegList = getRegList();
@@ -3785,6 +4454,8 @@
     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
+  else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
+    RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
   else
     return Error(RegLoc, "invalid register in register list");
 
@@ -3838,6 +4509,20 @@
       Reg = getDRegFromQReg(Reg);
       isQReg = true;
     }
+    if (!RC->contains(Reg) &&
+        RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
+        ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
+      // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
+      // subset of GPRRegClassId except it contains APSR as well.
+      RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
+    }
+    if (Reg == ARM::VPR && (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
+                            RC == &ARMMCRegisterClasses[ARM::DPRRegClassID])) {
+      RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
+      EReg = MRI->getEncodingValue(Reg);
+      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
+      continue;
+    }
     // The register must be in the same register class as the first.
     if (!RC->contains(Reg))
       return Error(RegLoc, "invalid register in register list");
@@ -3845,7 +4530,7 @@
     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
         Warning(RegLoc, "register list not in ascending order");
-      else
+      else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
         return Error(RegLoc, "register list not in ascending order");
     }
     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
@@ -3855,6 +4540,7 @@
     }
     // VFP register lists must also be contiguous.
     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
+        RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
         Reg != OldReg + 1)
       return Error(RegLoc, "non-contiguous register range");
     EReg = MRI->getEncodingValue(Reg);
@@ -3944,7 +4630,7 @@
   // As an extension (to match gas), support a plain D register or Q register
   // (without encosing curly braces) as a single or double entry list,
   // respectively.
-  if (Parser.getTok().is(AsmToken::Identifier)) {
+  if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
     SMLoc E = Parser.getTok().getEndLoc();
     int Reg = tryParseRegister();
     if (Reg == -1)
@@ -4012,9 +4698,14 @@
   unsigned Count = 1;
   int Spacing = 0;
   unsigned FirstReg = Reg;
+
+  if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
+      Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
+      return MatchOperand_ParseFail;
+  }
   // The list is of D registers, but we also allow Q regs and just interpret
   // them as the two D sub-registers.
-  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
+  else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
     FirstReg = Reg = getDRegFromQReg(Reg);
     Spacing = 1; // double-spacing requires explicit D registers, otherwise
                  // it's ambiguous with four-register single spaced.
@@ -4044,14 +4735,17 @@
         return MatchOperand_ParseFail;
       }
       // Allow Q regs and just interpret them as the two D sub-registers.
-      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
+      if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
         EndReg = getDRegFromQReg(EndReg) + 1;
       // If the register is the same as the start reg, there's nothing
       // more to do.
       if (Reg == EndReg)
         continue;
       // The register must be in the same register class as the first.
-      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
+      if ((hasMVE() &&
+           !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
+          (!hasMVE() &&
+           !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
         Error(AfterMinusLoc, "invalid register in register list");
         return MatchOperand_ParseFail;
       }
@@ -4084,13 +4778,21 @@
       Error(RegLoc, "register expected");
       return MatchOperand_ParseFail;
     }
+
+    if (hasMVE()) {
+      if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
+        Error(RegLoc, "vector register in range Q0-Q7 expected");
+        return MatchOperand_ParseFail;
+      }
+      Spacing = 1;
+    }
     // vector register lists must be contiguous.
     // It's OK to use the enumeration values directly here rather, as the
     // VFP register classes have the enum sorted properly.
     //
     // The list is of D registers, but we also allow Q regs and just interpret
     // them as the two D sub-registers.
-    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
+    else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
       if (!Spacing)
         Spacing = 1; // Register range implies a single spaced list.
       else if (Spacing == 2) {
@@ -4153,7 +4855,7 @@
   case NoLanes:
     // Two-register operands have been converted to the
     // composite register classes.
-    if (Count == 2) {
+    if (Count == 2 && !hasMVE()) {
       const MCRegisterClass *RC = (Spacing == 1) ?
         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
@@ -4165,7 +4867,7 @@
   case AllLanes:
     // Two-register operands have been converted to the
     // composite register classes.
-    if (Count == 2) {
+    if (Count == 2 && !hasMVE()) {
       const MCRegisterClass *RC = (Spacing == 1) ?
         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
@@ -5061,6 +5763,21 @@
   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
 }
 
+void ARMAsmParser::cvtMVEVMOVQtoDReg(
+  MCInst &Inst, const OperandVector &Operands) {
+
+  // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
+  assert(Operands.size() == 8);
+
+  ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
+  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
+  ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
+  ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
+  // skip second copy of Qd in Operands[6]
+  ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
+  ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
+}
+
 /// Parse an ARM memory expression, return false if successful else return true
 /// or an error.  The first token must be a '[' when called.
 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
@@ -5275,6 +5992,8 @@
     St = ARM_AM::ror;
   else if (ShiftName == "rrx" || ShiftName == "RRX")
     St = ARM_AM::rrx;
+  else if (ShiftName == "uxtw" || ShiftName == "UXTW")
+    St= ARM_AM::uxtw;
   else
     return Error(Loc, "illegal shift operator");
   Parser.Lex(); // Eat shift type token.
@@ -5624,11 +6343,14 @@
 // FIXME: Would be nice to autogen this.
 // FIXME: This is a bit of a maze of special cases.
 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
+                                      StringRef ExtraToken,
                                       unsigned &PredicationCode,
+                                      unsigned &VPTPredicationCode,
                                       bool &CarrySetting,
                                       unsigned &ProcessorIMod,
                                       StringRef &ITMask) {
   PredicationCode = ARMCC::AL;
+  VPTPredicationCode = ARMVCC::None;
   CarrySetting = false;
   ProcessorIMod = 0;
 
@@ -5652,7 +6374,12 @@
       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
-      Mnemonic == "vfmal" || Mnemonic == "vfmsl")
+      Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
+      Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
+      Mnemonic == "csel" || Mnemonic == "csinc" ||
+      Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
+      Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
+      Mnemonic == "csetm")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
@@ -5660,7 +6387,17 @@
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
-      Mnemonic != "sbcs" && Mnemonic != "rscs") {
+      Mnemonic != "sbcs" && Mnemonic != "rscs" &&
+      !(hasMVE() &&
+        (Mnemonic.startswith("vcmult") || Mnemonic.startswith("vcmule") ||
+         Mnemonic.startswith("vmine") || Mnemonic.startswith("vmult") ||
+         (Mnemonic.startswith("vmule") && !Mnemonic.startswith("vmuleq")) ||
+         Mnemonic.startswith("vmvne") || Mnemonic.startswith("vorne") ||
+         Mnemonic.startswith("vpsel") || Mnemonic.startswith("vq") ||
+         Mnemonic.startswith("vrintne") || Mnemonic.startswith("vrshl") ||
+         Mnemonic.startswith("vshl") ||
+         (Mnemonic.startswith("vnege") && !Mnemonic.startswith("vnegeq")) ||
+         Mnemonic.startswith("vnegt")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
@@ -5680,7 +6417,8 @@
         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
-        Mnemonic == "bxns" || Mnemonic == "blxns" ||
+        Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
+        Mnemonic == "vmlas" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;
@@ -5701,12 +6439,36 @@
     }
   }
 
+  if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
+      Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
+      Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
+      Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
+      Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
+      Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
+      Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
+    unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
+    if (CC != ~0U) {
+      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
+      VPTPredicationCode = CC;
+    }
+    return Mnemonic;
+  }
+
   // The "it" instruction has the condition mask on the end of the mnemonic.
   if (Mnemonic.startswith("it")) {
     ITMask = Mnemonic.slice(2, Mnemonic.size());
     Mnemonic = Mnemonic.slice(0, 2);
   }
 
+  if (Mnemonic.startswith("vpst")) {
+    ITMask = Mnemonic.slice(4, Mnemonic.size());
+    Mnemonic = Mnemonic.slice(0, 4);
+  }
+  else if (Mnemonic.startswith("vpt")) {
+    ITMask = Mnemonic.slice(3, Mnemonic.size());
+    Mnemonic = Mnemonic.slice(0, 3);
+  }
+
   return Mnemonic;
 }
 
@@ -5714,9 +6476,14 @@
 /// inclusion of carry set or predication code operands.
 //
 // FIXME: It would be nice to autogen this.
-void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
+void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
+                                         StringRef ExtraToken,
+                                         StringRef FullInst,
                                          bool &CanAcceptCarrySet,
-                                         bool &CanAcceptPredicationCode) {
+                                         bool &CanAcceptPredicationCode,
+                                         bool &CanAcceptVPTPredicationCode) {
+  CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
+
   CanAcceptCarrySet =
       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
@@ -5745,7 +6512,18 @@
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
       Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
-      Mnemonic == "pssbb") {
+      Mnemonic == "pssbb" ||
+      Mnemonic == "bfcsel" || Mnemonic == "wls" ||
+      Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
+      Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
+      Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
+      Mnemonic == "cset" || Mnemonic == "csetm" ||
+      Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
+      (hasMVE() &&
+       (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
+        Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
+        Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
+        Mnemonic.startswith("letp")))) {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
@@ -5979,7 +6757,8 @@
                                               OperandVector &Operands) {
   // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
   unsigned RegIdx = 3;
-  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") &&
+  if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
+      Mnemonic == "vrintr") &&
       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
@@ -5997,6 +6776,48 @@
   return false;
 }
 
+bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
+                                                    OperandVector &Operands) {
+  if (!hasMVE() || Operands.size() < 3)
+    return true;
+
+  if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
+      Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
+    return true;
+
+  if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
+    return false;
+
+  if (Mnemonic.startswith("vmov") &&
+      !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
+        Mnemonic.startswith("vmovx"))) {
+    for (auto &Operand : Operands) {
+      if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
+          ((*Operand).isReg() &&
+           (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
+                (*Operand).getReg()) ||
+            ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
+                (*Operand).getReg())))) {
+        return true;
+      }
+    }
+    return false;
+  } else {
+    for (auto &Operand : Operands) {
+      // We check both QPR and MQPR to more accurately report errors when
+      // using Q registers outside of the allowed range.
+      if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
+          (Operand->isReg() &&
+           (ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
+                Operand->getReg()) ||
+            ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
+                Operand->getReg()))))
+        return false;
+    }
+    return true;
+  }
+}
+
 static bool isDataTypeToken(StringRef Tok) {
   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
@@ -6037,7 +6858,7 @@
 
   if (!Op2.isReg())
     return;
-  if (!Op3.isMem())
+  if (!Op3.isGPRMem())
     return;
 
   const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
@@ -6088,14 +6909,16 @@
   // Create the leading tokens for the mnemonic, split by '.' characters.
   size_t Start = 0, Next = Name.find('.');
   StringRef Mnemonic = Name.slice(Start, Next);
+  StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
 
   // Split out the predication code and carry setting flag from the mnemonic.
   unsigned PredicationCode;
+  unsigned VPTPredicationCode;
   unsigned ProcessorIMod;
   bool CarrySetting;
   StringRef ITMask;
-  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
-                           ProcessorIMod, ITMask);
+  Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
+                           CarrySetting, ProcessorIMod, ITMask);
 
   // In Thumb1, only the branch (B) instruction can be predicated.
   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
@@ -6109,10 +6932,15 @@
   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
   // where the conditional bit0 is zero, the instruction post-processing
   // will adjust the mask accordingly.
-  if (Mnemonic == "it") {
-    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
+  if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
+      Mnemonic.startswith("vpst")) {
+    SMLoc Loc = Mnemonic == "it"  ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
+                Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
+                                    SMLoc::getFromPointer(NameLoc.getPointer() + 4);
     if (ITMask.size() > 3) {
-      return Error(Loc, "too many conditions on IT instruction");
+      if (Mnemonic == "it")
+        return Error(Loc, "too many conditions on IT instruction");
+      return Error(Loc, "too many conditions on VPT instruction");
     }
     unsigned Mask = 8;
     for (unsigned i = ITMask.size(); i != 0; --i) {
@@ -6121,7 +6949,7 @@
         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
       }
       Mask >>= 1;
-      if (ITMask[i - 1] == 't')
+      if (ITMask[i - 1] == (Mnemonic.startswith("vp") ? 'e' : 't'))
         Mask |= 8;
     }
     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
@@ -6137,8 +6965,9 @@
   // ConditionCode operands to match the mnemonic "as written" and then we let
   // the matcher deal with finding the right instruction or generating an
   // appropriate error.
-  bool CanAcceptCarrySet, CanAcceptPredicationCode;
-  getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
+  bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
+  getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
+                        CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
 
   // If we had a carry-set on an instruction that can't do that, issue an
   // error.
@@ -6153,6 +6982,13 @@
                  "' is not predicable, but condition code specified");
   }
 
+  // If we had a VPT predication code on an instruction that can't do that, issue an
+  // error.
+  if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
+    return Error(NameLoc, "instruction '" + Mnemonic +
+                 "' is not VPT predicable, but VPT code T/E is specified");
+  }
+
   // Add the carry setting operand, if necessary.
   if (CanAcceptCarrySet) {
     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
@@ -6165,7 +7001,24 @@
     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
                                       CarrySetting);
     Operands.push_back(ARMOperand::CreateCondCode(
-                         ARMCC::CondCodes(PredicationCode), Loc));
+                       ARMCC::CondCodes(PredicationCode), Loc));
+  }
+
+  // Add the VPT predication code operand, if necessary.
+  // FIXME: We don't add them for the instructions filtered below as these can
+  // have custom operands which need special parsing.  This parsing requires
+  // the operand to be in the same place in the OperandVector as their
+  // definition in tblgen.  Since these instructions may also have the
+  // scalar predication operand we do not add the vector one and leave until
+  // now to fix it up.
+  if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
+      !Mnemonic.startswith("vcmp") &&
+      !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
+        Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
+    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
+                                      CarrySetting);
+    Operands.push_back(ARMOperand::CreateVPTPred(
+                         ARMVCC::VPTCodes(VPTPredicationCode), Loc));
   }
 
   // Add the processor imod operand, if necessary.
@@ -6181,7 +7034,7 @@
   while (Next != StringRef::npos) {
     Start = Next;
     Next = Name.find('.', Start + 1);
-    StringRef ExtraToken = Name.slice(Start, Next);
+    ExtraToken = Name.slice(Start, Next);
 
     // Some NEON instructions have an optional datatype suffix that is
     // completely ignored. Check for that.
@@ -6237,57 +7090,174 @@
 
   // Some instructions have the same mnemonic, but don't always
   // have a predicate. Distinguish them here and delete the
-  // predicate if needed.
+  // appropriate predicate if needed.  This could be either the scalar
+  // predication code or the vector predication code.
   if (PredicationCode == ARMCC::AL &&
       shouldOmitPredicateOperand(Mnemonic, Operands))
     Operands.erase(Operands.begin() + 1);
 
-  // ARM mode 'blx' need special handling, as the register operand version
-  // is predicable, but the label operand version is not. So, we can't rely
-  // on the Mnemonic based checking to correctly figure out when to put
-  // a k_CondCode operand in the list. If we're trying to match the label
-  // version, remove the k_CondCode operand here.
-  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
-      static_cast<ARMOperand &>(*Operands[2]).isImm())
-    Operands.erase(Operands.begin() + 1);
 
-  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
-  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
-  // a single GPRPair reg operand is used in the .td file to replace the two
-  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
-  // expressed as a GPRPair, so we have to manually merge them.
-  // FIXME: We would really like to be able to tablegen'erate this.
-  if (!isThumb() && Operands.size() > 4 &&
-      (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
-       Mnemonic == "stlexd")) {
-    bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
-    unsigned Idx = isLoad ? 2 : 3;
-    ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
-    ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
-
-    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
-    // Adjust only if Op1 and Op2 are GPRs.
-    if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
-        MRC.contains(Op2.getReg())) {
-      unsigned Reg1 = Op1.getReg();
-      unsigned Reg2 = Op2.getReg();
-      unsigned Rt = MRI->getEncodingValue(Reg1);
-      unsigned Rt2 = MRI->getEncodingValue(Reg2);
-
-      // Rt2 must be Rt + 1 and Rt must be even.
-      if (Rt + 1 != Rt2 || (Rt & 1)) {
-        return Error(Op2.getStartLoc(),
-                     isLoad ? "destination operands must be sequential"
-                            : "source operands must be sequential");
+  if (hasMVE()) {
+    if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
+        PredicationCode == ARMCC::LT &&
+        Mnemonic.startswith("vmov")) {
+      // Very nasty hack to deal with the vector predicated variant of vmovlt
+      // the scalar predicated vmov with condition 'lt'.  We can not tell them
+      // apart until we have parsed their operands.
+      Operands.erase(Operands.begin() + 1);
+      Operands.erase(Operands.begin());
+      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+      SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
+                                         Mnemonic.size() - 1 + CarrySetting);
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
+    } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
+               !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+      // Another nasty hack to deal with the ambiguity between vcvt with scalar
+      // predication 'ne' and vcvtn with vector predication 'e'.  As above we
+      // can only distinguish between the two after we have parsed their
+      // operands.
+      Operands.erase(Operands.begin() + 1);
+      Operands.erase(Operands.begin());
+      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+      SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
+                                         Mnemonic.size() - 1 + CarrySetting);
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
+    } else if (Mnemonic.startswith("vmul") && PredicationCode == ARMCC::LT &&
+               !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+      // Another hack, this time to distinguish between scalar predicated vmul
+      // with 'lt' predication code and the vector instruction vmullt with
+      // vector predication code "none"
+      Operands.erase(Operands.begin() + 1);
+      Operands.erase(Operands.begin());
+      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
+    }
+    // For vmov and vcmp, as mentioned earlier, we did not add the vector
+    // predication code, since these may contain operands that require
+    // special parsing.  So now we have to see if they require vector
+    // predication and replace the scalar one with the vector predication
+    // operand if that is the case.
+    else if ((Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
+              (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
+               !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
+               !Mnemonic.startswith("vcvtm")))) {
+      if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+        // We could not split the vector predicate off vcvt because it might
+        // have been the scalar vcvtt instruction.  Now we know its a vector
+        // instruction, we still need to check whether its the vector
+        // predicated vcvt with 'Then' predication or the vector vcvtt.  We can
+        // distinguish the two based on the suffixes, if it is any of
+        // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
+        if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
+          auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
+          auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
+          if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
+              Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
+            Operands.erase(Operands.begin());
+            SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+            VPTPredicationCode = ARMVCC::Then;
+
+            Mnemonic = Mnemonic.substr(0, 4);
+            Operands.insert(Operands.begin(),
+                            ARMOperand::CreateToken(Mnemonic, MLoc));
+          }
+        }
+        Operands.erase(Operands.begin() + 1);
+        SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
+                                          Mnemonic.size() + CarrySetting);
+        Operands.insert(Operands.begin() + 1,
+                        ARMOperand::CreateVPTPred(
+                            ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
+      }
+    } else if (CanAcceptVPTPredicationCode) {
+      // For all other instructions, make sure only one of the two
+      // predication operands is left behind, depending on whether we should
+      // use the vector predication.
+      if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+        if (CanAcceptPredicationCode)
+          Operands.erase(Operands.begin() + 2);
+        else
+          Operands.erase(Operands.begin() + 1);
+      } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
+        Operands.erase(Operands.begin() + 1);
       }
-      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
-          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
-      Operands[Idx] =
-          ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
-      Operands.erase(Operands.begin() + Idx + 1);
     }
   }
 
+  if (VPTPredicationCode != ARMVCC::None) {
+    bool usedVPTPredicationCode = false;
+    for (unsigned I = 1; I < Operands.size(); ++I)
+      if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
+        usedVPTPredicationCode = true;
+    if (!usedVPTPredicationCode) {
+      // If we have a VPT predication code and we haven't just turned it
+      // into an operand, then it was a mistake for splitMnemonic to
+      // separate it from the rest of the mnemonic in the first place,
+      // and this may lead to wrong disassembly (e.g. scalar floating
+      // point VCMPE is actually a different instruction from VCMP, so
+      // we mustn't treat them the same). In that situation, glue it
+      // back on.
+      Mnemonic = Name.slice(0, Mnemonic.size() + 1);
+      Operands.erase(Operands.begin());
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(Mnemonic, NameLoc));
+    }
+  }
+
+    // ARM mode 'blx' need special handling, as the register operand version
+    // is predicable, but the label operand version is not. So, we can't rely
+    // on the Mnemonic based checking to correctly figure out when to put
+    // a k_CondCode operand in the list. If we're trying to match the label
+    // version, remove the k_CondCode operand here.
+    if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
+        static_cast<ARMOperand &>(*Operands[2]).isImm())
+      Operands.erase(Operands.begin() + 1);
+
+    // Adjust operands of ldrexd/strexd to MCK_GPRPair.
+    // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
+    // a single GPRPair reg operand is used in the .td file to replace the two
+    // GPRs. However, when parsing from asm, the two GRPs cannot be
+    // automatically
+    // expressed as a GPRPair, so we have to manually merge them.
+    // FIXME: We would really like to be able to tablegen'erate this.
+    if (!isThumb() && Operands.size() > 4 &&
+        (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
+         Mnemonic == "stlexd")) {
+      bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
+      unsigned Idx = isLoad ? 2 : 3;
+      ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
+      ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
+
+      const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
+      // Adjust only if Op1 and Op2 are GPRs.
+      if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
+          MRC.contains(Op2.getReg())) {
+        unsigned Reg1 = Op1.getReg();
+        unsigned Reg2 = Op2.getReg();
+        unsigned Rt = MRI->getEncodingValue(Reg1);
+        unsigned Rt2 = MRI->getEncodingValue(Reg2);
+
+        // Rt2 must be Rt + 1 and Rt must be even.
+        if (Rt + 1 != Rt2 || (Rt & 1)) {
+          return Error(Op2.getStartLoc(),
+                       isLoad ? "destination operands must be sequential"
+                              : "source operands must be sequential");
+        }
+        unsigned NewReg = MRI->getMatchingSuperReg(
+            Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
+        Operands[Idx] =
+            ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
+        Operands.erase(Operands.begin() + Idx + 1);
+      }
+  }
+
   // GNU Assembler extension (compatibility).
   fixupGNULDRDAlias(Mnemonic, Operands);
 
@@ -6446,6 +7416,17 @@
   return false;
 }
 
+static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
+  for (unsigned i = 0; i < MCID.NumOperands; ++i) {
+    if (ARM::isVpred(MCID.OpInfo[i].OperandType))
+      return i;
+  }
+  return -1;
+}
+
+static bool isVectorPredicable(const MCInstrDesc &MCID) {
+  return findFirstVectorPredOperandIdx(MCID) != -1;
+}
 
 // FIXME: We would really like to be able to tablegen'erate this.
 bool ARMAsmParser::validateInstruction(MCInst &Inst,
@@ -6477,7 +7458,8 @@
   } else if (isThumbTwo() && MCID.isPredicable() &&
              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
-             Inst.getOpcode() != ARM::t2Bcc) {
+             Inst.getOpcode() != ARM::t2Bcc &&
+             Inst.getOpcode() != ARM::t2BFic) {
     return Error(Loc, "predicated instructions must be in IT block");
   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
@@ -6503,6 +7485,30 @@
     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
   }
 
+  if (inVPTBlock() && !instIsBreakpoint(Inst)) {
+    unsigned Bit = 0;
+    if (VPTState.CurPosition != 0)
+      Bit = (VPTState.Mask >> (5 - VPTState.CurPosition)) & 1;
+    if (!isVectorPredicable(MCID))
+      return Error(Loc, "instruction in VPT block must be predicable");
+    unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
+    unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
+    if (Pred != VPTPred) {
+      SMLoc PredLoc;
+      for (unsigned I = 1; I < Operands.size(); ++I)
+        if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
+          PredLoc = Operands[I]->getStartLoc();
+      return Error(PredLoc, "incorrect predication in VPT block; got '" +
+                   StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
+                   "', but expected '" +
+                   ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
+    }
+  }
+  else if (hasMVE() && isVectorPredicable(MCID) &&
+           Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
+           ARMVCC::None)
+    return Error(Loc, "VPT predicated instructions must be in VPT block");
+
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
   case ARM::t2IT: {
@@ -6625,6 +7631,63 @@
                    "destination register and base register can't be identical");
     return false;
   }
+
+  case ARM::MVE_VLDRBU8noShift:
+  case ARM::MVE_VLDRBU16noShift:
+  case ARM::MVE_VLDRBS16noShift:
+  case ARM::MVE_VLDRBU32noShift:
+  case ARM::MVE_VLDRBS32noShift:
+  case ARM::MVE_VLDRHU16Shift:
+  case ARM::MVE_VLDRHU16noShift:
+  case ARM::MVE_VLDRHU32Shift:
+  case ARM::MVE_VLDRHU32noShift:
+  case ARM::MVE_VLDRHS32Shift:
+  case ARM::MVE_VLDRHS32noShift:
+  case ARM::MVE_VLDRWU32Shift:
+  case ARM::MVE_VLDRWU32noShift:
+  case ARM::MVE_VLDRDU64Shift:
+  case ARM::MVE_VLDRDU64noShift: {
+    // Qd must be different from Qm.
+    const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(0).getReg());
+    const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
+
+    if (Qd == Qm) {
+      return Error(Operands[3]->getStartLoc(),
+                   "destination vector register and vector offset register "
+                   "can't be identical");
+    }
+    return false;
+  }
+
+  case ARM::MVE_VLDRWU32NoWriteBack:
+  case ARM::MVE_VLDRDU64NoWriteBack: {
+    // Qd must be different from Qm.
+    const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(0).getReg());
+    const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(1).getReg());
+
+    if (Qd == Qm) {
+      return Error(Operands[3]->getStartLoc(),
+                   "destination vector register and vector pointer register "
+                   "can't be identical");
+    }
+    return false;
+  }
+
+  case ARM::MVE_VLDRWU32WriteBack:
+  case ARM::MVE_VLDRDU64WriteBack: {
+    // Qd must be different from Qm.
+    // NOTE: The first operand is a junk writeback operand that isn't used.
+    const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(1).getReg());
+    const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
+
+    if (Qd == Qm) {
+      return Error(Operands[3]->getStartLoc(),
+                   "destination vector register and vector pointer register "
+                   "can't be identical");
+    }
+    return false;
+  }
+
   case ARM::SBFX:
   case ARM::t2SBFX:
   case ARM::UBFX:
@@ -6861,6 +7924,81 @@
                                                "code specified");
     break;
   }
+  case ARM::t2WLS:
+  case ARM::MVE_WLSTP8:
+  case ARM::MVE_WLSTP16:
+  case ARM::MVE_WLSTP32:
+  case ARM::MVE_WLSTP64: {
+    int idx = Opcode == ARM::t2WLS ? 3 : 4;
+    if (!static_cast<ARMOperand &>(*Operands[idx]).isUnsignedOffset<11, 1>())
+      return Error(Operands[idx]->getStartLoc(),
+                   "loop end is out of range or not a positive multiple of 2");
+    break;
+  }
+  case ARM::t2LEUpdate:
+  case ARM::MVE_LEUpdateTP: {
+    if (Inst.getOperand(2).isImm() &&
+        !(Inst.getOperand(2).getImm() < 0 &&
+          Inst.getOperand(2).getImm() >= -4094 &&
+          (Inst.getOperand(2).getImm() & 1) == 0))
+      return Error(Operands[2]->getStartLoc(),
+                   "loop start is out of range or not a negative multiple of 2");
+    break;
+  }
+  case ARM::t2BFi:
+  case ARM::t2BFr:
+  case ARM::t2BFLi:
+  case ARM::t2BFLr: {
+    if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
+        (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
+      return Error(Operands[2]->getStartLoc(),
+                   "branch location out of range or not a multiple of 2");
+
+    if (Opcode == ARM::t2BFi) {
+      if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
+        return Error(Operands[3]->getStartLoc(),
+                     "branch target out of range or not a multiple of 2");
+    } else if (Opcode == ARM::t2BFLi) {
+      if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
+        return Error(Operands[3]->getStartLoc(),
+                     "branch target out of range or not a multiple of 2");
+    }
+    break;
+  }
+  case ARM::t2BFic: {
+    if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
+        (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
+      return Error(Operands[1]->getStartLoc(),
+                   "branch location out of range or not a multiple of 2");
+
+    if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
+      return Error(Operands[2]->getStartLoc(),
+                   "branch target out of range or not a multiple of 2");
+
+    assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
+           "branch location and else branch target should either both be "
+           "immediates or both labels");
+
+    if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
+      int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
+      if (Diff != 4 && Diff != 2)
+        return Error(
+            Operands[3]->getStartLoc(),
+            "else branch target must be 2 or 4 greater than the branch location");
+    }
+  }
+  case ARM::t2CLRM: {
+    for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
+      if (Inst.getOperand(i).isReg() &&
+          !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
+              Inst.getOperand(i).getReg())) {
+        return Error(Operands[2]->getStartLoc(),
+                     "invalid register in register list. Valid registers are "
+                     "r0-r12, lr/r14 and APSR.");
+      }
+    }
+    break;
+  }
   case ARM::DSB:
   case ARM::t2DSB: {
 
@@ -6908,6 +8046,47 @@
                    "list of registers must be at least 1 and at most 16");
     break;
   }
+  case ARM::VQDMULLt1s32bh:
+  case ARM::VQDMULLt1s32th:
+  case ARM::VCMULt1f32:
+  case ARM::VMULLt1s32bh:
+  case ARM::VMULLt1s32th:
+  case ARM::VMULLt1u32bh:
+  case ARM::VMULLt1u32th:
+  case ARM::VQDMLADHt1xs32:
+  case ARM::VQDMLADHt1s32:
+  case ARM::VQDMLADHt2xs32:
+  case ARM::VQDMLADHt2s32:
+  case ARM::VQDMLSDHt1xs32:
+  case ARM::VQDMLSDHt1s32:
+  case ARM::VQDMLSDHt2xs32:
+  case ARM::VQDMLSDHt2s32: {
+    if (Operands[3]->getReg() == Operands[4]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qn register can't be identical");
+    }
+    if (Operands[3]->getReg() == Operands[5]->getReg()) {
+      return Error (Operands[3]->getStartLoc(),
+                    "Qd register and Qm register can't be identical");
+    }
+    break;
+  }
+  case ARM::VMOVt1qtodreg: {
+    if (Operands[4]->getReg() != Operands[6]->getReg())
+      return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
+    if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
+        static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
+      return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
+    break;
+  }
+  case ARM::VMOVt1dregtoq: {
+    if (Operands[2]->getReg() != Operands[4]->getReg())
+      return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
+    if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
+        static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
+      return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
+    break;
+  }
   }
 
   return false;
@@ -7184,6 +8363,50 @@
   }
 
   switch (Inst.getOpcode()) {
+  case ARM::VORNIZ0v4i32:
+  case ARM::VORNIZ0v8i16:
+  case ARM::VORNIZ8v4i32:
+  case ARM::VORNIZ8v8i16:
+  case ARM::VORNIZ16v4i32:
+  case ARM::VORNIZ24v4i32:
+  case ARM::VANDIZ0v4i32:
+  case ARM::VANDIZ0v8i16:
+  case ARM::VANDIZ8v4i32:
+  case ARM::VANDIZ8v8i16:
+  case ARM::VANDIZ16v4i32:
+  case ARM::VANDIZ24v4i32: {
+    unsigned Opcode;
+    bool imm16 = false;
+    switch(Inst.getOpcode()) {
+    case ARM::VORNIZ0v4i32: Opcode = ARM::VORRIZ0v4i32; break;
+    case ARM::VORNIZ0v8i16: Opcode = ARM::VORRIZ0v8i16; imm16 = true; break;
+    case ARM::VORNIZ8v4i32: Opcode = ARM::VORRIZ8v4i32; break;
+    case ARM::VORNIZ8v8i16: Opcode = ARM::VORRIZ8v8i16; imm16 = true; break;
+    case ARM::VORNIZ16v4i32: Opcode = ARM::VORRIZ16v4i32; break;
+    case ARM::VORNIZ24v4i32: Opcode = ARM::VORRIZ24v4i32; break;
+    case ARM::VANDIZ0v4i32: Opcode = ARM::VBICIZ0v4i32; break;
+    case ARM::VANDIZ0v8i16: Opcode = ARM::VBICIZ0v8i16; imm16 = true; break;
+    case ARM::VANDIZ8v4i32: Opcode = ARM::VBICIZ8v4i32; break;
+    case ARM::VANDIZ8v8i16: Opcode = ARM::VBICIZ8v8i16; imm16 = true; break;
+    case ARM::VANDIZ16v4i32: Opcode = ARM::VBICIZ16v4i32; break;
+    case ARM::VANDIZ24v4i32: Opcode = ARM::VBICIZ24v4i32; break;
+    default: llvm_unreachable("unexpected opcode");
+    }
+
+    MCInst TmpInst;
+    TmpInst.setOpcode(Opcode);
+    TmpInst.addOperand(Inst.getOperand(0));
+    TmpInst.addOperand(Inst.getOperand(1));
+
+    // invert immediate
+    unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff);
+    TmpInst.addOperand(MCOperand::createImm(imm));
+
+    TmpInst.addOperand(Inst.getOperand(3));
+    TmpInst.addOperand(Inst.getOperand(4));
+    Inst = TmpInst;
+    return true;
+  }
   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
   case ARM::LDRT_POST:
   case ARM::LDRBT_POST: {
@@ -9090,6 +10313,35 @@
       return true;
     }
     return false;
+  case ARM::t2VPST:
+  case ARM::t2VPTv16i8:
+  case ARM::t2VPTv8i16:
+  case ARM::t2VPTv4i32:
+  case ARM::t2VPTv16u8:
+  case ARM::t2VPTv8u16:
+  case ARM::t2VPTv4u32:
+  case ARM::t2VPTv16s8:
+  case ARM::t2VPTv8s16:
+  case ARM::t2VPTv4s32:
+  case ARM::t2VPTv4f32:
+  case ARM::t2VPTv8f16:
+  case ARM::t2VPTv16i8r:
+  case ARM::t2VPTv8i16r:
+  case ARM::t2VPTv4i32r:
+  case ARM::t2VPTv16u8r:
+  case ARM::t2VPTv8u16r:
+  case ARM::t2VPTv4u32r:
+  case ARM::t2VPTv16s8r:
+  case ARM::t2VPTv8s16r:
+  case ARM::t2VPTv4s32r:
+  case ARM::t2VPTv4f32r:
+  case ARM::t2VPTv8f16r: {
+    assert(!inVPTBlock() && "Nested VPT blocks are not allowed");
+    MCOperand &MO = Inst.getOperand(0);
+    VPTState.Mask = MO.getImm();
+    VPTState.CurPosition = 0;
+    break;
+  }
   }
   return false;
 }
@@ -9154,11 +10406,29 @@
       return Match_RequiresV8;
   }
 
-  // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
-  // ARMv8-A.
-  if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
-      Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
-    return Match_InvalidOperand;
+  switch (Inst.getOpcode()) {
+  case ARM::VMRS:
+  case ARM::VMSR:
+  case ARM::VMRS_FPCXTS:
+  case ARM::VMRS_FPCXTNS:
+  case ARM::VMSR_FPCXTS:
+  case ARM::VMSR_FPCXTNS:
+  case ARM::VMRS_FPSCR_NZCVQC:
+  case ARM::VMSR_FPSCR_NZCVQC:
+  case ARM::FMSTAT:
+  case ARM::VMRS_VPR:
+  case ARM::VMRS_P0:
+  case ARM::VMSR_VPR:
+  case ARM::VMSR_P0:
+    // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
+    // ARMv8-A.
+    if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
+        (isThumb() && !hasV8Ops()))
+      return Match_InvalidOperand;
+    break;
+  default:
+    break;
+  }
 
   for (unsigned I = 0; I < MCID.NumOperands; ++I)
     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
@@ -9183,6 +10453,10 @@
 // Returns true if Inst is unpredictable if it is in and IT block, but is not
 // the last instruction in the block.
 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
+
+  if (Inst.getOpcode() == ARM::tSVC)
+    return false;
+
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
 
   // All branch & call instructions terminate IT blocks with the exception of
@@ -9312,6 +10586,7 @@
       // Still progress the IT block, otherwise one wrong condition causes
       // nasty cascading errors.
       forwardITPosition();
+      forwardVPTPosition();
       return true;
     }
 
@@ -9338,6 +10613,7 @@
     // and process gets a consistent answer about whether we're in an IT
     // block.
     forwardITPosition();
+    forwardVPTPosition();
 
     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
     // doesn't actually encode.
@@ -10693,6 +11969,28 @@
         if (CE->getValue() == 0)
           return Match_Success;
     break;
+  case MCK__35_8:
+    if (Op.isImm())
+      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
+        if (CE->getValue() == 8)
+          return Match_Success;
+    break;
+  case MCK__35_16:
+    if (Op.isImm())
+      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
+        if (CE->getValue() == 16)
+          return Match_Success;
+    break;
+  case MCK_Imm:
+    if (Op.isImm()) {
+      const MCExpr *SOExpr = Op.getImm();
+      int64_t Value;
+      if (!SOExpr->evaluateAsAbsolute(Value))
+        return Match_Success;
+      assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
+             "expression value must be representable in 32 bits");
+    }
+    break;
   case MCK_ModImm:
     if (Op.isImm()) {
       const MCExpr *SOExpr = Op.getImm();
@@ -10716,3 +12014,76 @@
   }
   return Match_InvalidOperand;
 }
+
+bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
+                                           StringRef ExtraToken) {
+  if (!hasMVE())
+    return false;
+
+  return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
+         Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
+         Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
+         Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
+         Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
+         Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
+         Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
+         Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
+         Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
+         Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
+         Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
+         Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
+         Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
+         Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
+         Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
+         Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
+         Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
+         Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
+         Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
+         Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
+         Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
+         Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
+         Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
+         Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
+         Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
+         Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
+         Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
+         Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
+         Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
+         Mnemonic.startswith("vqabs") ||
+         (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
+         Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
+         Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
+         Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
+         Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
+         Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
+         Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
+         Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
+         Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
+         Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
+         Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
+         Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
+         Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
+         Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
+         Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
+         Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
+         Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
+         Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
+         Mnemonic.startswith("vldrb") ||
+         (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
+         (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
+         Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
+         Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
+         Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
+         Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
+         Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
+         Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
+         Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
+         Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
+         Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
+         Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
+         Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
+         Mnemonic.startswith("vcvt") ||
+         (Mnemonic.startswith("vmov") &&
+          !(ExtraToken == ".f16" || ExtraToken == ".32" ||
+            ExtraToken == ".16" || ExtraToken == ".8"));
+}
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6,6 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "ARMBaseInstrInfo.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "MCTargetDesc/ARMMCTargetDesc.h"
@@ -86,6 +87,47 @@
       std::vector<unsigned char> ITStates;
   };
 
+  class VPTStatus
+  {
+    public:
+      unsigned getVPTPred() {
+        unsigned Pred = ARMVCC::None;
+        if (instrInVPTBlock())
+          Pred = VPTStates.back();
+        return Pred;
+      }
+
+      void advanceVPTState() {
+        VPTStates.pop_back();
+      }
+
+      bool instrInVPTBlock() {
+        return !VPTStates.empty();
+      }
+
+      bool instrLastInVPTBlock() {
+        return VPTStates.size() == 1;
+      }
+
+      void setVPTState(char Mask) {
+        // (3 - the number of trailing zeros) is the number of then / else.
+        unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
+        assert(NumTZ <= 3 && "Invalid VPT mask!");
+        // push predicates onto the stack the correct order for the pops
+        for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
+          bool T = ((Mask >> Pos) & 1) == 0;
+          if (T)
+            VPTStates.push_back(ARMVCC::Then);
+          else
+            VPTStates.push_back(ARMVCC::Else);
+        }
+        VPTStates.push_back(ARMVCC::Then);
+      }
+
+    private:
+      std::vector<unsigned char> VPTStates;
+  };
+
 /// ARM disassembler for all ARM platforms.
 class ARMDisassembler : public MCDisassembler {
 public:
@@ -117,6 +159,7 @@
 
 private:
   mutable ITStatus ITBlock;
+  mutable VPTStatus VPTBlock;
 
   DecodeStatus AddThumbPredicate(MCInst&) const;
   void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
@@ -143,18 +186,29 @@
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
+static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
+                                               unsigned RegNo, uint64_t Address,
+                                               const void *Decoder);
 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -173,6 +227,12 @@
                                                 const void *Decoder);
 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
@@ -263,6 +323,10 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveModImmInstruction(MCInst &Inst,unsigned Val,
+                               uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveVADCInstruction(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
@@ -277,6 +341,11 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
@@ -325,6 +394,8 @@
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
                                 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
                                                        unsigned Val,
                                                        uint64_t Address,
@@ -360,14 +431,28 @@
                                uint64_t Address, const void* Decoder);
 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
+                                           uint64_t Address,
+                                           const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
+                               uint64_t Address, const void *Decoder);
+template<int shift, int WriteBack>
+static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
@@ -410,6 +495,95 @@
 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
                                          uint64_t Address, const void *Decoder);
 
+template <bool isSigned, bool isNeg, int size>
+static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
+                                         uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
+                                               uint64_t Address,
+                                               const void *Decoder);
+static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
+static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const void *Decoder);
+static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
+                                           uint64_t Address,
+                                           const void *Decoder);
+static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder);
+static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
+                                         uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
+                                                     uint64_t Address,
+                                                     const void *Decoder);
+static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
+                                                     uint64_t Address,
+                                                     const void *Decoder);
+static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
+                                                     uint64_t Address,
+                                                     const void *Decoder);
+static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
+                                                       unsigned Val,
+                                                       uint64_t Address,
+                                                       const void *Decoder);
+static DecodeStatus DecodeVCMLARotOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
+static DecodeStatus DecodeVCADDRotOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
+static DecodeStatus DecodeVSTRVLDR_SYSREG_off(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const void *Decoder);
+static DecodeStatus DecodeVSTRVLDR_SYSREG_pre(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const void *Decoder);
+static DecodeStatus DecodeVSTRVLDR_SYSREG_post(MCInst &Inst, unsigned Insn,
+                                              uint64_t Address,
+                                              const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder);
+template<int shift>
+static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder);
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
+template <int shift>
+static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
+                                             uint64_t Address,
+                                             const void *Decoder);
+template <int shift, int size>
+static DecodeStatus DecodeInvertedExpandedImmOperand(
+    MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder);
+template<unsigned size>
+static DecodeStatus DecodeMVEVectorIndexOperand(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const void *Decoder);
+template<unsigned start>
+static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
+                                                    uint64_t Address,
+                                                    const void *Decoder);
+static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEVSHLL(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                   const void *Decoder);
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                      const void *Decoder);
+static DecodeStatus DecodeMveVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                   const void *Decoder);
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                   const void *Decoder);
+static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                                const void *Decoder);
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
@@ -570,6 +744,16 @@
   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
 }
 
+static bool isVectorPredicable(unsigned Opcode) {
+  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
+  for (unsigned i = 0; i < NumOps; ++i) {
+    if (ARM::isVpred(OpInfo[i].OperandType))
+      return true;
+  }
+  return false;
+}
+
 // Most Thumb instructions don't have explicit predicates in the
 // encoding, but rather get their predicates from IT context.  We need
 // to fix up the predicate operands using this context information as a
@@ -617,39 +801,66 @@
       break;
   }
 
-  // If we're in an IT block, base the predicate on that.  Otherwise,
+  // Warn on non-VPT predicable instruction in a VPT block and a VPT
+  // predicable instruction in an IT block
+  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
+       (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
+    S = SoftFail;
+
+  // If we're in an IT/VPT block, base the predicate on that.  Otherwise,
   // assume a predicate of AL.
-  unsigned CC;
-  CC = ITBlock.getITCC();
-  if (CC == 0xF)
-    CC = ARMCC::AL;
-  if (ITBlock.instrInITBlock())
+  unsigned CC = ARMCC::AL;
+  unsigned VCC = ARMVCC::None;
+  if (ITBlock.instrInITBlock()) {
+    CC = ITBlock.getITCC();
     ITBlock.advanceITState();
+  } else if (VPTBlock.instrInVPTBlock()) {
+    VCC = VPTBlock.getVPTPred();
+    VPTBlock.advanceVPTState();
+  }
 
   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
-  MCInst::iterator I = MI.begin();
-  for (unsigned i = 0; i < NumOps; ++i, ++I) {
-    if (I == MI.end()) break;
-    if (OpInfo[i].isPredicate()) {
-      if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
-        Check(S, SoftFail);
-      I = MI.insert(I, MCOperand::createImm(CC));
-      ++I;
-      if (CC == ARMCC::AL)
-        MI.insert(I, MCOperand::createReg(0));
-      else
-        MI.insert(I, MCOperand::createReg(ARM::CPSR));
-      return S;
-    }
+
+  MCInst::iterator CCI = MI.begin();
+  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
+    if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
   }
 
-  I = MI.insert(I, MCOperand::createImm(CC));
-  ++I;
-  if (CC == ARMCC::AL)
-    MI.insert(I, MCOperand::createReg(0));
-  else
-    MI.insert(I, MCOperand::createReg(ARM::CPSR));
+  if (ARMInsts[MI.getOpcode()].isPredicable()) {
+    CCI = MI.insert(CCI, MCOperand::createImm(CC));
+    ++CCI;
+    if (CC == ARMCC::AL)
+      MI.insert(CCI, MCOperand::createReg(0));
+    else
+      MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
+  } else if (CC != ARMCC::AL) {
+    Check(S, SoftFail);
+  }
+
+  MCInst::iterator VCCI = MI.begin();
+  unsigned VCCPos;
+  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
+    if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
+  }
+
+  if (isVectorPredicable(MI.getOpcode())) {
+    VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
+    ++VCCI;
+    if (VCC == ARMVCC::None)
+      MI.insert(VCCI, MCOperand::createReg(0));
+    else
+      MI.insert(VCCI, MCOperand::createReg(ARM::P0));
+    if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
+      int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
+        VCCPos + 2, MCOI::TIED_TO);
+      assert(TiedOp >= 0 &&
+             "Inactive register in vpred_r is not tied to an output!");
+      MI.insert(VCCI, MI.getOperand(TiedOp));
+    }
+  } else if (VCC != ARMVCC::None) {
+    Check(S, SoftFail);
+  }
 
   return S;
 }
@@ -667,6 +878,10 @@
     CC = ARMCC::AL;
   if (ITBlock.instrInITBlock())
     ITBlock.advanceITState();
+  else if (VPTBlock.instrInVPTBlock()) {
+    CC = VPTBlock.getVPTPred();
+    VPTBlock.advanceVPTState();
+  }
 
   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
   MCInst::iterator I = MI.begin();
@@ -757,6 +972,27 @@
 
   uint32_t Insn32 =
       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
+
+  Result =
+      decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
+  if (Result != MCDisassembler::Fail) {
+    Size = 4;
+
+    // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
+    // the VPT predicate.
+    if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
+      Result = MCDisassembler::SoftFail;
+
+    Check(Result, AddThumbPredicate(MI));
+
+    if (isVPTOpcode(MI.getOpcode())) {
+      unsigned Mask = MI.getOperand(0).getImm();
+      VPTBlock.setVPTState(Mask);
+    }
+
+    return Result;
+  }
+
   Result =
       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
   if (Result != MCDisassembler::Fail) {
@@ -879,6 +1115,13 @@
   ARM::R12, ARM::SP, ARM::LR, ARM::PC
 };
 
+static const uint16_t CLRMGPRDecoderTable[] = {
+  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
+  ARM::R12, 0, ARM::LR, ARM::APSR
+};
+
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 15)
@@ -889,6 +1132,20 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 15)
+    return MCDisassembler::Fail;
+
+  unsigned Register = CLRMGPRDecoderTable[RegNo];
+  if (Register == 0)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus
 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
                            uint64_t Address, const void *Decoder) {
@@ -917,6 +1174,24 @@
   return S;
 }
 
+static DecodeStatus
+DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
+                             uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (RegNo == 15)
+  {
+    Inst.addOperand(MCOperand::createReg(ARM::ZR));
+    return MCDisassembler::Success;
+  }
+
+  if (RegNo == 13)
+    S = MCDisassembler::SoftFail;
+
+  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+  return S;
+}
+
 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   if (RegNo > 7)
@@ -988,6 +1263,17 @@
   return S;
 }
 
+static DecodeStatus Decodet2rGPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (RegNo == 13 || RegNo == 15)
+    Check(S, MCDisassembler::SoftFail);
+
+  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+  return S;
+}
+
 static const uint16_t SPRDecoderTable[] = {
      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
@@ -1226,6 +1512,7 @@
 
   bool NeedDisjointWriteback = false;
   unsigned WritebackReg = 0;
+  bool CLRM = false;
   switch (Inst.getOpcode()) {
   default:
     break;
@@ -1240,17 +1527,26 @@
     NeedDisjointWriteback = true;
     WritebackReg = Inst.getOperand(0).getReg();
     break;
+  case ARM::t2CLRM:
+    CLRM = true;
+    break;
   }
 
   // Empty register lists are not allowed.
   if (Val == 0) return MCDisassembler::Fail;
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
-      if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
-        return MCDisassembler::Fail;
-      // Writeback not allowed if Rn is in the target list.
-      if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
-        Check(S, MCDisassembler::SoftFail);
+      if (CLRM) {
+        if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
+          return MCDisassembler::Fail;
+        }
+      } else {
+        if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
+          return MCDisassembler::Fail;
+        // Writeback not allowed if Rn is in the target list.
+        if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
+          Check(S, MCDisassembler::SoftFail);
+      }
     }
   }
 
@@ -1343,6 +1639,8 @@
   unsigned imm = fieldFromInstruction(Insn, 0, 8);
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned U = fieldFromInstruction(Insn, 23, 1);
+  const FeatureBitset &featureBits =
+    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
 
   switch (Inst.getOpcode()) {
     case ARM::LDC_OFFSET:
@@ -1377,15 +1675,42 @@
     case ARM::t2STCL_PRE:
     case ARM::t2STCL_POST:
     case ARM::t2STCL_OPTION:
-      if (coproc == 0xA || coproc == 0xB)
+    case ARM::t2LDC2_OFFSET:
+    case ARM::t2LDC2L_OFFSET:
+    case ARM::t2LDC2_PRE:
+    case ARM::t2LDC2L_PRE:
+    case ARM::t2STC2_OFFSET:
+    case ARM::t2STC2L_OFFSET:
+    case ARM::t2STC2_PRE:
+    case ARM::t2STC2L_PRE:
+    case ARM::LDC2_OFFSET:
+    case ARM::LDC2L_OFFSET:
+    case ARM::LDC2_PRE:
+    case ARM::LDC2L_PRE:
+    case ARM::STC2_OFFSET:
+    case ARM::STC2L_OFFSET:
+    case ARM::STC2_PRE:
+    case ARM::STC2L_PRE:
+    case ARM::t2LDC2_OPTION:
+    case ARM::t2STC2_OPTION:
+    case ARM::t2LDC2_POST:
+    case ARM::t2LDC2L_POST:
+    case ARM::t2STC2_POST:
+    case ARM::t2STC2L_POST:
+    case ARM::LDC2_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2_POST:
+    case ARM::STC2L_POST:
+      if (coproc == 0xA || coproc == 0xB ||
+          (featureBits[ARM::HasV8_1MMainlineOps] &&
+           (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
+            coproc == 0xE || coproc == 0xF)))
         return MCDisassembler::Fail;
       break;
     default:
       break;
   }
 
-  const FeatureBitset &featureBits =
-    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
     return MCDisassembler::Fail;
 
@@ -3166,6 +3491,62 @@
   return S;
 }
 
+static DecodeStatus
+DecodeMveModImmInstruction(MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned imm = fieldFromInstruction(Insn, 0, 4);
+  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
+  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
+  imm |= cmode                             << 8;
+  imm |= fieldFromInstruction(Insn, 5, 1)  << 12;
+
+  if (cmode == 0xF && Inst.getOpcode() == ARM::VMVNimmi32)
+    return MCDisassembler::Fail;
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(imm));
+
+  // Might be more than vmov immediate.
+
+  Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+  Inst.addOperand(MCOperand::createReg(0));
+  Inst.addOperand(MCOperand::createImm(0));
+
+  return S;
+}
+
+static DecodeStatus DecodeMveVADCInstruction(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = fieldFromInstruction(Insn, 13, 3);
+  Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+
+  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
+  Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  unsigned Qm = fieldFromInstruction(Insn, 1, 3);
+  Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
+    Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+  Inst.addOperand(MCOperand::createImm(Qd));
+
+  return S;
+}
+
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
@@ -3722,6 +4103,21 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
+                                   const void *Decoder) {
+  if (Val == 0)
+    Inst.addOperand(MCOperand::createImm(INT32_MIN));
+  else {
+    int imm = Val & 0x7F;
+
+    if (!(Val & 0x80))
+      imm *= -1;
+    Inst.addOperand(MCOperand::createImm(imm * 4));
+  }
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
@@ -3737,6 +4133,22 @@
   return S;
 }
 
+static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
+                                           uint64_t Address,
+                                           const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rn = fieldFromInstruction(Val, 8, 4);
+  unsigned imm = fieldFromInstruction(Val, 0, 8);
+
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
@@ -3764,6 +4176,21 @@
   return MCDisassembler::Success;
 }
 
+template<int shift>
+static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
+                         uint64_t Address, const void *Decoder) {
+  int imm = Val & 0x7F;
+  if (Val == 0)
+    imm = INT32_MIN;
+  else if (!(Val & 0x80))
+    imm *= -1;
+  if (imm != INT32_MIN)
+    imm <<= shift;
+  Inst.addOperand(MCOperand::createImm(imm));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
@@ -3810,27 +4237,64 @@
   return S;
 }
 
-static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+template<int shift>
+static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
+                                         uint64_t Address,
+                                         const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
-  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
-  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
-  unsigned addr = fieldFromInstruction(Insn, 0, 8);
-  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
-  addr |= Rn << 9;
-  unsigned load = fieldFromInstruction(Insn, 20, 1);
+  unsigned Rn = fieldFromInstruction(Val, 8, 3);
+  unsigned imm =
+      fieldFromInstruction(Val, 0, 8);
 
-  if (Rn == 15) {
-    switch (Inst.getOpcode()) {
-    case ARM::t2LDR_PRE:
-    case ARM::t2LDR_POST:
-      Inst.setOpcode(ARM::t2LDRpci);
-      break;
-    case ARM::t2LDRB_PRE:
-    case ARM::t2LDRB_POST:
-      Inst.setOpcode(ARM::t2LDRBpci);
-      break;
+  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+template<int shift, int WriteBack>
+static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
+                                         uint64_t Address,
+                                         const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rn = fieldFromInstruction(Val, 8, 4);
+  unsigned imm = fieldFromInstruction(Val, 0, 8);
+  if (WriteBack) {
+    if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+      return MCDisassembler::Fail;
+  } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
+                                    uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
+  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  unsigned addr = fieldFromInstruction(Insn, 0, 8);
+  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
+  addr |= Rn << 9;
+  unsigned load = fieldFromInstruction(Insn, 20, 1);
+
+  if (Rn == 15) {
+    switch (Inst.getOpcode()) {
+    case ARM::t2LDR_PRE:
+    case ARM::t2LDR_POST:
+      Inst.setOpcode(ARM::t2LDRpci);
+      break;
+    case ARM::t2LDRB_PRE:
+    case ARM::t2LDRB_POST:
+      Inst.setOpcode(ARM::t2LDRBpci);
+      break;
     case ARM::t2LDRH_PRE:
     case ARM::t2LDRH_POST:
       Inst.setOpcode(ARM::t2LDRHpci);
@@ -3957,6 +4421,43 @@
   return S;
 }
 
+static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
+                             uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Rn = fieldFromInstruction(Insn, 3, 4);
+  unsigned Qm = fieldFromInstruction(Insn, 0, 3);
+
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+template<int shift>
+static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
+                             uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Qm = fieldFromInstruction(Insn, 8, 3);
+  int imm = fieldFromInstruction(Insn, 0, 7);
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  if(!fieldFromInstruction(Insn, 7, 1)) {
+    if (imm == 0)
+      imm = INT32_MIN;                 // indicate -0
+    else
+      imm *= -1;
+  }
+  if (imm != INT32_MIN)
+    imm <<= shift;
+  Inst.addOperand(MCOperand::createImm(imm));
+
+  return S;
+}
+
 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
@@ -3992,6 +4493,13 @@
   if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
     return MCDisassembler::Fail;
 
+  // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should
+  // decode as VFP/MVE instructions.
+  if (featureBits[ARM::HasV8_1MMainlineOps] &&
+      ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA ||
+       (Val & 0xE) == 0xE))
+    return MCDisassembler::Fail;
+
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
@@ -5357,14 +5865,37 @@
       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
   DecodeStatus S = MCDisassembler::Success;
 
-  unsigned Rt = fieldFromInstruction(Val, 12, 4);
+  // Add explicit operand for the destination sysreg, for cases where
+  // we have to model it for code generation purposes.
+  switch (Inst.getOpcode()) {
+  case ARM::VMSR_FPSCR_NZCVQC:
+    Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+    break;
+  case ARM::VMSR_P0:
+    Inst.addOperand(MCOperand::createReg(ARM::VPR));
+    break;
+  }
 
-  if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
-    if (Rt == 13 || Rt == 15)
-      S = MCDisassembler::SoftFail;
-    Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
-  } else
-    Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+  if (Inst.getOpcode() != ARM::FMSTAT) {
+    unsigned Rt = fieldFromInstruction(Val, 12, 4);
+
+    if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
+      if (Rt == 13 || Rt == 15)
+        S = MCDisassembler::SoftFail;
+      Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+    } else
+      Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+  }
+
+  // Add explicit operand for the source sysreg, similarly to above.
+  switch (Inst.getOpcode()) {
+  case ARM::VMRS_FPSCR_NZCVQC:
+    Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
+    break;
+  case ARM::VMRS_P0:
+    Inst.addOperand(MCOperand::createReg(ARM::VPR));
+    break;
+  }
 
   if (featureBits[ARM::ModeThumb]) {
     Inst.addOperand(MCOperand::createImm(ARMCC::AL));
@@ -5377,3 +5908,881 @@
 
   return S;
 }
+
+template <bool isSigned, bool isNeg, int size>
+static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
+                                         uint64_t Address,
+                                         const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  if (Val == 0)
+    S = MCDisassembler::SoftFail;
+
+  uint64_t DecVal;
+  if (isSigned)
+    DecVal = SignExtend32<size + 1>(Val << 1);
+  else
+    DecVal = (Val << 1);
+
+  if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
+                                Decoder))
+    Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
+  return S;
+}
+
+static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+
+  uint64_t LocImm = Inst.getOperand(0).getImm();
+  Val = LocImm + (2 << Val);
+  if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
+                                Decoder))
+    Inst.addOperand(MCOperand::createImm(Val));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  if (Val >= ARMCC::AL)  // also exclude the non-condition NV
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createImm(Val));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                 const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Inst.getOpcode() == ARM::MVE_LCTP)
+    return S;
+
+  unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
+                 fieldFromInstruction(Insn, 1, 10) << 1;
+  switch (Inst.getOpcode()) {
+  case ARM::t2LEUpdate:
+  case ARM::MVE_LEUpdateTP:
+    Inst.addOperand(MCOperand::createReg(ARM::LR));
+    Inst.addOperand(MCOperand::createReg(ARM::LR));
+  case ARM::t2LE:
+    if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address,
+                                                        Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  case ARM::t2WLS:
+  case ARM::MVE_WLSTP8:
+  case ARM::MVE_WLSTP16:
+  case ARM::MVE_WLSTP32:
+  case ARM::MVE_WLSTP64:
+    Inst.addOperand(MCOperand::createReg(ARM::LR));
+    if (!Check(S,
+               DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
+                                       Address, Decoder)) ||
+        !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address,
+                                                         Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  case ARM::t2DLS:
+  case ARM::MVE_DLSTP8:
+  case ARM::MVE_DLSTP16:
+  case ARM::MVE_DLSTP32:
+  case ARM::MVE_DLSTP64:
+    unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+    if (Rn == 0xF) {
+      // Enforce all the rest of the instruction bits in LCTP, which
+      // won't have been reliably checked based on LCTP's own tablegen
+      // record, because we came to this decode by a roundabout route.
+      uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
+      if ((Insn & ~SBZMask) != CanonicalLCTP)
+        return MCDisassembler::Fail;   // a mandatory bit is wrong: hard fail
+      if (Insn != CanonicalLCTP)
+        Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
+
+      Inst.setOpcode(ARM::MVE_LCTP);
+    } else {
+      Inst.addOperand(MCOperand::createReg(ARM::LR));
+      if (!Check(S, DecoderGPRRegisterClass(Inst,
+                                            fieldFromInstruction(Insn, 16, 4),
+                                            Address, Decoder)))
+        return MCDisassembler::Fail;
+    }
+    break;
+  }
+  return S;
+}
+
+static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
+                                           uint64_t Address,
+                                           const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val == 0)
+    Val = 32;
+
+  Inst.addOperand(MCOperand::createImm(Val));
+
+  return S;
+}
+
+static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  if ((RegNo) + 1 > 11)
+    return MCDisassembler::Fail;
+
+  unsigned Register = GPRDecoderTable[(RegNo) + 1];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  if ((RegNo) > 14)
+    return MCDisassembler::Fail;
+
+  unsigned Register = GPRDecoderTable[(RegNo)];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+  Inst.addOperand(MCOperand::createReg(0));
+  if (Inst.getOpcode() == ARM::VSCCLRMD) {
+    unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
+                       (fieldFromInstruction(Insn, 12, 4) << 8) |
+                       (fieldFromInstruction(Insn, 22, 1) << 12);
+    if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
+      return MCDisassembler::Fail;
+    }
+  } else {
+    unsigned reglist = fieldFromInstruction(Insn, 0, 8) |
+                       (fieldFromInstruction(Insn, 22, 1) << 8) |
+                       (fieldFromInstruction(Insn, 12, 4) << 9);
+    if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
+      return MCDisassembler::Fail;
+    }
+  }
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+
+  return S;
+}
+
+static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                              uint64_t Address,
+                              const void *Decoder) {
+  if (RegNo > 7)
+    return MCDisassembler::Fail;
+
+  unsigned Register = QPRDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static const uint16_t QQPRDecoderTable[] = {
+     ARM::Q0_Q1,  ARM::Q1_Q2,  ARM::Q2_Q3,  ARM::Q3_Q4,
+     ARM::Q4_Q5,  ARM::Q5_Q6,  ARM::Q6_Q7
+};
+
+static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                              uint64_t Address,
+                              const void *Decoder) {
+  if (RegNo > 6)
+    return MCDisassembler::Fail;
+
+  unsigned Register = QQPRDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static const uint16_t QQQQPRDecoderTable[] = {
+     ARM::Q0_Q1_Q2_Q3,  ARM::Q1_Q2_Q3_Q4,  ARM::Q2_Q3_Q4_Q5,
+     ARM::Q3_Q4_Q5_Q6,  ARM::Q4_Q5_Q6_Q7
+};
+
+static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
+                              uint64_t Address,
+                              const void *Decoder) {
+  if (RegNo > 4)
+    return MCDisassembler::Fail;
+
+  unsigned Register = QQQQPRDecoderTable[RegNo];
+  Inst.addOperand(MCOperand::createReg(Register));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
+                                         uint64_t Address,
+                                         const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  // Parse VPT mask and encode it in the MCInst as an immediate with the same
+  // format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1 and
+  // 't' as 0 and finish with a 1.
+  unsigned Imm = 0;
+  // We always start with a 't'.
+  unsigned CurBit = 0;
+  for (int i = 3; i >= 0; --i) {
+    // If the bit we are looking at is not the same as last one, invert the
+    // CurBit, if it is the same leave it as is.
+    CurBit ^= (Val >> i) & 1U;
+
+    // Encode the CurBit at the right place in the immediate.
+    Imm |= (CurBit << i);
+
+    // If we are done, finish the encoding with a 1.
+    if ((Val & ~(~0U << i)) == 0) {
+      Imm |= 1U << i;
+      break;
+    }
+  }
+
+  Inst.addOperand(MCOperand::createImm(Imm));
+
+  return S;
+}
+
+static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
+                                        uint64_t Address, const void *Decoder) {
+  // The vpred_r operand type includes an MQPR register field derived
+  // from the encoding. But we don't actually want to add an operand
+  // to the MCInst at this stage, because AddThumbPredicate will do it
+  // later, and will infer the register number from the TIED_TO
+  // constraint. So this is a deliberately empty decoder method that
+  // will inhibit the auto-generated disassembly code from adding an
+  // operand at all.
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
+                                                      unsigned Val,
+                                                      uint64_t Address,
+                                                      const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
+                                                      unsigned Val,
+                                                      uint64_t Address,
+                                                      const void *Decoder) {
+  unsigned Code;
+  switch (Val & 0x3) {
+  case 0:
+    Code = ARMCC::GE;
+    break;
+  case 1:
+    Code = ARMCC::LT;
+    break;
+  case 2:
+    Code = ARMCC::GT;
+    break;
+  case 3:
+    Code = ARMCC::LE;
+    break;
+  }
+  Inst.addOperand(MCOperand::createImm(Code));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
+                                                      unsigned Val,
+                                                      uint64_t Address,
+                                                      const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
+                                                     uint64_t Address,
+                                                     const void *Decoder) {
+  unsigned Code;
+  switch (Val) {
+  default:
+    return MCDisassembler::Fail;
+  case 0:
+    Code = ARMCC::EQ;
+    break;
+  case 1:
+    Code = ARMCC::NE;
+    break;
+  case 4:
+    Code = ARMCC::GE;
+    break;
+  case 5:
+    Code = ARMCC::LT;
+    break;
+  case 6:
+    Code = ARMCC::GT;
+    break;
+  case 7:
+    Code = ARMCC::LE;
+    break;
+  }
+
+  Inst.addOperand(MCOperand::createImm(Code));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeVCMLARotOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val > 3)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Val * 90));
+
+  return S;
+}
+
+static DecodeStatus DecodeVCADDRotOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val > 3)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Val == 0 ? 90 : 270));
+
+  return S;
+}
+
+static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
+                                         uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned DecodedVal = 64 - Val;
+
+  switch (Inst.getOpcode()) {
+  case ARM::VCVTt1f16s16:
+  case ARM::VCVTt1s16f16:
+  case ARM::VCVTt1f16u16:
+  case ARM::VCVTt1u16f16:
+    if (DecodedVal > 16)
+      return MCDisassembler::Fail;
+  case ARM::VCVTt1f32s32:
+  case ARM::VCVTt1s32f32:
+  case ARM::VCVTt1f32u32:
+  case ARM::VCVTt1u32f32:
+    if (DecodedVal > 32)
+      return MCDisassembler::Fail;
+  }
+
+  Inst.addOperand(MCOperand::createImm(64 - Val));
+
+  return S;
+}
+
+static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
+  switch (Opcode) {
+  case ARM::VSTR_P0_off:
+  case ARM::VSTR_P0_pre:
+  case ARM::VSTR_P0_post:
+  case ARM::VLDR_P0_off:
+  case ARM::VLDR_P0_pre:
+  case ARM::VLDR_P0_post:
+    return ARM::P0;
+  default:
+    return 0;
+  }
+}
+
+static DecodeStatus DecodeVSTRVLDR_SYSREG_off(MCInst &Inst, unsigned Val,
+                                              uint64_t Address,
+                                              const void *Decoder) {
+  switch (Inst.getOpcode()) {
+  case ARM::VSTR_FPSCR_off:
+  case ARM::VSTR_FPSCR_NZCVQC_off:
+  case ARM::VLDR_FPSCR_off:
+  case ARM::VLDR_FPSCR_NZCVQC_off:
+    const FeatureBitset &featureBits =
+        ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
+
+    if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
+      return MCDisassembler::Fail;
+  }
+
+  DecodeStatus S = MCDisassembler::Success;
+  if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
+    Inst.addOperand(MCOperand::createReg(Sysreg));
+  unsigned Rn = fieldFromInstruction(Val, 16, 4);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+  if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+  Inst.addOperand(MCOperand::createReg(0));
+
+  return S;
+}
+
+static DecodeStatus DecodeVSTRVLDR_SYSREG_pre(MCInst &Inst, unsigned Val,
+                                              uint64_t Address,
+                                              const void *Decoder) {
+  switch (Inst.getOpcode()) {
+  case ARM::VSTR_FPSCR_pre:
+  case ARM::VSTR_FPSCR_NZCVQC_pre:
+  case ARM::VLDR_FPSCR_pre:
+  case ARM::VLDR_FPSCR_NZCVQC_pre:
+    const FeatureBitset &featureBits =
+        ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
+
+    if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
+      return MCDisassembler::Fail;
+  }
+
+  DecodeStatus S = MCDisassembler::Success;
+  if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
+    Inst.addOperand(MCOperand::createReg(Sysreg));
+  unsigned Rn = fieldFromInstruction(Val, 16, 4);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+  Inst.addOperand(MCOperand::createReg(0));
+
+  return S;
+}
+
+static DecodeStatus DecodeVSTRVLDR_SYSREG_post(MCInst &Inst, unsigned Val,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  switch (Inst.getOpcode()) {
+  case ARM::VSTR_FPSCR_post:
+  case ARM::VSTR_FPSCR_NZCVQC_post:
+  case ARM::VLDR_FPSCR_post:
+  case ARM::VLDR_FPSCR_NZCVQC_post:
+    const FeatureBitset &featureBits =
+        ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
+
+    if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
+      return MCDisassembler::Fail;
+  }
+
+  DecodeStatus S = MCDisassembler::Success;
+  if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
+    Inst.addOperand(MCOperand::createReg(Sysreg));
+  unsigned Rn = fieldFromInstruction(Val, 16, 4);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(ARMCC::AL));
+  Inst.addOperand(MCOperand::createReg(0));
+
+  return S;
+}
+
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = fieldFromInstruction(Val, 13, 3);
+  unsigned Rn = fieldFromInstruction(Val, 16, 3);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeTAddrModeImm7<shift>(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = fieldFromInstruction(Val, 13, 3);
+  unsigned Rn = fieldFromInstruction(Val, 16, 4);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
+
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeT2AddrModeImm7<shift,1>(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+template <int shift>
+static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
+                                        uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = fieldFromInstruction(Val, 13, 3);
+  unsigned Qm = fieldFromInstruction(Val, 17, 3);
+  unsigned addr = fieldFromInstruction(Val, 0, 7) |
+                  (fieldFromInstruction(Val, 23, 1) << 7) | (Qm << 8);
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMveAddrModeQ<shift>(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val > 3)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(1 << Val));
+  return S;
+}
+
+template <int shift>
+static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+    Val <<= shift;
+
+    Inst.addOperand(MCOperand::createImm(Val));
+    return MCDisassembler::Success;
+}
+
+template <int shift, int size>
+static DecodeStatus DecodeInvertedExpandedImmOperand(
+    MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) {
+    Val <<= shift;
+    Val ^= (((uint64_t)1) << size) - 1;
+
+    Inst.addOperand(MCOperand::createImm(Val));
+    return MCDisassembler::Success;
+}
+
+template<unsigned size>
+static DecodeStatus DecodeMVEVectorIndexOperand(MCInst &Inst, unsigned Val,
+                                                uint64_t Address,
+                                                const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  static_assert((size == 1 || size == 2 || size == 4), "Size must be 1, 2 or 4.");
+
+  unsigned Imm = 0;
+  unsigned Beat = ((Val >> 2) & 1) | ((Val >> 3) & 2);
+  if (size == 4)
+    Imm = Val & 3;
+  else if (size == 2)
+    Imm = (Val >> 1) & 1;
+
+  Imm += size * Beat;
+
+  Inst.addOperand(MCOperand::createImm(Imm));
+
+  return S;
+}
+
+template<unsigned start>
+static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
+                                                    uint64_t Address,
+                                                    const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  Inst.addOperand(MCOperand::createImm(start + Val));
+
+  return S;
+}
+
+static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
+  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned index = fieldFromInstruction(Insn, 4, 1);
+
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
+                                         uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
+  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned index = fieldFromInstruction(Insn, 4, 1);
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodeMVEVSHLL(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                   const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned U = fieldFromInstruction(Insn, 28, 1);
+  unsigned T = fieldFromInstruction(Insn, 12, 1);
+  unsigned Qd = (fieldFromInstruction(Insn, 22, 1) << 3) | fieldFromInstruction(Insn, 13, 3);
+  unsigned Qm = (fieldFromInstruction(Insn, 5, 1) << 3) | fieldFromInstruction(Insn, 1, 3);
+  unsigned szimm5 = fieldFromInstruction(Insn, 16, 5);
+  unsigned size16 = szimm5 < 16 ? 0 : 1;
+
+  // Depending on the (U)nsignedness, (T)op or bottom and size of the element
+  // (size16) we pick different Opcodes.  We do this using an array of opcodes
+  // and the index of each opcode can be decoded usin U * 4 + T * 2 + size16.
+  unsigned opcodes[] = {ARM::t1VSHLLs8bh,  ARM::t1VSHLLs16bh, ARM::t1VSHLLs8th,
+                        ARM::t1VSHLLs16th, ARM::t1VSHLLu8bh,  ARM::t1VSHLLu16bh,
+                        ARM::t1VSHLLu8th,  ARM::t1VSHLLu16th};
+  Inst.setOpcode(opcodes[U*4+T*2+size16]);
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  // To decode the immediate we subtract the size of the element.
+  unsigned Imm = szimm5 - size16 * 8 - 8;
+  Inst.addOperand(MCOperand::createImm(Imm));
+
+  Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+  Inst.addOperand(MCOperand::createReg(0));
+
+  return S;
+}
+
+static DecodeStatus DecodeMVEOverlappingLongShift(
+  MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
+  unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
+  unsigned Rm = fieldFromInstruction(Insn, 12, 4);
+
+  if (RdaHi == 14) {
+    // This value of RdaHi (really indicating pc, because RdaHi has to
+    // be an odd-numbered register, so the low bit will be set by the
+    // decode function below) indicates that we must decode as SQRSHR
+    // or UQRSHL, which both have a single Rda register field with all
+    // four bits.
+    unsigned Rda = fieldFromInstruction(Insn, 16, 4);
+
+    switch (Inst.getOpcode()) {
+      case ARM::t2ASRLr:
+      case ARM::t2SQRSHRL:
+        Inst.setOpcode(ARM::t2SQRSHR);
+        break;
+      case ARM::t2LSLLr:
+      case ARM::t2UQRSHLL:
+        Inst.setOpcode(ARM::t2UQRSHL);
+        break;
+      default:
+        llvm_unreachable("Unexpected starting opcode!");
+    }
+
+    // Rda as output parameter
+    if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+      return MCDisassembler::Fail;
+
+    // Rda again as input parameter
+    if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+      return MCDisassembler::Fail;
+
+    // Rm, the amount to shift by
+    if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+      return MCDisassembler::Fail;
+
+    return S;
+  }
+
+  // Otherwise, we decode as whichever opcode our caller has already
+  // put into Inst. Those all look the same:
+
+  // RdaLo,RdaHi as output parameters
+  if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  // RdaLo,RdaHi again as input parameters
+  if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  // Rm, the amount to shift by
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                      const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
+                 fieldFromInstruction(Insn, 1, 3));
+  unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus DecodeMveVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+  unsigned Qn = fieldFromInstruction(Insn, 17, 3);
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  unsigned cond_type;
+  unsigned scalar = 0;
+  switch (Inst.getOpcode()) {
+  case ARM::VCMPt2f16:
+  case ARM::VCMPt2f32:
+    scalar = 1;
+  case ARM::VCMPt1f16:
+  case ARM::VCMPt1f32:
+    cond_type = 0;
+    break;
+  case ARM::VCMPt2i8:
+  case ARM::VCMPt2i16:
+  case ARM::VCMPt2i32:
+    scalar = 1;
+  case ARM::VCMPt1i8:
+  case ARM::VCMPt1i16:
+  case ARM::VCMPt1i32:
+    cond_type = 1;
+    break;
+  case ARM::VCMPt2s8:
+  case ARM::VCMPt2s16:
+  case ARM::VCMPt2s32:
+    scalar = 1;
+  case ARM::VCMPt1s8:
+  case ARM::VCMPt1s16:
+  case ARM::VCMPt1s32:
+    cond_type = 2;
+    break;
+  case ARM::VCMPt2u8:
+  case ARM::VCMPt2u16:
+  case ARM::VCMPt2u32:
+    scalar = 1;
+  case ARM::VCMPt1u8:
+  case ARM::VCMPt1u16:
+  case ARM::VCMPt1u32:
+    cond_type = 3;
+    break;
+  }
+  unsigned fc;
+
+  if (scalar) {
+    fc = fieldFromInstruction(Insn, 12, 1) << 2 |
+         fieldFromInstruction(Insn, 7, 1) |
+         fieldFromInstruction(Insn, 5, 1) << 1;
+    unsigned Rm = fieldFromInstruction(Insn, 0, 4);
+    if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
+      return MCDisassembler::Fail;
+  } else {
+    fc = fieldFromInstruction(Insn, 12, 1) << 2 |
+         fieldFromInstruction(Insn, 7, 1) |
+         fieldFromInstruction(Insn, 0, 1) << 1;
+    unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
+                  fieldFromInstruction(Insn, 1, 3);
+
+    if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+      return MCDisassembler::Fail;
+  }
+  switch (cond_type) {
+  case 0:
+    // pred_basic_fp
+    if (!Check(S,
+               DecodeRestrictedFPPredicateOperand(Inst, fc, Address, Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  case 1:
+    // pred_basic_i
+    if (!Check(S,
+               DecodeRestrictedIPredicateOperand(Inst, fc, Address, Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  case 2:
+    // pred_basic_s
+    if (!Check(S,
+               DecodeRestrictedSPredicateOperand(Inst, fc, Address, Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  case 3:
+    // pred_basic_u
+    if (!Check(S,
+               DecodeRestrictedUPredicateOperand(Inst, fc, Address, Decoder)))
+      return MCDisassembler::Fail;
+    break;
+  }
+  Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+  Inst.addOperand(MCOperand::createReg(0));
+  Inst.addOperand(MCOperand::createImm(0));
+
+  return S;
+}
+
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  return S;
+}
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
@@ -170,6 +170,13 @@
   void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O);
+  void printMandatoryRestrictedPredicateOperand(const MCInst *MI,
+                                                unsigned OpNum,
+                                                const MCSubtargetInfo &STI,
+                                                raw_ostream &O);
+  void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum,
+                                      const MCSubtargetInfo &STI,
+                                      raw_ostream &O);
   void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
                                 const MCSubtargetInfo &STI, raw_ostream &O);
   void printRegisterList(const MCInst *MI, unsigned OpNum,
@@ -211,6 +218,10 @@
                           const MCSubtargetInfo &STI, raw_ostream &O);
   void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
                                 const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMVEVectorListTwoQ(const MCInst *MI, unsigned OpNum,
+                              const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMVEVectorListFourQ(const MCInst *MI, unsigned OpNum,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
   void printVectorListThree(const MCInst *MI, unsigned OpNum,
                             const MCSubtargetInfo &STI, raw_ostream &O);
   void printVectorListFour(const MCInst *MI, unsigned OpNum,
@@ -239,6 +250,24 @@
   template<int64_t Angle, int64_t Remainder>
   void printComplexRotationOp(const MCInst *MI, unsigned OpNum,
                               const MCSubtargetInfo &STI, raw_ostream &O);
+  void printComplexRotationOpOdd(const MCInst *MI, unsigned OpNum,
+                                 const MCSubtargetInfo &STI, raw_ostream &O);
+
+  // MVE
+  void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
+                                const MCSubtargetInfo &STI,
+                                raw_ostream &O);
+  void printVPTMask(const MCInst *MI, unsigned OpNum,
+                    const MCSubtargetInfo &STI, raw_ostream &O);
+  template<int shift>
+  void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
+                                 const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
+                                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
+  void printMVEi64SplatOperand(const MCInst *MI, unsigned OpNum,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
 
 private:
   unsigned DefaultAltIdx = ARM::NoRegAltName;
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -603,6 +603,40 @@
     << markup(">");
 }
 
+template<int shift>
+void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
+                                               const MCSubtargetInfo &STI,
+                                               raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(OpNum);
+  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
+
+  O << markup("<mem:") << "[";
+  printRegName(O, MO1.getReg());
+  O << ", ";
+  printRegName(O, MO2.getReg());
+
+  if (shift > 0)
+    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
+
+  O << "]" << markup(">");
+}
+
+void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
+                                               const MCSubtargetInfo &STI,
+                                               raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(OpNum);
+  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
+
+  O << markup("<mem:") << "[";
+  printRegName(O, MO1.getReg());
+
+  int64_t Imm = MO2.getImm();
+  if (Imm != 0)
+    O << ", " << markup("<imm:") << '#' << Imm << markup(">");
+
+  O << "]" << markup(">");
+}
+
 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
                                            const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
@@ -771,11 +805,13 @@
 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
-  assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
-                        [&](const MCOperand &LHS, const MCOperand &RHS) {
-                          return MRI.getEncodingValue(LHS.getReg()) <
-                                 MRI.getEncodingValue(RHS.getReg());
-                        }));
+  if (MI->getOpcode() != ARM::t2CLRM) {
+    assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
+                          [&](const MCOperand &LHS, const MCOperand &RHS) {
+                            return MRI.getEncodingValue(LHS.getReg()) <
+                                   MRI.getEncodingValue(RHS.getReg());
+                          }));
+  }
 
   O << "{";
   for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
@@ -930,6 +966,15 @@
     O << ARMCondCodeToString(CC);
 }
 
+void ARMInstPrinter::printMandatoryRestrictedPredicateOperand(
+    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
+    raw_ostream &O) {
+  if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
+    O << "cs";
+  else
+    printMandatoryPredicateOperand(MI, OpNum, STI, O);
+}
+
 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
                                                     unsigned OpNum,
                                                     const MCSubtargetInfo &STI,
@@ -938,6 +983,14 @@
   O << ARMCondCodeToString(CC);
 }
 
+void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
+                                                            unsigned OpNum,
+                                                            const MCSubtargetInfo &STI,
+                                                            raw_ostream &O) {
+  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
+  O << ARMCondCodeToString(ARMCC::getOppositeCondition(CC));
+}
+
 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
                                               const MCSubtargetInfo &STI,
                                               raw_ostream &O) {
@@ -1405,6 +1458,44 @@
   O << "}";
 }
 
+void ARMInstPrinter::printMVEVectorListTwoQ(const MCInst *MI, unsigned OpNum,
+                                            const MCSubtargetInfo &STI,
+                                            raw_ostream &O) {
+  // MVE vector lists are always written as a list of q-registers,
+  // never d-registers. getSubReg will give us the four d-regs making
+  // up a QQPR, so we take every other one of those and find its
+  // super-reg in the MQPR class in order to get the list of q-regs to
+  // print.
+  auto MQPR = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
+  unsigned Reg = MI->getOperand(OpNum).getReg();
+  const char *Prefix = "{";
+  for (auto SubIdx: {ARM::dsub_0, ARM::dsub_2}) {
+    unsigned SubReg = MRI.getMatchingSuperReg(MRI.getSubReg(Reg, SubIdx),
+                                              ARM::dsub_0, MQPR);
+    O << Prefix;
+    printRegName(O, SubReg);
+    Prefix = ", ";
+  }
+  O << "}";
+}
+
+void ARMInstPrinter::printMVEVectorListFourQ(const MCInst *MI, unsigned OpNum,
+                                             const MCSubtargetInfo &STI,
+                                             raw_ostream &O) {
+  // Same as printMVEVectorListTwoQ but with four q-registers.
+  auto MQPR = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
+  unsigned Reg = MI->getOperand(OpNum).getReg();
+  const char *Prefix = "{";
+  for (auto SubIdx: {ARM::dsub_0, ARM::dsub_2, ARM::dsub_4, ARM::dsub_6}) {
+    unsigned SubReg = MRI.getMatchingSuperReg(MRI.getSubReg(Reg, SubIdx),
+                                              ARM::dsub_0, MQPR);
+    O << Prefix;
+    printRegName(O, SubReg);
+    Prefix = ", ";
+  }
+  O << "}";
+}
+
 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
                                           const MCSubtargetInfo &STI,
                                           raw_ostream &O) {
@@ -1580,3 +1671,56 @@
   O << "#" << (Val * Angle) + Remainder;
 }
 
+void ARMInstPrinter::printComplexRotationOpOdd(const MCInst *MI, unsigned OpNo,
+                                               const MCSubtargetInfo &STI,
+                                               raw_ostream &O) {
+  unsigned Val = MI->getOperand(OpNo).getImm();
+  O << "#" << (Val * 180) + 90;
+}
+
+void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
+                                              const MCSubtargetInfo &STI,
+                                              raw_ostream &O) {
+  ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
+  if (CC != ARMVCC::None)
+    O << ARMVPTPredToString(CC);
+}
+
+void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
+                                  const MCSubtargetInfo &STI,
+                                  raw_ostream &O) {
+  // (3 - the number of trailing zeroes) is the number of them / else.
+  unsigned Mask = MI->getOperand(OpNum).getImm();
+  unsigned NumTZ = countTrailingZeros(Mask);
+  assert(NumTZ <= 3 && "Invalid VPT mask!");
+  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
+    bool T = ((Mask >> Pos) & 1) == 0;
+    if (T)
+      O << 't';
+    else
+      O << 'e';
+  }
+}
+
+void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
+                                             const MCSubtargetInfo &STI,
+                                             raw_ostream &O) {
+  uint32_t Val = MI->getOperand(OpNum).getImm();
+  O << markup("<imm:") << "#0x";
+  O.write_hex(Val);
+  O << markup(">");
+}
+
+void ARMInstPrinter::printMVEi64SplatOperand(const MCInst *MI, unsigned OpNum,
+                                             const MCSubtargetInfo &STI,
+                                             raw_ostream &O) {
+  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
+  uint64_t Val = 0;
+  for (int i = 0; i < 8; i++)
+      if ((EncodedImm >> i) & 1)
+          Val |= (uint64_t)0xff << (i * 8);
+
+  O << markup("<imm:") << "#0x";
+  O.write_hex(Val);
+  O << markup(">");
+}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
@@ -30,7 +30,8 @@
     lsl,
     lsr,
     ror,
-    rrx
+    rrx,
+    uxtw
   };
 
   enum AddrOpc {
@@ -48,6 +49,7 @@
     case ARM_AM::lsr: return "lsr";
     case ARM_AM::ror: return "ror";
     case ARM_AM::rrx: return "rrx";
+    case ARM_AM::uxtw: return "uxtw";
     }
   }
 
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -75,6 +75,9 @@
 
   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
 
+  unsigned gettGPROddEvenOpValue(const MCInst &MI, unsigned OpIdx,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
@@ -162,6 +165,11 @@
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
+  /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
+  /// operand.
+  uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
 
   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
   /// operand.
@@ -180,6 +188,12 @@
                                    SmallVectorImpl<MCFixup> &Fixups,
                                    const MCSubtargetInfo &STI) const;
 
+  /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
+  /// operand.
+  uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
+                                      SmallVectorImpl<MCFixup> &Fixups,
+                                      const MCSubtargetInfo &STI) const;
+
   /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
   /// operand.
   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
@@ -192,6 +206,31 @@
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
+  /// getT2Imm7s4OpValue - Return encoding info for '+/- imm7<<2'
+  /// operand.
+  uint32_t getT2Imm7s4OpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
+
+  /// getT2Imm7OpValue - Return encoding info for '+/- imm7 << shift'
+  /// operand.
+  template<int shift>
+  uint32_t getT2Imm7OpValue(const MCInst &MI, unsigned OpIdx,
+                            SmallVectorImpl<MCFixup> &Fixups,
+                            const MCSubtargetInfo &STI) const;
+
+  /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
+  /// operand.
+  uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
+                                   SmallVectorImpl<MCFixup> &Fixups,
+                                   const MCSubtargetInfo &STI) const;
+
+  /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
+  /// operand.
+  template<int shift>
+  uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
+                                  SmallVectorImpl<MCFixup> &Fixups,
+                                  const MCSubtargetInfo &STI) const;
 
   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
   /// operand as needed by load/store instructions.
@@ -223,8 +262,10 @@
     case ARM_AM::asr: return 2;
     case ARM_AM::ror:
     case ARM_AM::rrx: return 3;
+    case ARM_AM::uxtw:
+    default:
+      llvm_unreachable("Invalid ShiftOpc!");
     }
-    llvm_unreachable("Invalid ShiftOpc!");
   }
 
   /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
@@ -326,6 +367,13 @@
   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
     SmallVectorImpl<MCFixup> &Fixups,
     const MCSubtargetInfo &STI) const;
+  template<int shift>
+  unsigned getT2AddrModeImm7OpValue(const MCInst &MI, unsigned OpNum,
+    SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const;
+  unsigned getT2AddrModeImm7OffsetOpValue(const MCInst &MI, unsigned OpNum,
+    SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const;
   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
     SmallVectorImpl<MCFixup> &Fixups,
     const MCSubtargetInfo &STI) const;
@@ -383,6 +431,14 @@
   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
+  template <uint8_t shift, bool invert>
+  unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const {
+    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
+    const MCOperand MO = MI.getOperand(Op);
+    return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift;
+  }
 
   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
                                       unsigned EncodedValue,
@@ -401,6 +457,17 @@
                                 unsigned EncodedValue,
                                 const MCSubtargetInfo &STI) const;
 
+  // MVE
+  unsigned getVCMLARotOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
+
+  unsigned getVCADDRotOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
+  uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
   void EmitByte(unsigned char C, raw_ostream &OS) const {
     OS << (char)C;
   }
@@ -416,6 +483,30 @@
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
+
+  template <bool isNeg, ARM::Fixups fixup>
+  uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
+
+  uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                                   SmallVectorImpl<MCFixup> &Fixups,
+                                   const MCSubtargetInfo &STI) const;
+
+  uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
+  uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
+                                        SmallVectorImpl<MCFixup> &Fixups,
+                                        const MCSubtargetInfo &STI) const;
+  template <unsigned size>
+  uint32_t getMVEVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
+                                    SmallVectorImpl<MCFixup> &Fixups,
+                                    const MCSubtargetInfo &STI) const;
+  template <unsigned size>
+  uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
+                                        SmallVectorImpl<MCFixup> &Fixups,
+                                        const MCSubtargetInfo &STI) const;
 };
 
 } // end anonymous namespace
@@ -440,6 +531,14 @@
   return EncodedValue;
 }
 
+// MVE
+unsigned ARMMCCodeEmitter::gettGPROddEvenOpValue(const MCInst &MI, unsigned OpIdx,
+                                                 SmallVectorImpl<MCFixup> &Fixups,
+                                                 const MCSubtargetInfo &STI) const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) >> 1;
+}
+
 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
 /// instructions, and rewrite them to their Thumb2 form if we are currently in
 /// Thumb2 mode.
@@ -501,6 +600,9 @@
   if (MO.isReg()) {
     unsigned Reg = MO.getReg();
     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
+    if (STI.getFeatureBits()[ARM::HasMVEIntegerOps] ||
+        STI.getFeatureBits()[ARM::HasMVEFloatOps])
+      return RegNo;
 
     // Q registers are encoded as 2x their register number.
     switch (Reg) {
@@ -843,6 +945,41 @@
   return (Rm << 3) | Rn;
 }
 
+/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
+/// operand.
+uint32_t
+ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
+                                        SmallVectorImpl<MCFixup> &Fixups,
+                                        const MCSubtargetInfo &STI) const {
+  // {4-0} = szimm5
+  // The value we are trying to encode is an immediate between either the
+  // range of [1-7] or [1-15] depending on whether we are dealing with the
+  // u8/s8 or the u16/s16 variants respectively.
+  // This value is encoded as follows, if ShiftImm is the value within those
+  // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
+  // or 16.
+
+  unsigned Size, ShiftImm;
+  switch(MI.getOpcode()) {
+    case ARM::t1VSHLLs16bh:
+    case ARM::t1VSHLLs16th:
+    case ARM::t1VSHLLu16bh:
+    case ARM::t1VSHLLu16th:
+      Size = 16;
+      break;
+    case ARM::t1VSHLLs8bh:
+    case ARM::t1VSHLLs8th:
+    case ARM::t1VSHLLu8bh:
+    case ARM::t1VSHLLu8th:
+      Size = 8;
+      break;
+    default:
+      llvm_unreachable("Use of operand not supported by this instruction");
+  }
+  ShiftImm = MI.getOperand(OpIdx).getImm();
+  return Size + ShiftImm;
+}
+
 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
 uint32_t ARMMCCodeEmitter::
 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
@@ -926,6 +1063,119 @@
   return Binary;
 }
 
+/// getT2Imm7s4OpValue - Return encoding info for
+/// '+/- imm7<<2' operand.
+uint32_t ARMMCCodeEmitter::
+getT2Imm7s4OpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const {
+  // FIXME: The immediate operand should have already been encoded like this
+  // before ever getting here. The encoder method should just need to combine
+  // the MI operands for the register and the offset into a single
+  // representation for the complex operand in the .td file. This isn't just
+  // style, unfortunately. As-is, we can't represent the distinct encoding
+  // for #-0.
+
+  // {7}    = (A)dd (add == '1', sub == '0')
+  // {6-0}  = imm7
+  int32_t Imm7 = MI.getOperand(OpIdx).getImm();
+  bool isAdd = Imm7 >= 0;
+
+  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
+  if (Imm7 < 0)
+    Imm7 = -(uint32_t)Imm7;
+
+  // Scaled by 4.
+  Imm7 /= 4;
+
+  uint32_t Binary = Imm7 & 0x7f;
+  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
+  if (isAdd)
+    Binary |= (1 << 7);
+  return Binary;
+}
+
+/// getT2Imm7OpValue - Return encoding info for
+/// '+/- imm7 << shift' operand.
+template<int shift>
+uint32_t ARMMCCodeEmitter::
+getT2Imm7OpValue(const MCInst &MI, unsigned OpIdx,
+                 SmallVectorImpl<MCFixup> &Fixups,
+                 const MCSubtargetInfo &STI) const {
+  // FIXME: The immediate operand should have already been encoded like this
+  // before ever getting here. The encoder method should just need to combine
+  // the MI operands for the register and the offset into a single
+  // representation for the complex operand in the .td file. This isn't just
+  // style, unfortunately. As-is, we can't represent the distinct encoding
+  // for #-0.
+
+  // {7}    = (A)dd (add == '1', sub == '0')
+  // {6-0}  = imm7
+  int32_t Imm7 = MI.getOperand(OpIdx).getImm() >> shift;
+  bool isAdd = Imm7 >= 0;
+
+  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
+  if (Imm7 < 0)
+    Imm7 = -(uint32_t)Imm7;
+
+  uint32_t Binary = Imm7 & 0x7f;
+  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
+  if (isAdd)
+    Binary |= (1 << 7);
+  return Binary;
+}
+
+/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
+/// operand.
+uint32_t ARMMCCodeEmitter::
+getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
+                        SmallVectorImpl<MCFixup> &Fixups,
+                        const MCSubtargetInfo &STI) const {
+    // {6-3} Rn
+    // {2-0} Qm
+    const MCOperand &M0 = MI.getOperand(OpIdx);
+    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
+
+    unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
+    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
+
+    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
+
+    return (Rn << 3) | Qm;
+}
+
+/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
+/// operand.
+template<int shift>
+uint32_t ARMMCCodeEmitter::
+getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
+                        SmallVectorImpl<MCFixup> &Fixups,
+                        const MCSubtargetInfo &STI) const {
+    // {10-8} Qm
+    // {7-0} Imm
+    const MCOperand &M0 = MI.getOperand(OpIdx);
+    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
+
+    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
+    int32_t Imm = M1.getImm();
+
+    bool isAdd = Imm >= 0;
+
+    Imm >>= shift;
+
+    if (!isAdd)
+      Imm = -(uint32_t)Imm;
+
+    Imm &= 0x7f;
+
+    if (isAdd)
+      Imm |= 0x80;
+
+    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
+
+    return (Qm << 8) | Imm;
+}
+
 /// getT2AddrModeImm8s4OpValue - Return encoding info for
 /// 'reg +/- imm8<<2' operand.
 uint32_t ARMMCCodeEmitter::
@@ -967,6 +1217,33 @@
   return Binary;
 }
 
+/// getT2AddrModeImm7s4OpValue - Return encoding info for
+/// 'reg +/- imm7<<2' operand.
+uint32_t
+ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
+                                             SmallVectorImpl<MCFixup> &Fixups,
+                                             const MCSubtargetInfo &STI) const {
+  // {11-8} = reg
+  // {7}    = (A)dd (add == '1', sub == '0')
+  // {6-0}  = imm7
+  unsigned Reg, Imm7;
+  // If The first operand isn't a register, we have a label reference.
+  bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
+
+  // FIXME: The immediate operand should have already been encoded like this
+  // before ever getting here. The encoder method should just need to combine
+  // the MI operands for the register and the offset into a single
+  // representation for the complex operand in the .td file. This isn't just
+  // style, unfortunately. As-is, we can't represent the distinct encoding
+  // for #-0.
+  uint32_t Binary = (Imm7 >> 2) & 0xff;
+  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
+  if (isAdd)
+    Binary |= (1 << 7);
+  Binary |= (Reg << 8);
+  return Binary;
+}
+
 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
 /// 'reg + imm8<<2' operand.
 uint32_t ARMMCCodeEmitter::
@@ -1421,6 +1698,29 @@
   return Value;
 }
 
+template<int shift>
+unsigned ARMMCCodeEmitter::
+getT2AddrModeImm7OpValue(const MCInst &MI, unsigned OpNum,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+  const MCOperand &MO1 = MI.getOperand(OpNum);
+  const MCOperand &MO2 = MI.getOperand(OpNum+1);
+
+  // FIXME: Needs fixup support.
+  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
+
+  // Even though the immediate is 7 bits long, we need 8 bits in order
+  // to represent the (inverse of the) sign bit.
+  Value <<= 8;
+  int32_t tmp = ((int32_t)MO2.getImm()) >> shift;
+  if (tmp < 0)
+    tmp = abs(tmp);
+  else
+    Value |= 128; // Set the ADD bit
+  Value |= tmp & 127;
+  return Value;
+}
+
 unsigned ARMMCCodeEmitter::
 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
                          SmallVectorImpl<MCFixup> &Fixups,
@@ -1439,6 +1739,23 @@
 }
 
 unsigned ARMMCCodeEmitter::
+getT2AddrModeImm7OffsetOpValue(const MCInst &MI, unsigned OpNum,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+  const MCOperand &MO1 = MI.getOperand(OpNum);
+
+  // FIXME: Needs fixup support.
+  unsigned Value = 0;
+  int32_t tmp = (int32_t)MO1.getImm();
+  if (tmp < 0)
+    tmp = abs(tmp);
+  else
+    Value |= 128; // Set the ADD bit
+  Value |= tmp & 128;
+  return Value;
+}
+
+unsigned ARMMCCodeEmitter::
 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
                 SmallVectorImpl<MCFixup> &Fixups,
                 const MCSubtargetInfo &STI) const {
@@ -1499,7 +1816,7 @@
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
                        SmallVectorImpl<MCFixup> &Fixups,
                        const MCSubtargetInfo &STI) const {
-  // VLDM/VSTM:
+  // VLDM/VSTM/VSCCLRM:
   //   {12-8} = Vd
   //   {7-0}  = Number of registers
   //
@@ -1508,28 +1825,40 @@
   unsigned Reg = MI.getOperand(Op).getReg();
   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
+  bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
 
   unsigned Binary = 0;
 
   if (SPRRegs || DPRRegs) {
-    // VLDM/VSTM
+    // VLDM/VSTM/VSCCLRM
     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
     Binary |= (RegNo & 0x1f) << 8;
+
+    // Ignore VPR
+    if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
+      --NumRegs;
     if (SPRRegs)
       Binary |= NumRegs;
     else
       Binary |= NumRegs * 2;
   } else {
     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
-    assert(std::is_sorted(MI.begin() + Op, MI.end(),
-                          [&](const MCOperand &LHS, const MCOperand &RHS) {
-                            return MRI.getEncodingValue(LHS.getReg()) <
-                                   MRI.getEncodingValue(RHS.getReg());
-                          }));
+    if (!CLRMRegs) {
+      assert(std::is_sorted(MI.begin() + Op, MI.end(),
+                            [&](const MCOperand &LHS, const MCOperand &RHS) {
+                              return MRI.getEncodingValue(LHS.getReg()) <
+                                     MRI.getEncodingValue(RHS.getReg());
+                            }));
+    }
 
     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
-      unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
+      unsigned RegNo;
+      if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
+        RegNo = 15;
+      } else {
+        RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
+      }
       Binary |= 1 << RegNo;
     }
   }
@@ -1675,6 +2004,182 @@
   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 }
 
+template <bool isNeg, ARM::Fixups fixup>
+uint32_t
+ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                                     SmallVectorImpl<MCFixup> &Fixups,
+                                     const MCSubtargetInfo &STI) const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  if (MO.isExpr())
+    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
+  return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
+}
+
+uint32_t
+ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  const MCOperand BranchMO = MI.getOperand(0);
+
+  if (MO.isExpr()) {
+    assert(BranchMO.isExpr());
+    const MCExpr *DiffExpr = MCBinaryExpr::createSub(
+        MO.getExpr(), BranchMO.getExpr(), CTX);
+    MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
+    Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
+    return 0;
+  }
+
+  assert(MO.isImm() && BranchMO.isImm());
+  int Diff = MO.getImm() - BranchMO.getImm();
+  assert(Diff == 4 || Diff == 2);
+
+  return Diff == 4;
+}
+
+uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
+                                             SmallVectorImpl<MCFixup> &Fixups,
+                                             const MCSubtargetInfo &STI)const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+
+  int Value = MO.getImm();
+  int Imm = 0;
+
+  // VPT Masks are actually encoded as a series of invert/don't invert bits,
+  // rather than true/false bits.
+  unsigned PrevBit = 0;
+  for (int i = 3; i >= 0; --i) {
+    unsigned Bit = (Value >> i) & 1;
+
+    // Check if we are at the end of the mask.
+    if ((Value & ~(~0U << i)) == 0) {
+      Imm |= (1 << i);
+      break;
+    }
+
+    // Convert the bit in the mask based on the previous bit.
+    if (Bit != PrevBit)
+      Imm |= (1 << i);
+
+    PrevBit = Bit;
+  }
+
+  return Imm;
+}
+
+uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
+    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
+
+  const MCOperand MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+
+  switch (MO.getImm()) {
+  default:
+    assert(0 && "Unexpected Condition!");
+    return 0;
+  case ARMCC::HS:
+  case ARMCC::EQ:
+    return 0;
+  case ARMCC::HI:
+  case ARMCC::NE:
+    return 1;
+  case ARMCC::GE:
+    return 4;
+  case ARMCC::LT:
+    return 5;
+  case ARMCC::GT:
+    return 6;
+  case ARMCC::LE:
+    return 7;
+  }
+}
+
+unsigned ARMMCCodeEmitter::
+getVCMLARotOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const {
+   const MCOperand &MO = MI.getOperand(OpIdx);
+   assert(MO.isImm() && "Unexpected operand type!");
+
+   unsigned Value = MO.getImm();
+   assert(Value == 0 || Value == 90 || Value == 180 || Value == 270);
+
+   return Value / 90;
+}
+
+unsigned ARMMCCodeEmitter::
+getVCADDRotOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const {
+   const MCOperand &MO = MI.getOperand(OpIdx);
+   assert(MO.isImm() && "Unexpected operand type!");
+
+   unsigned Value = MO.getImm();
+   assert(Value == 90 || Value == 270);
+
+   return Value == 270;
+}
+
+uint32_t ARMMCCodeEmitter::
+getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+
+  int Value = MO.getImm();
+  assert(Value == 1 || Value == 2 || Value == 4 || Value == 8);
+
+  if (Value == 1)
+    return 0;
+  if (Value == 2)
+    return 1;
+  if (Value == 4)
+    return 2;
+  return 3;
+}
+
+template <unsigned size>
+uint32_t ARMMCCodeEmitter::
+getMVEVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+  static_assert(size == 1 || size == 2 || size == 4, "Size must be 1, 2, or 4.");
+
+  int Value = MO.getImm();
+
+  // This is encoded on a beat basis
+  int Mod = Value % size;
+  int Div = Value / size;
+
+  int Imm = 0;
+  if (size == 4) {
+    Imm = 8;
+    Imm |= Mod;
+  } else if (size == 2) {
+    Imm = 1;
+    Imm |= Mod << 1;
+  }
+  return Imm | (Div & 2) << 3 | (Div & 1) << 2;
+}
+
+template <unsigned start>
+uint32_t ARMMCCodeEmitter::
+getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const {
+  const MCOperand MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+
+  int Value = MO.getImm();
+  return Value - start;
+}
+
 #include "ARMGenMCCodeEmitter.inc"
 
 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -14,6 +14,7 @@
 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
 
 #include "llvm/Support/DataTypes.h"
+#include "llvm/MC/MCInstrDesc.h"
 #include <memory>
 #include <string>
 
@@ -99,6 +100,20 @@
 
 /// Construct ARM Mach-O relocation info.
 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
+
+namespace ARM {
+enum OperandType {
+  OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
+  OPERAND_VPRED_N,
+};
+inline bool isVpred(OperandType op) {
+  return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
+}
+inline bool isVpred(uint8_t op) {
+  return isVpred(static_cast<OperandType>(op));
+}
+} // end namespace ARM
+
 } // End llvm namespace
 
 // Defines symbolic names for ARM registers.  This defines a mapping from
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -276,14 +276,29 @@
 public:
   ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
 
-  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
-                      uint64_t Size, uint64_t &Target) const override {
+  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                      uint64_t &Target) const override {
+    unsigned OpId;
+    switch (Inst.getOpcode()) {
+    default:
+      OpId = 0;
+      break;
+    case ARM::t2WLS:
+    case ARM::t2LEUpdate:
+      OpId = 2;
+      break;
+    case ARM::t2LE:
+      OpId = 1;
+      break;
+    }
+
     // We only handle PCRel branches for now.
-    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
+    if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
+        MCOI::OPERAND_PCREL)
       return false;
 
-    int64_t Imm = Inst.getOperand(0).getImm();
-    Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
+    // In Thumb mode the PC is always off by 4 bytes.
+    Target = Addr + Inst.getOperand(OpId).getImm() + 4;
     return true;
   }
 };
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -161,7 +161,7 @@
     // otherwise).
     if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
       MachineRegisterInfo *MRI = &MF.getRegInfo();
-      MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
+      MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
     }
 
     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
@@ -203,7 +203,7 @@
     if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
       MachineRegisterInfo *MRI = &MF.getRegInfo();
       MRI->constrainRegClass(DestReg,
-                             &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
+                             &ARM::GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass);
     }
 
     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -66,6 +66,30 @@
 }
 } // end namespace ARMCC
 
+namespace ARMVCC {
+  enum VPTCodes {
+    None = 0,
+    Then,
+    Else
+  };
+}
+
+inline static const char *ARMVPTPredToString(ARMVCC::VPTCodes CC) {
+  switch (CC) {
+  case ARMVCC::None:  return "none";
+  case ARMVCC::Then:  return "t";
+  case ARMVCC::Else:  return "e";
+  }
+  llvm_unreachable("Unknown VPT code");
+}
+
+inline static unsigned ARMVectorCondCodeFromString(StringRef CC) {
+  return StringSwitch<unsigned>(CC.lower())
+    .Case("t", ARMVCC::Then)
+    .Case("e", ARMVCC::Else)
+    .Default(~0U);
+}
+
 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
   switch (CC) {
   case ARMCC::EQ:  return "eq";
diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll
--- a/llvm/test/CodeGen/ARM/half.ll
+++ b/llvm/test/CodeGen/ARM/half.ll
@@ -3,6 +3,10 @@
 ; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8
 ; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8
 ; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=-fp64 | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8-SP
+; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
+; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP
 
 define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
diff --git a/llvm/test/MC/ARM/clrm-asm.s b/llvm/test/MC/ARM/clrm-asm.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/clrm-asm.s
@@ -0,0 +1,24 @@
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK %s
+// RUN:   FileCheck --check-prefix=ERROR < %t %s
+
+// CHECK: clrm            {r0, r1, r2, r3} @ encoding: [0x9f,0xe8,0x0f,0x00]
+clrm {r0, r1, r2, r3}
+
+// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @ encoding: [0x9f,0xe8,0xff,0xdf]
+clrm {r0-r12, lr, apsr}
+
+// CHECK: clrm            {apsr, lr} @ encoding: [0x9f,0xe8,0x00,0xc0]
+clrm {apsr, lr}
+
+// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, lr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
+clrm {r0-r4, apsr, lr}
+
+// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
+clrm {sp}
+
+// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
+clrm {r13}
+
+// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
+clrm {r0-r12, sp}
diff --git a/llvm/test/MC/ARM/fp-armv8-m.s b/llvm/test/MC/ARM/fp-armv8-m.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/fp-armv8-m.s
@@ -0,0 +1,140 @@
+@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp -mattr=+fp64 -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-V81M %s
+@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+fp-armv8 -mattr=+fp64 -show-encoding < %s \
+@ RUN:     | FileCheck --check-prefix=CHECK-V81M %s
+
+@ VCVT{B,T}
+
+  vcvtt.f64.f16 d3, s1
+@ CHECK-V81M: vcvtt.f64.f16 d3, s1      @ encoding: [0xb2,0xee,0xe0,0x3b]
+  vcvtt.f16.f64 s5, d12
+@ CHECK-V81M: vcvtt.f16.f64 s5, d12     @ encoding: [0xf3,0xee,0xcc,0x2b]
+
+  vcvtb.f64.f16 d3, s1
+@ CHECK-V81M: vcvtb.f64.f16 d3, s1     @ encoding: [0xb2,0xee,0x60,0x3b]
+  vcvtb.f16.f64 s4, d1
+@ CHECK-V81M: vcvtb.f16.f64 s4, d1     @ encoding: [0xb3,0xee,0x41,0x2b]
+
+  it ge
+  vcvttge.f64.f16 d3, s1
+@ CHECK-V81M: vcvttge.f64.f16 d3, s1      @ encoding: [0xb2,0xee,0xe0,0x3b]
+  it gt
+  vcvttgt.f16.f64 s5, d12
+@ CHECK-V81M: vcvttgt.f16.f64 s5, d12     @ encoding: [0xf3,0xee,0xcc,0x2b]
+
+  it eq
+  vcvtbeq.f64.f16 d3, s1
+@ CHECK-V81M: vcvtbeq.f64.f16 d3, s1     @ encoding: [0xb2,0xee,0x60,0x3b]
+  it lt
+  vcvtblt.f16.f64 s4, d1
+@ CHECK-V81M: vcvtblt.f16.f64 s4, d1     @ encoding: [0xb3,0xee,0x41,0x2b]
+
+
+@ VCVT{A,N,P,M}
+
+  vcvta.s32.f32 s2, s3
+@ CHECK-V81M: vcvta.s32.f32 s2, s3     @ encoding: [0xbc,0xfe,0xe1,0x1a]
+  vcvta.s32.f64 s2, d3
+@ CHECK-V81M: vcvta.s32.f64 s2, d3     @ encoding: [0xbc,0xfe,0xc3,0x1b]
+  vcvtn.s32.f32 s6, s23
+@ CHECK-V81M: vcvtn.s32.f32 s6, s23     @ encoding: [0xbd,0xfe,0xeb,0x3a]
+  vcvtn.s32.f64 s6, d7
+@ CHECK-V81M: vcvtn.s32.f64 s6, d7     @ encoding: [0xbd,0xfe,0xc7,0x3b]
+  vcvtp.s32.f32 s0, s4
+@ CHECK-V81M: vcvtp.s32.f32 s0, s4     @ encoding: [0xbe,0xfe,0xc2,0x0a]
+  vcvtp.s32.f64 s0, d4
+@ CHECK-V81M: vcvtp.s32.f64 s0, d4     @ encoding: [0xbe,0xfe,0xc4,0x0b]
+  vcvtm.s32.f32 s17, s8
+@ CHECK-V81M: vcvtm.s32.f32 s17, s8     @ encoding: [0xff,0xfe,0xc4,0x8a]
+  vcvtm.s32.f64 s17, d8
+@ CHECK-V81M: vcvtm.s32.f64 s17, d8     @ encoding: [0xff,0xfe,0xc8,0x8b]
+
+  vcvta.u32.f32 s2, s3
+@ CHECK-V81M: vcvta.u32.f32 s2, s3     @ encoding: [0xbc,0xfe,0x61,0x1a]
+  vcvta.u32.f64 s2, d3
+@ CHECK-V81M: vcvta.u32.f64 s2, d3     @ encoding: [0xbc,0xfe,0x43,0x1b]
+  vcvtn.u32.f32 s6, s23
+@ CHECK-V81M: vcvtn.u32.f32 s6, s23     @ encoding: [0xbd,0xfe,0x6b,0x3a]
+  vcvtn.u32.f64 s6, d7
+@ CHECK-V81M: vcvtn.u32.f64 s6, d7     @ encoding: [0xbd,0xfe,0x47,0x3b]
+  vcvtp.u32.f32 s0, s4
+@ CHECK-V81M: vcvtp.u32.f32 s0, s4     @ encoding: [0xbe,0xfe,0x42,0x0a]
+  vcvtp.u32.f64 s0, d4
+@ CHECK-V81M: vcvtp.u32.f64 s0, d4     @ encoding: [0xbe,0xfe,0x44,0x0b]
+  vcvtm.u32.f32 s17, s8
+@ CHECK-V81M: vcvtm.u32.f32 s17, s8     @ encoding: [0xff,0xfe,0x44,0x8a]
+  vcvtm.u32.f64 s17, d8
+@ CHECK-V81M: vcvtm.u32.f64 s17, d8     @ encoding: [0xff,0xfe,0x48,0x8b]
+
+
+@ VSEL
+  vselge.f32 s4, s1, s23
+@ CHECK-V81M: vselge.f32 s4, s1, s23    @ encoding: [0x20,0xfe,0xab,0x2a]
+  vselge.f64 d0, d1, d3
+@ CHECK-V81M: vselge.f64 d0, d1, d3  @ encoding: [0x21,0xfe,0x03,0x0b]
+  vselgt.f32 s0, s1, s0
+@ CHECK-V81M: vselgt.f32 s0, s1, s0    @ encoding: [0x30,0xfe,0x80,0x0a]
+  vselgt.f64 d5, d10, d11
+@ CHECK-V81M: vselgt.f64 d5, d10, d11  @ encoding: [0x3a,0xfe,0x0b,0x5b]
+  vseleq.f32 s30, s28, s23
+@ CHECK-V81M: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
+  vseleq.f64 d2, d4, d8
+@ CHECK-V81M: vseleq.f64 d2, d4, d8    @ encoding: [0x04,0xfe,0x08,0x2b]
+  vselvs.f32 s21, s16, s14
+@ CHECK-V81M: vselvs.f32 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xaa]
+  vselvs.f64 d0, d1, d15
+@ CHECK-V81M: vselvs.f64 d0, d1, d15   @ encoding: [0x11,0xfe,0x0f,0x0b]
+
+
+@ VMAXNM / VMINNM
+  vmaxnm.f32 s5, s12, s0
+@ CHECK-V81M: vmaxnm.f32 s5, s12, s0    @ encoding: [0xc6,0xfe,0x00,0x2a]
+  vmaxnm.f64 d5, d14, d15
+@ CHECK-V81M: vmaxnm.f64 d5, d14, d15   @ encoding: [0x8e,0xfe,0x0f,0x5b]
+  vminnm.f32 s0, s0, s12
+@ CHECK-V81M: vminnm.f32 s0, s0, s12    @ encoding: [0x80,0xfe,0x46,0x0a]
+  vminnm.f64 d4, d6, d9
+@ CHECK-V81M: vminnm.f64 d4, d6, d9     @ encoding: [0x86,0xfe,0x49,0x4b]
+
+@ VRINT{Z,R,X}
+
+  it ge
+  vrintzge.f64 d3, d12
+@ CHECK-V81M: vrintzge.f64 d3, d12   @ encoding: [0xb6,0xee,0xcc,0x3b]
+  vrintz.f32 s3, s24
+@ CHECK-V81M: vrintz.f32 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x1a]
+  it lt
+  vrintrlt.f64 d5, d0
+@ CHECK-V81M: vrintrlt.f64 d5, d0    @ encoding: [0xb6,0xee,0x40,0x5b]
+  vrintr.f32 s0, s9
+@ CHECK-V81M: vrintr.f32 s0, s9      @ encoding: [0xb6,0xee,0x64,0x0a]
+  it eq
+  vrintxeq.f64 d14, d15
+@ CHECK-V81M: vrintxeq.f64 d14, d15  @ encoding: [0xb7,0xee,0x4f,0xeb]
+  it vs
+  vrintxvs.f32 s10, s14
+@ CHECK-V81M: vrintxvs.f32 s10, s14  @ encoding: [0xb7,0xee,0x47,0x5a]
+
+@ VRINT{A,N,P,M}
+
+  vrinta.f64 d3, d4
+@ CHECK-V81M: vrinta.f64 d3, d4     @ encoding: [0xb8,0xfe,0x44,0x3b]
+  vrinta.f32 s12, s1
+@ CHECK-V81M: vrinta.f32 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x6a]
+  vrintn.f64 d3, d4
+@ CHECK-V81M: vrintn.f64 d3, d4     @ encoding: [0xb9,0xfe,0x44,0x3b]
+  vrintn.f32 s12, s1
+@ CHECK-V81M: vrintn.f32 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x6a]
+  vrintp.f64 d3, d4
+@ CHECK-V81M: vrintp.f64 d3, d4     @ encoding: [0xba,0xfe,0x44,0x3b]
+  vrintp.f32 s12, s1
+@ CHECK-V81M: vrintp.f32 s12, s1    @ encoding: [0xba,0xfe,0x60,0x6a]
+  vrintm.f64 d3, d4
+@ CHECK-V81M: vrintm.f64 d3, d4     @ encoding: [0xbb,0xfe,0x44,0x3b]
+  vrintm.f32 s12, s1
+@ CHECK-V81M: vrintm.f32 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x6a]
+
+@ MVFR2
+
+  vmrs sp, mvfr2
+@ CHECK-V81M: vmrs sp, mvfr2        @ encoding: [0xf5,0xee,0x10,0xda]
diff --git a/llvm/test/MC/ARM/fp-armv8.s b/llvm/test/MC/ARM/fp-armv8.s
--- a/llvm/test/MC/ARM/fp-armv8.s
+++ b/llvm/test/MC/ARM/fp-armv8.s
@@ -12,13 +12,17 @@
   vcvtb.f16.f64 s4, d1
 @ CHECK: vcvtb.f16.f64 s4, d1     @ encoding: [0x41,0x2b,0xb3,0xee]
 
+  it ge
   vcvttge.f64.f16 d3, s1
 @ CHECK: vcvttge.f64.f16 d3, s1      @ encoding: [0xe0,0x3b,0xb2,0xae]
+  it gt
   vcvttgt.f16.f64 s5, d12
 @ CHECK: vcvttgt.f16.f64 s5, d12     @ encoding: [0xcc,0x2b,0xf3,0xce]
 
+  it eq
   vcvtbeq.f64.f16 d3, s1
 @ CHECK: vcvtbeq.f64.f16 d3, s1     @ encoding: [0x60,0x3b,0xb2,0x0e]
+  it lt
   vcvtblt.f16.f64 s4, d1
 @ CHECK: vcvtblt.f16.f64 s4, d1     @ encoding: [0x41,0x2b,0xb3,0xbe]
 
@@ -91,16 +95,20 @@
 
 @ VRINT{Z,R,X}
 
+  it ge
   vrintzge.f64 d3, d12
 @ CHECK: vrintzge.f64 d3, d12   @ encoding: [0xcc,0x3b,0xb6,0xae]
   vrintz.f32 s3, s24
 @ CHECK: vrintz.f32 s3, s24     @ encoding: [0xcc,0x1a,0xf6,0xee]
+  it lt
   vrintrlt.f64 d5, d0
 @ CHECK: vrintrlt.f64 d5, d0    @ encoding: [0x40,0x5b,0xb6,0xbe]
   vrintr.f32 s0, s9
 @ CHECK: vrintr.f32 s0, s9      @ encoding: [0x64,0x0a,0xb6,0xee]
+  it eq
   vrintxeq.f64 d28, d30
 @ CHECK: vrintxeq.f64 d28, d30  @ encoding: [0x6e,0xcb,0xf7,0x0e]
+  it vs
   vrintxvs.f32 s10, s14
 @ CHECK: vrintxvs.f32 s10, s14  @ encoding: [0x47,0x5a,0xb7,0x6e]
 
diff --git a/llvm/test/MC/ARM/fullfp16.s b/llvm/test/MC/ARM/fullfp16.s
--- a/llvm/test/MC/ARM/fullfp16.s
+++ b/llvm/test/MC/ARM/fullfp16.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=ARM
 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s --check-prefix=THUMB
+@ RUN llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=THUMB
+@ RUN llvm-mc -triple thumbv8.1m.main -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=THUMB
 
          vadd.f16  s0, s1, s0
 @ ARM:    vadd.f16 s0, s1, s0        @ encoding: [0x80,0x09,0x30,0xee]
diff --git a/llvm/test/MC/ARM/mve.s b/llvm/test/MC/ARM/mve.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/mve.s
@@ -0,0 +1,6088 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: asrl    r0, r1, #23  @ encoding: [0x50,0xea,0xef,0x51]
+# CHECK-NOFP: asrl    r0, r1, #23  @ encoding: [0x50,0xea,0xef,0x51]
+asrl    r0, r1, #23
+
+# CHECK: asrl    lr, r1, #27  @ encoding: [0x5e,0xea,0xef,0x61]
+# CHECK-NOFP: asrl    lr, r1, #27  @ encoding: [0x5e,0xea,0xef,0x61]
+asrl    lr, r1, #27
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NEXT: asrleq    lr, r1, #27  @ encoding: [0x5e,0xea,0xef,0x61]
+# CHECK-NOFP: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOFP-NEXT: asrleq    lr, r1, #27  @ encoding: [0x5e,0xea,0xef,0x61]
+it eq
+asrleq    lr, r1, #27
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+asrl    r3, r2, #33
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+asrl    r0, r1, #33
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+asrl    r0, r0, #32
+
+# CHECK: asrl    r0, r1, r4  @ encoding: [0x50,0xea,0x2d,0x41]
+# CHECK-NOFP: asrl    r0, r1, r4  @ encoding: [0x50,0xea,0x2d,0x41]
+asrl    r0, r1, r4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+asrl    r0, r0, r4
+
+# CHECK: cinc    lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+# CHECK-NOFP: cinc    lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+csinc   lr, r2, r2, hs
+
+# CHECK: cinc    lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+# CHECK-NOFP: cinc    lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+cinc    lr, r7, pl
+
+# CHECK: cinv    lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+# CHECK-NOFP: cinv    lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+cinv    lr, r12, hs
+
+# CHECK: cneg    lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+# CHECK-NOFP: cneg    lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+csneg   lr, r10, r10, lo
+
+# CHECK: csel    r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+# CHECK-NOFP: csel    r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+csel    r9, r9, r11, vc
+
+# CHECK: cset    lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+# CHECK-NOFP: cset    lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+cset    lr, eq
+
+# CHECK: csetm   lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+# CHECK-NOFP: csetm   lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+csetm   lr, hs
+
+# CHECK: csinc   lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+# CHECK-NOFP: csinc   lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+csinc   lr, r10, r7, le
+
+# CHECK: csinv   lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+# CHECK-NOFP: csinv   lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+csinv   lr, r5, zr, hs
+
+# CHECK: cinv    lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+# CHECK-NOFP: cinv    lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+csinv   lr, r2, r2, mi
+
+# CHECK: csneg   lr, r1, r11, vc  @ encoding: [0x51,0xea,0x7b,0xbe]
+# CHECK-NOFP: csneg   lr, r1, r11, vc  @ encoding: [0x51,0xea,0x7b,0xbe]
+csneg   lr, r1, r11, vc
+
+# CHECK: lsll    lr, r1, #11  @ encoding: [0x5e,0xea,0xcf,0x21]
+# CHECK-NOFP: lsll    lr, r1, #11  @ encoding: [0x5e,0xea,0xcf,0x21]
+lsll    lr, r1, #11
+
+# CHECK: lsll    lr, r1, r4  @ encoding: [0x5e,0xea,0x0d,0x41]
+# CHECK-NOFP: lsll    lr, r1, r4  @ encoding: [0x5e,0xea,0x0d,0x41]
+lsll    lr, r1, r4
+
+# CHECK: lsrl    lr, r1, #12  @ encoding: [0x5e,0xea,0x1f,0x31]
+# CHECK-NOFP: lsrl    lr, r1, #12  @ encoding: [0x5e,0xea,0x1f,0x31]
+lsrl    lr, r1, #12
+
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# CHECK-NOFP: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+sqrshr  lr, r12
+
+# CHECK: sqrshr  r11, r12  @ encoding: [0x5b,0xea,0x2d,0xcf]
+# CHECK-NOFP: sqrshr  r11, r12  @ encoding: [0x5b,0xea,0x2d,0xcf]
+sqrshr  r11, r12
+
+# CHECK: sqrshrl lr, r3, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+# CHECK-NOFP: sqrshrl lr, r3, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+sqrshrl lr, r3, r8
+
+# CHECK: sqshl   lr, #17  @ encoding: [0x5e,0xea,0x7f,0x4f]
+# CHECK-NOFP: sqshl   lr, #17  @ encoding: [0x5e,0xea,0x7f,0x4f]
+sqshl   lr, #17
+
+# CHECK: sqshll  lr, r11, #28  @ encoding: [0x5f,0xea,0x3f,0x7b]
+# CHECK-NOFP: sqshll  lr, r11, #28  @ encoding: [0x5f,0xea,0x3f,0x7b]
+sqshll  lr, r11, #28
+
+# CHECK: srshr   lr, #11  @ encoding: [0x5e,0xea,0xef,0x2f]
+# CHECK-NOFP: srshr   lr, #11  @ encoding: [0x5e,0xea,0xef,0x2f]
+srshr   lr, #11
+
+# CHECK: srshrl  lr, r11, #23  @ encoding: [0x5f,0xea,0xef,0x5b]
+# CHECK-NOFP: srshrl  lr, r11, #23  @ encoding: [0x5f,0xea,0xef,0x5b]
+srshrl  lr, r11, #23
+
+# CHECK: uqrshl  lr, r1  @ encoding: [0x5e,0xea,0x0d,0x1f]
+# CHECK-NOFP: uqrshl  lr, r1  @ encoding: [0x5e,0xea,0x0d,0x1f]
+uqrshl  lr, r1
+
+# CHECK: uqrshll lr, r1, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+# CHECK-NOFP: uqrshll lr, r1, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+uqrshll lr, r1, r4
+
+# CHECK: uqshl   r0, #1  @ encoding: [0x50,0xea,0x4f,0x0f]
+# CHECK-NOFP: uqshl   r0, #1  @ encoding: [0x50,0xea,0x4f,0x0f]
+uqshl   r0, #1
+
+# CHECK: uqshll  lr, r7, #7  @ encoding: [0x5f,0xea,0xcf,0x17]
+# CHECK-NOFP: uqshll  lr, r7, #7  @ encoding: [0x5f,0xea,0xcf,0x17]
+uqshll  lr, r7, #7
+
+# CHECK: urshr   r0, #10  @ encoding: [0x50,0xea,0x9f,0x2f]
+# CHECK-NOFP: urshr   r0, #10  @ encoding: [0x50,0xea,0x9f,0x2f]
+urshr   r0, #10
+
+# CHECK: urshrl  r0, r9, #29  @ encoding: [0x51,0xea,0x5f,0x79]
+# CHECK-NOFP: urshrl  r0, r9, #29  @ encoding: [0x51,0xea,0x5f,0x79]
+urshrl  r0, r9, #29
+
+# CHECK: vabav.s8  r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
+# CHECK-NOFP: vabav.s8  r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
+vabav.s8 r0, q1, q3
+
+# CHECK: vabav.s16  r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
+# CHECK-NOFP: vabav.s16  r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
+vabav.s16 r0, q1, q3
+
+# CHECK: vabav.s32  r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
+# CHECK-NOFP: vabav.s32  r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
+vabav.s32 r0, q1, q3
+
+# CHECK: vabav.u8  r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
+# CHECK-NOFP: vabav.u8  r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
+vabav.u8 r0, q1, q3
+
+# CHECK: vabav.u16  r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
+# CHECK-NOFP: vabav.u16  r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
+vabav.u16 r0, q1, q3
+
+# CHECK: vabav.u32  r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
+# CHECK-NOFP: vabav.u32  r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
+vabav.u32 r0, q1, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
+vabavt.s32 lr, q1, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
+vabave.u8 r12, q1, q3
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: instructions in IT block must be predicable
+it eq
+vabav.s16 lr, q1, q3
+
+# CHECK: vpteee.i8 eq, q0, q1 @ encoding: [0x41,0xfe,0x02,0x2f]
+# CHECK-NOFP: vpteee.i8 eq, q0, q1 @ encoding: [0x41,0xfe,0x02,0x2f]
+vpteee.i8 eq, q0, q1
+vabavt.s32 lr, q1, q3
+vabave.s32 lr, q1, q3
+vabave.s32 lr, q1, q3
+vabave.s32 lr, q1, q3
+
+# CHECK: vptttt.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x3f]
+# CHECK-NOFP: vptttt.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x3f]
+vptttt.s32 gt, q0, q1
+vabavt.u32 lr, q1, q3
+vabavt.s32 lr, q1, q3
+vabavt.s16 lr, q1, q3
+vabavt.s8 lr, q1, q3
+
+# CHECK: vptete.f16 ne, q0, q1 @ encoding: [0x71,0xfe,0x82,0xef]
+# CHECK-NOFP-NOT: vptete.f16 ne, q0, q1 @ encoding: [0x71,0xfe,0x82,0xef]
+vptete.f16 ne, q0, q1
+vabavt.s32 lr, q1, q3
+vabave.u32 lr, q1, q3
+vabavt.s32 lr, q1, q3
+vabave.s16 lr, q1, q3
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
+vabavt.s32 lr, q1, q3
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: instruction in VPT block must be predicable
+vpt.s8 le, q0, q1
+cinc lr, r2, lo
+
+# CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+# CHECK-NOFP: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+vaddv.s16 lr, q0
+
+# ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
+vaddv.s16 r1, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK-NOFP: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK-NOFP: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
+vpte.i8 eq, q0, q0
+vaddvt.s16 r0, q6
+vaddve.s16 r0, q6
+
+# CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+vaddva.s16 lr, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOFP: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+vpte.i8 eq, q0, q0
+vaddvat.s16 lr, q0
+vaddvae.s16 lr, q0
+
+# CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+# CHECK-NOFP: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+vaddlv.s32 r0, r9, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r0, r2, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r1, r3, q2
+
+# CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+# CHECK-NOFP: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+vaddlv.u32 r0, r1, q1
+
+# CHECK: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+vminnmv.f16 lr, q3
+
+# CHECK: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOFP-NOT: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+vminnmv.f32 lr, q1
+
+# CHECK: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOFP-NOT: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+vminnmav.f16 lr, q0
+
+# CHECK: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+vminnmav.f32 lr, q3
+
+# CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+# CHECK-NOFP: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+vminv.s8 lr, q0
+
+# CHECK: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+# CHECK-NOFP: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+vminv.s16 lr, q0
+
+# CHECK: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+# CHECK-NOFP: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+vminv.s32 lr, q2
+
+# CHECK: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+# CHECK-NOFP: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+vminv.u8 r0, q0
+
+# CHECK: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+# CHECK-NOFP: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+vminv.u32 r10, q3
+
+# CHECK: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+# CHECK-NOFP: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+vminav.s16 r0, q0
+
+# CHECK: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+# CHECK-NOFP: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+vminav.s8 r0, q1
+
+# CHECK: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+# CHECK-NOFP: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+vminav.s32 lr, q1
+
+# CHECK: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOFP-NOT: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+vmaxnmv.f16 lr, q1
+
+# CHECK: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOFP-NOT: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+vmaxnmv.f32 r10, q1
+
+# CHECK: vmaxnmav.f16 r0, q6  @ encoding: [0xec,0xfe,0x0c,0x0f]
+# CHECK-NOFP-NOT: vmaxnmav.f16 r0, q6  @ encoding: [0xec,0xfe,0x0c,0x0f]
+vmaxnmav.f16 r0, q6
+
+# CHECK: vmaxnmav.f32 lr, q7  @ encoding: [0xec,0xee,0x0e,0xef]
+# CHECK-NOFP-NOT: vmaxnmav.f32 lr, q7  @ encoding: [0xec,0xee,0x0e,0xef]
+vmaxnmav.f32 lr, q7
+
+# CHECK: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+# CHECK-NOFP: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+vmaxv.s8 lr, q4
+
+# CHECK: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+# CHECK-NOFP: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+vmaxv.s16 lr, q0
+
+# CHECK: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+# CHECK-NOFP: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+vmaxv.s32 r1, q1
+
+# CHECK: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+# CHECK-NOFP: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+vmaxv.u8 r0, q4
+
+# CHECK: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+# CHECK-NOFP: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+vmaxv.u16 r0, q1
+
+# CHECK: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+# CHECK-NOFP: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+vmaxv.u32 r1, q0
+
+# CHECK: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+# CHECK-NOFP: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+vmaxav.s8 lr, q6
+
+# CHECK: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+# CHECK-NOFP: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+vmaxav.s16 r0, q6
+
+# CHECK: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+# CHECK-NOFP: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+vmaxav.s32 r10, q7
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOFP: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+vmladav.s16 lr, q0, q7
+
+# CHECK: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+# CHECK-NOFP: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+vmladav.s32 lr, q0, q4
+
+# CHECK: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+# CHECK-NOFP: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+vmladav.u16 lr, q0, q7
+
+# CHECK: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+# CHECK-NOFP: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+vmladav.u32 lr, q0, q0
+
+# CHECK: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+# CHECK-NOFP: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+vmladava.s16 lr, q0, q4
+
+# CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+# CHECK-NOFP: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+vmladavx.s16 r0, q0, q7
+
+# CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+# CHECK-NOFP: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+vmladavax.s16 lr, q0, q7
+
+# CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+# CHECK-NOFP: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+vmladav.s8 lr, q3, q0
+
+# CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+# CHECK-NOFP: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+vmladav.u8 lr, q1, q7
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlaldavh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r1, r3, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r2, r4, q5, q2
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+# CHECK-NOFP: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+vrmlaldavhax.s32 lr, r1, q3, q0
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlalvh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOFP: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlalvh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvha.s32 lr, r1, q3, q6  @ encoding: [0x86,0xee,0x2c,0xef]
+# CHECK-NOFP: vrmlalvha.s32 lr, r1, q3, q6  @ encoding: [0x86,0xee,0x2c,0xef]
+vrmlalvha.s32 lr, r1, q3, q6
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+# CHECK-NOFP: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+vrmlalvha.u32 lr, r1, q7, q1
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOFP: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vmlsdav.s32 lr, q2, q6  @ encoding: [0xf5,0xee,0x0d,0xee]
+# CHECK-NOFP: vmlsdav.s32 lr, q2, q6  @ encoding: [0xf5,0xee,0x0d,0xee]
+vmlsdav.s32 lr, q2, q6
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vmlsdavaxt.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK-NOFP: vmlsdavaxt.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK: vmlsdavaxe.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK-NOFP: vmlsdavaxe.s16 lr, q1, q4  @ encoding: [0xf2,0xee,0x29,0xfe]
+vpte.i8 eq, q0, q0
+vmlsdavaxt.s16 lr, q1, q4
+vmlsdavaxe.s16 lr, q1, q4
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOFP: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+vmlav.s16 lr, q0, q7
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+# CHECK-NOFP: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+vmlaldav.s16 lr, r1, q4, q1
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+# CHECK-NOFP: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+vmlaldav.s32 lr, r11, q4, q1
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+# CHECK-NOFP: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+vmlalv.s32 r0, r1, q7, q6
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+# CHECK-NOFP: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+vmlalv.u16 lr, r11, q5, q4
+
+# CHECK: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
+# CHECK-NOFP-NOT: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
+vmaxnm.f32 q0, q1, q4
+
+# CHECK: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
+# CHECK-NOFP-NOT: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
+vminnm.f16 q3, q0, q1
+
+# CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+# CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+vmin.s8 q3, q0, q7
+
+# CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOFP: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+vmin.s16 q0, q1, q2
+
+# CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+# CHECK-NOFP: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+vmin.s32 q0, q1, q2
+
+# CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+vmin.u8 q0, q1, q2
+
+# CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+vmin.u16 q0, q1, q2
+
+# CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+vmin.u32 q0, q1, q2
+
+# CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+# CHECK-NOFP: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+vmax.s8 q3, q0, q7
+
+# CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+# CHECK-NOFP: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+vmax.s16 q0, q1, q2
+
+# CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+# CHECK-NOFP: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+vmax.s32 q0, q1, q2
+
+# CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+vmax.u8 q0, q1, q2
+
+# CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+vmax.u16 q0, q1, q2
+
+# CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+vmax.u32 q0, q1, q2
+
+# CHECK: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+# CHECK-NOFP: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+vshlc   q0, lr, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshlc   q0, lr, #33
+
+# CHECK: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+# CHECK-NOFP: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+vmovlb.s8 q0, q6
+
+# CHECK: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOFP: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+vmovlt.s8 q0, q4
+
+# CHECK: vpt.i8 eq, q0, q0
+# CHECK-NOFP: vpt.i8 eq, q0, q0
+# CHECK: vmovltt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOFP: vmovltt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+vpt.i8 eq, q0, q0
+vmovltt.s8 q0, q4
+
+# CHECK: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+# CHECK-NOFP: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+vmovlb.u8 q0, q0
+
+# CHECK: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+# CHECK-NOFP: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+vmovlt.u8 q0, q2
+
+# CHECK: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+# CHECK-NOFP: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+vmovlb.u16 q1, q0
+
+# CHECK: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+# CHECK-NOFP: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+vmovlt.u16 q0, q2
+
+# CHECK: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+# CHECK-NOFP: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+vshllb.s8 q0, q2, #8
+
+# CHECK: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+# CHECK-NOFP: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+vshllt.s8 q1, q5, #8
+
+# CHECK: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+# CHECK-NOFP: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+vshllb.s8 q0, q0, #7
+
+# CHECK: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+# CHECK-NOFP: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+vshllb.u8 q1, q1, #8
+
+# CHECK: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+# CHECK-NOFP: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+vshllt.u8 q0, q0, #8
+
+# CHECK: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+# CHECK-NOFP: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+vshllb.u8 q0, q0, #3
+
+# CHECK: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+# CHECK-NOFP: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+vshllb.u16 q0, q5, #16
+
+# CHECK: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+# CHECK-NOFP: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+vshllt.u16 q0, q3, #16
+
+# CHECK: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+# CHECK-NOFP: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+vshllt.s16 q0, q0, #16
+
+# CHECK: vshllt.s16 q0, q0, #14  @ encoding: [0xbe,0xee,0x40,0x1f]
+vshllt.s16 q0, q0, #14
+
+# CHECK: vshllt.s16 q0, q0, #11  @ encoding: [0xbb,0xee,0x40,0x1f]
+vshllt.s16 q0, q0, #11
+
+# CHECK: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+# CHECK-NOFP: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+vshllb.u16 q0, q2, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.s8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.u8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.u8 q0, q2, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.s16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.u16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.u16 q0, q2, #0
+
+# CHECK: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+# CHECK-NOFP: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+vrshrnb.i16 q0, q3, #1
+
+# CHECK: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+# CHECK-NOFP: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+vrshrnt.i16 q0, q2, #5
+
+# CHECK: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+# CHECK-NOFP: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+vrshrnb.i32 q0, q4, #8
+
+# CHECK: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+# CHECK-NOFP: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+vrshrnt.i32 q0, q2, #7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshrnb.i16 q0, q3, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshrnb.i32 q0, q3, #17
+
+# CHECK: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+# CHECK-NOFP: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+vshrnb.i16 q1, q2, #1
+
+# CHECK: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+# CHECK-NOFP: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+vshrnt.i16 q0, q1, #1
+
+# CHECK: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+# CHECK-NOFP: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+vshrnb.i32 q0, q0, #12
+
+# CHECK: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+# CHECK-NOFP: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+vshrnt.i32 q0, q2, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshrnb.i16 q1, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshrnb.i32 q1, q2, #17
+
+# CHECK: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+# CHECK-NOFP: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+vqrshrunb.s16 q0, q2, #8
+
+# CHECK: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+# CHECK-NOFP: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+vqrshrunt.s16 q0, q0, #6
+
+# CHECK: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+# CHECK-NOFP: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+vqrshrunt.s32 q0, q1, #8
+
+# CHECK: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+# CHECK-NOFP: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+vqrshrunb.s32 q0, q7, #13
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqrshrunb.s16 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqrshrunb.s32 q0, q2, #17
+
+# CHECK: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+# CHECK-NOFP: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+vqshrunb.s16 q0, q7, #5
+
+# CHECK: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+# CHECK-NOFP: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+vqshrunt.s16 q0, q1, #7
+
+# CHECK: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+# CHECK-NOFP: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+vqshrunb.s32 q0, q6, #4
+
+# CHECK: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+# CHECK-NOFP: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+vqshrunt.s32 q0, q2, #10
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqshrunt.s16 q0, q1, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqshrunb.s32 q0, q6, #17
+
+# CHECK: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+# CHECK-NOFP: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+vqrshrnb.s16 q0, q7, #8
+
+# CHECK: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+# CHECK-NOFP: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+vqrshrnt.u16 q1, q3, #4
+
+# CHECK: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+# CHECK-NOFP: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+vqrshrnb.u32 q0, q1, #7
+
+# CHECK: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+# CHECK-NOFP: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+vqrshrnt.s32 q0, q1, #11
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqrshrnb.s16 q0, q7, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqrshrnb.s32 q0, q7, #17
+
+# CHECK: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+# CHECK-NOFP: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+vqshrnb.s16 q0, q6, #5
+
+# CHECK: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+# CHECK-NOFP: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+vqshrnt.s16 q0, q1, #4
+
+# CHECK: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+# CHECK-NOFP: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+vqshrnb.u16 q0, q3, #7
+
+# CHECK: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+# CHECK-NOFP: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+vqshrnt.u16 q0, q2, #8
+
+# CHECK: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+# CHECK-NOFP: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+vqshrnt.s32 q1, q4, #3
+
+# CHECK: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+# CHECK-NOFP: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+vqshrnb.u32 q0, q2, #14
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqshrnb.s16 q0, q6, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqshrnb.u32 q0, q6, #17
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.s8 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.s16 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.s32 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.u8 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.u16 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.u32 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.i8 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.i16 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.i32 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.f16 q0, q1, q7
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOFP: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+vbic.f32 q0, q1, q7
+
+# CHECK: vrev64.8 q0, q4  @ encoding: [0xb0,0xff,0x48,0x00]
+# CHECK-NOFP: vrev64.8 q0, q4  @ encoding: [0xb0,0xff,0x48,0x00]
+vrev64.8 q0, q4
+
+# CHECK: vrev64.16 q1, q3  @ encoding: [0xb4,0xff,0x46,0x20]
+# CHECK-NOFP: vrev64.16 q1, q3  @ encoding: [0xb4,0xff,0x46,0x20]
+vrev64.16 q1, q3
+
+# CHECK: vrev64.32 q0, q2  @ encoding: [0xb8,0xff,0x44,0x00]
+# CHECK-NOFP: vrev64.32 q0, q2  @ encoding: [0xb8,0xff,0x44,0x00]
+vrev64.32 q0, q2
+
+# CHECK: vrev32.8 q0, q1  @ encoding: [0xb0,0xff,0xc2,0x00]
+# CHECK-NOFP: vrev32.8 q0, q1  @ encoding: [0xb0,0xff,0xc2,0x00]
+vrev32.8 q0, q1
+
+# CHECK: vrev32.16 q0, q5  @ encoding: [0xb4,0xff,0xca,0x00]
+# CHECK-NOFP: vrev32.16 q0, q5  @ encoding: [0xb4,0xff,0xca,0x00]
+vrev32.16 q0, q5
+
+# CHECK: vrev16.8 q0, q2  @ encoding: [0xb0,0xff,0x44,0x01]
+# CHECK-NOFP: vrev16.8 q0, q2  @ encoding: [0xb0,0xff,0x44,0x01]
+vrev16.8 q0, q2
+
+# CHECK: vmvn q0, q2  @ encoding: [0xb0,0xff,0xc4,0x05]
+# CHECK-NOFP: vmvn q0, q2  @ encoding: [0xb0,0xff,0xc4,0x05]
+vmvn q0, q2
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.s8 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.s16 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.s32 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.u8 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.u16 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.u32 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.i8 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.i16 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.i32 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.f16 q2, q1, q7
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOFP: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+veor.f32 q2, q1, q7
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.s8 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.s16 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.s32 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.u8 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.u16 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.u32 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.i8 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.i16 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.i32 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.f16 q0, q3, q2
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOFP: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+vorn.f32 q0, q3, q2
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.s8 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.s16 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.s32 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.u8 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.u16 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.u32 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.i8 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.i16 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.i32 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.f16 q1, q2, q1
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOFP: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+vorr.f32 q1, q2, q1
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.s8 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.s16 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.s32 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.u8 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.u16 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.u32 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.i8 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.i16 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.i32 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.f16 q0, q2, q0
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOFP: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+vand.f32 q0, q2, q0
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+# CHECK-NOFP: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+vmul.i8 q0, q0, q3
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+# CHECK-NOFP: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+vmul.i16 q6, q0, q3
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+# CHECK-NOFP: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+vmul.i32 q7, q3, q6
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+# CHECK-NOFP: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+vqrdmulh.s8 q0, q5, q5
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+# CHECK-NOFP: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+vqrdmulh.s16 q1, q4, q2
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+# CHECK-NOFP: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+vqrdmulh.s32 q0, q5, q0
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+# CHECK-NOFP: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+vqdmulh.s8 q0, q4, q5
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+# CHECK-NOFP: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+vqdmulh.s16 q6, q4, q0
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+# CHECK-NOFP: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+vqdmulh.s32 q5, q0, q6
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+# CHECK-NOFP: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+vsub.i8 q3, q2, q5
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+# CHECK-NOFP: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+vsub.i16 q0, q3, q6
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+# CHECK-NOFP: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+vsub.i32 q0, q0, q6
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+# CHECK-NOFP: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+vadd.i8 q0, q2, q2
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+# CHECK-NOFP: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+vadd.i16 q2, q2, q1
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+# CHECK-NOFP: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+vadd.i32 q0, q0, q6
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+# CHECK-NOFP: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+vqsub.s8 q1, q6, q0
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+# CHECK-NOFP: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+vqsub.s16 q0, q6, q1
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+# CHECK-NOFP: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+vqsub.s32 q0, q0, q5
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+# CHECK-NOFP: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+vqsub.u8 q0, q2, q6
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+# CHECK-NOFP: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+vqsub.u16 q0, q7, q1
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+# CHECK-NOFP: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+vqsub.u32 q1, q4, q7
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+# CHECK-NOFP: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+vqadd.s8 q0, q4, q6
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+# CHECK-NOFP: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+vqadd.s16 q0, q5, q5
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+# CHECK-NOFP: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+vqadd.s32 q0, q0, q4
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+# CHECK-NOFP: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+vqadd.u8 q0, q4, q2
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+# CHECK-NOFP: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+vqadd.u16 q4, q6, q6
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+# CHECK-NOFP: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+vqadd.u32 q0, q1, q2
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+# CHECK-NOFP: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+vabd.s8 q0, q0, q2
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+# CHECK-NOFP: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+vabd.s16 q1, q5, q4
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+# CHECK-NOFP: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+vabd.s32 q2, q3, q2
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+# CHECK-NOFP: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+vabd.u8 q1, q6, q4
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+# CHECK-NOFP: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+vabd.u16 q0, q6, q2
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+# CHECK-NOFP: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+vabd.u32 q0, q7, q4
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+# CHECK-NOFP: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+vrhadd.s8 q0, q1, q1
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+# CHECK-NOFP: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+vrhadd.s16 q0, q1, q0
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+# CHECK-NOFP: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+vrhadd.s32 q0, q4, q1
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+# CHECK-NOFP: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+vrhadd.u8 q1, q0, q6
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+# CHECK-NOFP: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+vrhadd.u16 q2, q2, q5
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+# CHECK-NOFP: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+vrhadd.u32 q2, q3, q0
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+# CHECK-NOFP: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+vhsub.s8 q0, q0, q2
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+# CHECK-NOFP: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+vhsub.s16 q1, q3, q1
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+# CHECK-NOFP: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+vhsub.s32 q0, q2, q5
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+# CHECK-NOFP: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+vhsub.u8 q0, q4, q2
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+# CHECK-NOFP: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+vhsub.u16 q0, q7, q5
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+# CHECK-NOFP: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+vhsub.u32 q2, q6, q4
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+# CHECK-NOFP: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+vhadd.s8 q0, q7, q0
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+# CHECK-NOFP: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+vhadd.s16 q4, q0, q2
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+# CHECK-NOFP: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+vhadd.s32 q0, q3, q1
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+# CHECK-NOFP: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+vhadd.u8 q3, q0, q3
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+# CHECK-NOFP: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+vhadd.u16 q0, q1, q3
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+# CHECK-NOFP: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+vhadd.u32 q0, q1, q3
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+# CHECK-NOFP: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+vdup.8 q6, r8
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+# CHECK-NOFP: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+vdup.16 q7, lr
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+# CHECK-NOFP: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+vdup.32 q1, r9
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOFP: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOFP: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+vpte.i8 eq, q0, q0
+vdupt.16 q0, r1
+vdupe.16 q0, r1
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+# CHECK-NOFP: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+vcls.s8 q2, q1
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+# CHECK-NOFP: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+vcls.s16 q0, q4
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+# CHECK-NOFP: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+vcls.s32 q0, q0
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+# CHECK-NOFP: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+vclz.i8 q0, q7
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+# CHECK-NOFP: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+vclz.i16 q4, q7
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+# CHECK-NOFP: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+vclz.i32 q7, q5
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+# CHECK-NOFP: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+vneg.s8 q1, q0
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+# CHECK-NOFP: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+vneg.s16 q0, q1
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+# CHECK-NOFP: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+vneg.s32 q7, q2
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+# CHECK-NOFP: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+vabs.s8 q1, q1
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+# CHECK-NOFP: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+vabs.s16 q0, q2
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+# CHECK-NOFP: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+vabs.s32 q0, q7
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+# CHECK-NOFP: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+vqneg.s8 q0, q0
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+# CHECK-NOFP: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+vqneg.s16 q6, q2
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+# CHECK-NOFP: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+vqneg.s32 q7, q2
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+# CHECK-NOFP: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+vqabs.s8 q2, q4
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+# CHECK-NOFP: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+vqabs.s16 q0, q2
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+# CHECK-NOFP: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+vqabs.s32 q0, q5
+
+# CHECK: vrintn.f16 q1, q0  @ encoding: [0xb6,0xff,0x40,0x24]
+# CHECK-NOFP-NOT: vrintn.f16 q1, q0  @ encoding: [0xb6,0xff,0x40,0x24]
+vrintn.f16 q1, q0
+
+# CHECK: vrintn.f32 q0, q4  @ encoding: [0xba,0xff,0x48,0x04]
+# CHECK-NOFP-NOT: vrintn.f32 q0, q4  @ encoding: [0xba,0xff,0x48,0x04]
+vrintn.f32 q0, q4
+
+# CHECK: vrinta.f16 q0, q1  @ encoding: [0xb6,0xff,0x42,0x05]
+# CHECK-NOFP-NOT: vrinta.f16 q0, q1  @ encoding: [0xb6,0xff,0x42,0x05]
+vrinta.f16 q0, q1
+
+# CHECK: vrinta.f32 q1, q3  @ encoding: [0xba,0xff,0x46,0x25]
+# CHECK-NOFP-NOT: vrinta.f32 q1, q3  @ encoding: [0xba,0xff,0x46,0x25]
+vrinta.f32 q1, q3
+
+# CHECK: vrintm.f16 q0, q5  @ encoding: [0xb6,0xff,0xca,0x06]
+# CHECK-NOFP-NOT: vrintm.f16 q0, q5  @ encoding: [0xb6,0xff,0xca,0x06]
+vrintm.f16 q0, q5
+
+# CHECK: vrintm.f32 q0, q4  @ encoding: [0xba,0xff,0xc8,0x06]
+# CHECK-NOFP-NOT: vrintm.f32 q0, q4  @ encoding: [0xba,0xff,0xc8,0x06]
+vrintm.f32 q0, q4
+
+# CHECK: vrintp.f16 q1, q0  @ encoding: [0xb6,0xff,0xc0,0x27]
+# CHECK-NOFP-NOT: vrintp.f16 q1, q0  @ encoding: [0xb6,0xff,0xc0,0x27]
+vrintp.f16 q1, q0
+
+# CHECK: vrintp.f32 q0, q1  @ encoding: [0xba,0xff,0xc2,0x07]
+# CHECK-NOFP-NOT: vrintp.f32 q0, q1  @ encoding: [0xba,0xff,0xc2,0x07]
+vrintp.f32 q0, q1
+
+# CHECK: vrintx.f16 q1, q2  @ encoding: [0xb6,0xff,0xc4,0x24]
+# CHECK-NOFP-NOT: vrintx.f16 q1, q2  @ encoding: [0xb6,0xff,0xc4,0x24]
+vrintx.f16 q1, q2
+
+# CHECK: vrintx.f32 q1, q1  @ encoding: [0xba,0xff,0xc2,0x24]
+# CHECK-NOFP-NOT: vrintx.f32 q1, q1  @ encoding: [0xba,0xff,0xc2,0x24]
+vrintx.f32 q1, q1
+
+# CHECK: vrintz.f16 q1, q6  @ encoding: [0xb6,0xff,0xcc,0x25]
+# CHECK-NOFP-NOT: vrintz.f16 q1, q6  @ encoding: [0xb6,0xff,0xcc,0x25]
+vrintz.f16 q1, q6
+
+# CHECK: vrintz.f32 q1, q0  @ encoding: [0xba,0xff,0xc0,0x25]
+# CHECK-NOFP-NOT: vrintz.f32 q1, q0  @ encoding: [0xba,0xff,0xc0,0x25]
+vrintz.f32 q1, q0
+
+# CHECK: vmul.f16 q2, q1, q3  @ encoding: [0x12,0xff,0x56,0x4d]
+# CHECK-NOFP-NOT: vmul.f16 q2, q1, q3  @ encoding: [0x12,0xff,0x56,0x4d]
+vmul.f16 q2, q1, q3
+
+# CHECK: vmul.f32 q0, q0, q5  @ encoding: [0x00,0xff,0x5a,0x0d]
+# CHECK-NOFP-NOT: vmul.f32 q0, q0, q5  @ encoding: [0x00,0xff,0x5a,0x0d]
+vmul.f32 q0, q0, q5
+
+# CHECK: vcmla.f16 q3, q2, q1, #0  @ encoding: [0x24,0xfc,0x42,0x68]
+# CHECK-NOFP-NOT: vcmla.f16 q3, q2, q1, #0  @ encoding: [0x24,0xfc,0x42,0x68]
+vcmla.f16 q3, q2, q1, #0
+
+# CHECK: vcmla.f16 q0, q0, q5, #90  @ encoding: [0xa0,0xfc,0x4a,0x08]
+# CHECK-NOFP-NOT: vcmla.f16 q0, q0, q5, #90  @ encoding: [0xa0,0xfc,0x4a,0x08]
+vcmla.f16 q0, q0, q5, #90
+
+# CHECK: vcmla.f16 q3, q7, q2, #180  @ encoding: [0x2e,0xfd,0x44,0x68]
+# CHECK-NOFP-NOT: vcmla.f16 q3, q7, q2, #180  @ encoding: [0x2e,0xfd,0x44,0x68]
+vcmla.f16 q3, q7, q2, #180
+
+# CHECK: vcmla.f16 q2, q7, q6, #270  @ encoding: [0xae,0xfd,0x4c,0x48]
+# CHECK-NOFP-NOT: vcmla.f16 q2, q7, q6, #270  @ encoding: [0xae,0xfd,0x4c,0x48]
+vcmla.f16 q2, q7, q6, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmla.f16 q3, q2, q1, #200
+
+# CHECK: vcmla.f32 q2, q6, q6, #0  @ encoding: [0x3c,0xfc,0x4c,0x48]
+# CHECK-NOFP-NOT: vcmla.f32 q2, q6, q6, #0  @ encoding: [0x3c,0xfc,0x4c,0x48]
+vcmla.f32 q2, q6, q6, #0
+
+# CHECK: vcmla.f32 q7, q1, q3, #90  @ encoding: [0xb2,0xfc,0x46,0xe8]
+# CHECK-NOFP-NOT: vcmla.f32 q7, q1, q3, #90  @ encoding: [0xb2,0xfc,0x46,0xe8]
+vcmla.f32 q7, q1, q3, #90
+
+# CHECK: vcmla.f32 q4, q5, q3, #180  @ encoding: [0x3a,0xfd,0x46,0x88]
+# CHECK-NOFP-NOT: vcmla.f32 q4, q5, q3, #180  @ encoding: [0x3a,0xfd,0x46,0x88]
+vcmla.f32 q4, q5, q3, #180
+
+# CHECK: vcmla.f32 q3, q2, q7, #270  @ encoding: [0xb4,0xfd,0x4e,0x68]
+# CHECK-NOFP-NOT: vcmla.f32 q3, q2, q7, #270  @ encoding: [0xb4,0xfd,0x4e,0x68]
+vcmla.f32 q3, q2, q7, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmla.f32 q3, q2, q1, #16
+
+# CHECK: vfma.f16 q0, q2, q3  @ encoding: [0x14,0xef,0x56,0x0c]
+# CHECK-NOFP-NOT: vfma.f16 q0, q2, q3  @ encoding: [0x14,0xef,0x56,0x0c]
+vfma.f16 q0, q2, q3
+
+# CHECK: vfma.f32 q0, q3, q7  @ encoding: [0x06,0xef,0x5e,0x0c]
+# CHECK-NOFP-NOT: vfma.f32 q0, q3, q7  @ encoding: [0x06,0xef,0x5e,0x0c]
+vfma.f32 q0, q3, q7
+
+# CHECK: vfms.f16 q0, q2, q5  @ encoding: [0x34,0xef,0x5a,0x0c]
+# CHECK-NOFP-NOT: vfms.f16 q0, q2, q5  @ encoding: [0x34,0xef,0x5a,0x0c]
+vfms.f16 q0, q2, q5
+
+# CHECK: vfms.f32 q1, q1, q2  @ encoding: [0x22,0xef,0x54,0x2c]
+# CHECK-NOFP-NOT: vfms.f32 q1, q1, q2  @ encoding: [0x22,0xef,0x54,0x2c]
+vfms.f32 q1, q1, q2
+
+# CHECK: vadd.f16 q0, q0, q5  @ encoding: [0x10,0xef,0x4a,0x0d]
+# CHECK-NOFP-NOT: vadd.f16 q0, q0, q5  @ encoding: [0x10,0xef,0x4a,0x0d]
+vadd.f16 q0, q0, q5
+
+# CHECK: vadd.f32 q1, q3, q0  @ encoding: [0x06,0xef,0x40,0x2d]
+# CHECK-NOFP-NOT: vadd.f32 q1, q3, q0  @ encoding: [0x06,0xef,0x40,0x2d]
+vadd.f32 q1, q3, q0
+
+# CHECK: vcadd.f16 q2, q1, q7, #90  @ encoding: [0x82,0xfc,0x4e,0x48]
+# CHECK-NOFP-NOT: vcadd.f16 q2, q1, q7, #90  @ encoding: [0x82,0xfc,0x4e,0x48]
+vcadd.f16 q2, q1, q7, #90
+
+# CHECK: vcadd.f16 q2, q5, q7, #270  @ encoding: [0x8a,0xfd,0x4e,0x48]
+# CHECK-NOFP-NOT: vcadd.f16 q2, q5, q7, #270  @ encoding: [0x8a,0xfd,0x4e,0x48]
+vcadd.f16 q2, q5, q7, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.f16 q2, q5, q7, #180
+
+# CHECK: vcadd.f32 q0, q4, q7, #90  @ encoding: [0x98,0xfc,0x4e,0x08]
+# CHECK-NOFP-NOT: vcadd.f32 q0, q4, q7, #90  @ encoding: [0x98,0xfc,0x4e,0x08]
+vcadd.f32 q0, q4, q7, #90
+
+# CHECK: vcadd.f32 q2, q2, q3, #270  @ encoding: [0x94,0xfd,0x46,0x48]
+# CHECK-NOFP-NOT: vcadd.f32 q2, q2, q3, #270  @ encoding: [0x94,0xfd,0x46,0x48]
+vcadd.f32 q2, q2, q3, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.f32 q2, q5, q7, #0
+
+# CHECK: vabd.f16 q0, q0, q6  @ encoding: [0x30,0xff,0x4c,0x0d]
+# CHECK-NOFP-NOT: vabd.f16 q0, q0, q6  @ encoding: [0x30,0xff,0x4c,0x0d]
+vabd.f16 q0, q0, q6
+
+# CHECK: vabd.f32 q0, q1, q4  @ encoding: [0x22,0xff,0x48,0x0d]
+# CHECK-NOFP-NOT: vabd.f32 q0, q1, q4  @ encoding: [0x22,0xff,0x48,0x0d]
+vabd.f32 q0, q1, q4
+
+# CHECK: vcvt.f16.s16 q1, q7, #11  @ encoding: [0xb5,0xef,0x5e,0x2c]
+# CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #11  @ encoding: [0xb5,0xef,0x5e,0x2c]
+vcvt.f16.s16 q1, q7, #11
+
+# CHECK: vcvt.s16.f16 q1, q1, #3  @ encoding: [0xbd,0xef,0x52,0x2d]
+# CHECK-NOFP-NOT: vcvt.s16.f16 q1, q1, #3  @ encoding: [0xbd,0xef,0x52,0x2d]
+vcvt.s16.f16 q1, q1, #3
+
+# CHECK: vcvt.f16.u16 q2, q1, #10  @ encoding: [0xb6,0xff,0x52,0x4c]
+# CHECK-NOFP-NOT: vcvt.f16.u16 q2, q1, #10  @ encoding: [0xb6,0xff,0x52,0x4c]
+vcvt.f16.u16 q2, q1, #10
+
+# CHECK: vcvt.u16.f16 q0, q0, #3  @ encoding: [0xbd,0xff,0x50,0x0d]
+# CHECK-NOFP-NOT: vcvt.u16.f16 q0, q0, #3  @ encoding: [0xbd,0xff,0x50,0x0d]
+vcvt.u16.f16 q0, q0, #3
+
+# CHECK: vcvt.f32.s32 q1, q7, #6  @ encoding: [0xba,0xef,0x5e,0x2e]
+# CHECK-NOFP-NOT: vcvt.f32.s32 q1, q7, #6  @ encoding: [0xba,0xef,0x5e,0x2e]
+vcvt.f32.s32 q1, q7, #6
+
+# CHECK: vcvt.s32.f32 q1, q0, #21  @ encoding: [0xab,0xef,0x50,0x2f]
+# CHECK-NOFP-NOT: vcvt.s32.f32 q1, q0, #21  @ encoding: [0xab,0xef,0x50,0x2f]
+vcvt.s32.f32 q1, q0, #21
+
+# CHECK: vcvt.f32.u32 q1, q4, #4  @ encoding: [0xbc,0xff,0x58,0x2e]
+# CHECK-NOFP-NOT: vcvt.f32.u32 q1, q4, #4  @ encoding: [0xbc,0xff,0x58,0x2e]
+vcvt.f32.u32 q1, q4, #4
+
+# CHECK: vcvt.u32.f32 q1, q5, #8  @ encoding: [0xb8,0xff,0x5a,0x2f]
+# CHECK-NOFP-NOT: vcvt.u32.f32 q1, q5, #8  @ encoding: [0xb8,0xff,0x5a,0x2f]
+vcvt.u32.f32 q1, q5, #8
+
+# CHECK: vcvta.s16.f16 q0, q7  @ encoding: [0xb7,0xff,0x4e,0x00]
+# CHECK-NOFP-NOT: vcvta.s16.f16 q0, q7  @ encoding: [0xb7,0xff,0x4e,0x00]
+vcvta.s16.f16 q0, q7
+
+# CHECK: vcvtn.u32.f32 q7, q6  @ encoding: [0xbb,0xff,0xcc,0xe1]
+# CHECK-NOFP-NOT: vcvtn.u32.f32 q7, q6  @ encoding: [0xbb,0xff,0xcc,0xe1]
+vcvtn.u32.f32 q7, q6
+
+# CHECK: vcvtp.s32.f32 q0, q7  @ encoding: [0xbb,0xff,0x4e,0x02]
+# CHECK-NOFP-NOT: vcvtp.s32.f32 q0, q7  @ encoding: [0xbb,0xff,0x4e,0x02]
+vcvtp.s32.f32 q0, q7
+
+# CHECK: vcvtm.u32.f32 q1, q4  @ encoding: [0xbb,0xff,0xc8,0x23]
+# CHECK-NOFP-NOT: vcvtm.u32.f32 q1, q4  @ encoding: [0xbb,0xff,0xc8,0x23]
+vcvtm.u32.f32 q1, q4
+
+# CHECK: vneg.f16 q0, q7  @ encoding: [0xb5,0xff,0xce,0x07]
+# CHECK-NOFP-NOT: vneg.f16 q0, q7  @ encoding: [0xb5,0xff,0xce,0x07]
+vneg.f16 q0, q7
+
+# CHECK: vneg.f32 q0, q2  @ encoding: [0xb9,0xff,0xc4,0x07]
+# CHECK-NOFP-NOT: vneg.f32 q0, q2  @ encoding: [0xb9,0xff,0xc4,0x07]
+vneg.f32 q0, q2
+
+# CHECK: vabs.f16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x07]
+# CHECK-NOFP-NOT: vabs.f16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x07]
+vabs.f16 q0, q2
+
+# CHECK: vabs.f32 q0, q0  @ encoding: [0xb9,0xff,0x40,0x07]
+# CHECK-NOFP-NOT: vabs.f32 q0, q0  @ encoding: [0xb9,0xff,0x40,0x07]
+vabs.f32 q0, q0
+
+# CHECK: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+# CHECK-NOFP: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+vshl.s8 q6, q6, q6
+
+# CHECK: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+# CHECK-NOFP: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+vshl.s16 q0, q4, q2
+
+# CHECK: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+# CHECK-NOFP: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+vshl.s32 q1, q1, q5
+
+# CHECK: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+# CHECK-NOFP: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+vshl.u8 q1, q7, q2
+
+# CHECK: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+# CHECK-NOFP: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+vshl.u16 q0, q4, q0
+
+# CHECK: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+# CHECK-NOFP: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+vshl.u32 q2, q2, q4
+
+# CHECK: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+# CHECK-NOFP: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+vqshl.s8 q0, q1, q6
+
+# CHECK: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+# CHECK-NOFP: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+vqshl.s16 q4, q3, q7
+
+# CHECK: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+# CHECK-NOFP: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+vqshl.s32 q0, q5, q5
+
+# CHECK: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+# CHECK-NOFP: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+vqshl.u8 q0, q0, q6
+
+# CHECK: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+# CHECK-NOFP: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+vqshl.u16 q0, q5, q4
+
+# CHECK: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+# CHECK-NOFP: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+vqshl.u32 q1, q0, q4
+
+# CHECK: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+# CHECK-NOFP: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+vqrshl.s8 q1, q6, q1
+
+# CHECK: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+# CHECK-NOFP: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+vqrshl.s16 q2, q4, q6
+
+# CHECK: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+# CHECK-NOFP: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+vqrshl.s32 q0, q0, q5
+
+# CHECK: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+# CHECK-NOFP: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+vqrshl.u8 q0, q2, q1
+
+# CHECK: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+# CHECK-NOFP: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+vqrshl.u16 q1, q6, q0
+
+# CHECK: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+# CHECK-NOFP: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+vqrshl.u32 q0, q0, q0
+
+# CHECK: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+# CHECK-NOFP: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+vrshl.s8 q0, q6, q4
+
+# CHECK: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+# CHECK-NOFP: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+vrshl.s16 q1, q4, q7
+
+# CHECK: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+# CHECK-NOFP: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+vrshl.s32 q1, q4, q4
+
+# CHECK: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+# CHECK-NOFP: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+vrshl.u8 q0, q3, q5
+
+# CHECK: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+# CHECK-NOFP: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+vrshl.u16 q5, q6, q5
+
+# CHECK: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+# CHECK-NOFP: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+vrshl.u32 q1, q7, q3
+
+# CHECK: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+# CHECK-NOFP: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+vsri.8 q0, q2, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vsri.8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vsri.8 q0, q2, #0
+
+# CHECK: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+# CHECK-NOFP: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+vsri.16 q0, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vsri.16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vsri.16 q0, q2, #0
+
+# CHECK: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+# CHECK-NOFP: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+vsri.32 q0, q1, #15
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vsri.32 q0, q2, #33
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vsri.32 q0, q2, #0
+
+# CHECK: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+# CHECK-NOFP: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+vsli.8 q0, q3, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vsli.8 q0, q3, #8
+
+# CHECK: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+# CHECK-NOFP: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+vsli.16 q0, q1, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vsli.16 q0, q3, #16
+
+# CHECK: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+# CHECK-NOFP: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+vsli.32 q0, q1, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vsli.32 q0, q1, #32
+
+# CHECK: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+# CHECK-NOFP: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+vqshl.s8 q0, q4, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshl.s8 q0, q4, #8
+
+# CHECK: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+# CHECK-NOFP: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+vqshl.u8 q0, q6, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshl.u8 q0, q4, #8
+
+# CHECK: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+# CHECK-NOFP: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+vqshl.s16 q1, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshl.s16 q1, q2, #16
+
+# CHECK: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+# CHECK-NOFP: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+vqshl.u16 q0, q5, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshl.u16 q1, q2, #16
+
+# CHECK: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+# CHECK-NOFP: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+vqshl.s32 q1, q3, #29
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshl.s32 q1, q3, #32
+
+# CHECK: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+# CHECK-NOFP: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+vqshl.u32 q0, q2, #19
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshl.u32 q0, q2, #32
+
+# CHECK: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+# CHECK-NOFP: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+vqshlu.s8 q0, q1, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshlu.s8 q0, q1, #8
+
+# CHECK: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+# CHECK-NOFP: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+vqshlu.s16 q2, q1, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshlu.s16 q0, q1, #16
+
+# CHECK: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+# CHECK-NOFP: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+vqshlu.s32 q0, q4, #26
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshlu.s32 q0, q1, #32
+
+# CHECK: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+# CHECK-NOFP: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+vrshr.s8 q1, q3, #7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshr.s8 q1, q3, #9
+
+# CHECK: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+# CHECK-NOFP: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+vrshr.u8 q1, q3, #2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshr.u8 q1, q3, #9
+
+# CHECK: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+# CHECK-NOFP: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+vrshr.s16 q0, q1, #10
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshr.s16 q0, q1, #17
+
+# CHECK: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+# CHECK-NOFP: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+vrshr.u16 q0, q5, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshr.u16 q0, q5, #20
+
+# CHECK: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+# CHECK-NOFP: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+vrshr.s32 q0, q5, #23
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vrshr.s32 q0, q5, #33
+
+# CHECK: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+# CHECK-NOFP: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+vrshr.u32 q0, q1, #30
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vrshr.u32 q0, q1, #55
+
+# CHECK: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+# CHECK-NOFP: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+vshr.s8 q0, q7, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshr.s8 q0, q7, #9
+
+# CHECK: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+# CHECK-NOFP: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+vshr.u8 q0, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshr.u8 q0, q2, #9
+
+# CHECK: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+# CHECK-NOFP: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+vshr.s16 q0, q3, #16
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshr.s16 q0, q2, #17
+
+# CHECK: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+# CHECK-NOFP: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+vshr.u16 q7, q6, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshr.u16 q7, q6, #20
+
+# CHECK: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+# CHECK-NOFP: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+vshr.s32 q0, q6, #24
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshr.s32 q0, q6, #33
+
+# CHECK: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+# CHECK-NOFP: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+vshr.u32 q2, q5, #30
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshr.u32 q2, q5, #33
+
+# CHECK: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+# CHECK-NOFP: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+vshl.i8 q0, q6, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vshl.i8 q0, q6, #8
+
+# CHECK: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+# CHECK-NOFP: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+vshl.i16 q1, q0, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vshl.i16 q1, q0, #16
+
+# CHECK: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+# CHECK-NOFP: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+vshl.i32 q2, q2, #26
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vshl.i32 q2, q2, #33
+
+# CHECK: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+vpsel   q0, q5, q2
+
+# CHECK: vcmp.f16 eq, q0, q4  @ encoding: [0x31,0xfe,0x08,0x0f]
+# CHECK-NOFP-NOT: vcmp.f16 eq, q0, q4  @ encoding: [0x31,0xfe,0x08,0x0f]
+vcmp.f16 eq, q0, q4
+
+# CHECK: vcmp.f16 ne, q2, q7  @ encoding: [0x35,0xfe,0x8e,0x0f]
+# CHECK-NOFP-NOT: vcmp.f16 ne, q2, q7  @ encoding: [0x35,0xfe,0x8e,0x0f]
+vcmp.f16 ne, q2, q7
+
+# CHECK: vcmp.f16 ge, q0, q0  @ encoding: [0x31,0xfe,0x00,0x1f]
+# CHECK-NOFP-NOT: vcmp.f16 ge, q0, q0  @ encoding: [0x31,0xfe,0x00,0x1f]
+vcmp.f16 ge, q0, q0
+
+# CHECK: vcmp.f16 lt, q0, q1  @ encoding: [0x31,0xfe,0x82,0x1f]
+# CHECK-NOFP-NOT: vcmp.f16 lt, q0, q1  @ encoding: [0x31,0xfe,0x82,0x1f]
+vcmp.f16 lt, q0, q1
+
+# CHECK: vcmp.f16 gt, q1, q4  @ encoding: [0x33,0xfe,0x09,0x1f]
+# CHECK-NOFP-NOT: vcmp.f16 gt, q1, q4  @ encoding: [0x33,0xfe,0x09,0x1f]
+vcmp.f16 gt, q1, q4
+
+# CHECK: vcmp.f16 le, q2, q6  @ encoding: [0x35,0xfe,0x8d,0x1f]
+# CHECK-NOFP-NOT: vcmp.f16 le, q2, q6  @ encoding: [0x35,0xfe,0x8d,0x1f]
+vcmp.f16 le, q2, q6
+
+# CHECK: vcmp.f32 eq, q2, q5  @ encoding: [0x35,0xee,0x0a,0x0f]
+# CHECK-NOFP-NOT: vcmp.f32 eq, q2, q5  @ encoding: [0x35,0xee,0x0a,0x0f]
+vcmp.f32 eq, q2, q5
+
+# CHECK: vcmp.f32 ne, q3, q4  @ encoding: [0x37,0xee,0x88,0x0f]
+# CHECK-NOFP-NOT: vcmp.f32 ne, q3, q4  @ encoding: [0x37,0xee,0x88,0x0f]
+vcmp.f32 ne, q3, q4
+
+# CHECK: vcmp.f32 ge, q0, q7  @ encoding: [0x31,0xee,0x0e,0x1f]
+# CHECK-NOFP-NOT: vcmp.f32 ge, q0, q7  @ encoding: [0x31,0xee,0x0e,0x1f]
+vcmp.f32 ge, q0, q7
+
+# CHECK: vcmp.f32 lt, q5, q2  @ encoding: [0x3b,0xee,0x84,0x1f]
+# CHECK-NOFP-NOT: vcmp.f32 lt, q5, q2  @ encoding: [0x3b,0xee,0x84,0x1f]
+vcmp.f32 lt, q5, q2
+
+# CHECK: vcmp.f32 gt, q2, q7  @ encoding: [0x35,0xee,0x0f,0x1f]
+# CHECK-NOFP-NOT: vcmp.f32 gt, q2, q7  @ encoding: [0x35,0xee,0x0f,0x1f]
+vcmp.f32 gt, q2, q7
+
+# CHECK: vcmp.f32 le, q2, q4  @ encoding: [0x35,0xee,0x89,0x1f]
+# CHECK-NOFP-NOT: vcmp.f32 le, q2, q4  @ encoding: [0x35,0xee,0x89,0x1f]
+vcmp.f32 le, q2, q4
+
+# CHECK: vcmp.i8 eq, q4, q6  @ encoding: [0x09,0xfe,0x0c,0x0f]
+# CHECK-NOFP: vcmp.i8 eq, q4, q6  @ encoding: [0x09,0xfe,0x0c,0x0f]
+vcmp.i8 eq, q4, q6
+
+# CHECK: vcmp.i8 ne, q2, q2  @ encoding: [0x05,0xfe,0x84,0x0f]
+# CHECK-NOFP: vcmp.i8 ne, q2, q2  @ encoding: [0x05,0xfe,0x84,0x0f]
+vcmp.i8 ne, q2, q2
+
+# CHECK: vcmp.s8 ge, q0, q0  @ encoding: [0x01,0xfe,0x00,0x1f]
+# CHECK-NOFP: vcmp.s8 ge, q0, q0  @ encoding: [0x01,0xfe,0x00,0x1f]
+vcmp.s8 ge, q0, q0
+
+# CHECK: vcmp.s8 lt, q2, q7  @ encoding: [0x05,0xfe,0x8e,0x1f]
+# CHECK-NOFP: vcmp.s8 lt, q2, q7  @ encoding: [0x05,0xfe,0x8e,0x1f]
+vcmp.s8 lt, q2, q7
+
+# CHECK: vcmp.s8 gt, q4, q3  @ encoding: [0x09,0xfe,0x07,0x1f]
+# CHECK-NOFP: vcmp.s8 gt, q4, q3  @ encoding: [0x09,0xfe,0x07,0x1f]
+vcmp.s8 gt, q4, q3
+
+# CHECK: vcmp.s8 le, q7, q3  @ encoding: [0x0f,0xfe,0x87,0x1f]
+# CHECK-NOFP: vcmp.s8 le, q7, q3  @ encoding: [0x0f,0xfe,0x87,0x1f]
+vcmp.s8 le, q7, q3
+
+# CHECK: vcmp.u8 hi, q1, q4  @ encoding: [0x03,0xfe,0x89,0x0f]
+# CHECK-NOFP: vcmp.u8 hi, q1, q4  @ encoding: [0x03,0xfe,0x89,0x0f]
+vcmp.u8 hi, q1, q4
+
+# CHECK: vcmp.u8 cs, q1, q4  @ encoding: [0x03,0xfe,0x09,0x0f]
+# CHECK-NOFP: vcmp.u8 cs, q1, q4  @ encoding: [0x03,0xfe,0x09,0x0f]
+vcmp.u8 cs, q1, q4
+
+# CHECK: vcmp.i16 eq, q4, q7  @ encoding: [0x19,0xfe,0x0e,0x0f]
+# CHECK-NOFP: vcmp.i16 eq, q4, q7  @ encoding: [0x19,0xfe,0x0e,0x0f]
+vcmp.i16 eq, q4, q7
+
+# CHECK: vcmp.i16 ne, q2, q1  @ encoding: [0x15,0xfe,0x82,0x0f]
+# CHECK-NOFP: vcmp.i16 ne, q2, q1  @ encoding: [0x15,0xfe,0x82,0x0f]
+vcmp.i16 ne, q2, q1
+
+# CHECK: vcmp.s16 ge, q1, q7  @ encoding: [0x13,0xfe,0x0e,0x1f]
+# CHECK-NOFP: vcmp.s16 ge, q1, q7  @ encoding: [0x13,0xfe,0x0e,0x1f]
+vcmp.s16 ge, q1, q7
+
+# CHECK: vcmp.s16 lt, q0, q1  @ encoding: [0x11,0xfe,0x82,0x1f]
+# CHECK-NOFP: vcmp.s16 lt, q0, q1  @ encoding: [0x11,0xfe,0x82,0x1f]
+vcmp.s16 lt, q0, q1
+
+# CHECK: vcmp.s16 gt, q1, q7  @ encoding: [0x13,0xfe,0x0f,0x1f]
+# CHECK-NOFP: vcmp.s16 gt, q1, q7  @ encoding: [0x13,0xfe,0x0f,0x1f]
+vcmp.s16 gt, q1, q7
+
+# CHECK: vcmp.s16 le, q2, q1  @ encoding: [0x15,0xfe,0x83,0x1f]
+# CHECK-NOFP: vcmp.s16 le, q2, q1  @ encoding: [0x15,0xfe,0x83,0x1f]
+vcmp.s16 le, q2, q1
+
+# CHECK: vcmp.u16 hi, q1, q4  @ encoding: [0x13,0xfe,0x89,0x0f]
+# CHECK-NOFP: vcmp.u16 hi, q1, q4  @ encoding: [0x13,0xfe,0x89,0x0f]
+vcmp.u16 hi, q1, q4
+
+# CHECK: vcmp.u16 cs, q1, q4  @ encoding: [0x13,0xfe,0x09,0x0f]
+# CHECK-NOFP: vcmp.u16 cs, q1, q4  @ encoding: [0x13,0xfe,0x09,0x0f]
+vcmp.u16 cs, q1, q4
+
+# CHECK: vcmp.i32 eq, q2, q7  @ encoding: [0x25,0xfe,0x0e,0x0f]
+# CHECK-NOFP: vcmp.i32 eq, q2, q7  @ encoding: [0x25,0xfe,0x0e,0x0f]
+vcmp.i32 eq, q2, q7
+
+# CHECK: vcmp.i32 ne, q2, q4  @ encoding: [0x25,0xfe,0x88,0x0f]
+# CHECK-NOFP: vcmp.i32 ne, q2, q4  @ encoding: [0x25,0xfe,0x88,0x0f]
+vcmp.i32 ne, q2, q4
+
+# CHECK: vcmp.s32 ge, q5, q5  @ encoding: [0x2b,0xfe,0x0a,0x1f]
+# CHECK-NOFP: vcmp.s32 ge, q5, q5  @ encoding: [0x2b,0xfe,0x0a,0x1f]
+vcmp.s32 ge, q5, q5
+
+# CHECK: vcmp.s32 lt, q2, q2  @ encoding: [0x25,0xfe,0x84,0x1f]
+# CHECK-NOFP: vcmp.s32 lt, q2, q2  @ encoding: [0x25,0xfe,0x84,0x1f]
+vcmp.s32 lt, q2, q2
+
+# CHECK: vcmp.s32 gt, q0, q1  @ encoding: [0x21,0xfe,0x03,0x1f]
+# CHECK-NOFP: vcmp.s32 gt, q0, q1  @ encoding: [0x21,0xfe,0x03,0x1f]
+vcmp.s32 gt, q0, q1
+
+# CHECK: vcmp.s32 le, q5, q4  @ encoding: [0x2b,0xfe,0x89,0x1f]
+# CHECK-NOFP: vcmp.s32 le, q5, q4  @ encoding: [0x2b,0xfe,0x89,0x1f]
+vcmp.s32 le, q5, q4
+
+# CHECK: vcmp.u32 hi, q1, q4  @ encoding: [0x23,0xfe,0x89,0x0f]
+# CHECK-NOFP: vcmp.u32 hi, q1, q4  @ encoding: [0x23,0xfe,0x89,0x0f]
+vcmp.u32 hi, q1, q4
+
+# CHECK: vcmp.u32 cs, q1, q4  @ encoding: [0x23,0xfe,0x09,0x0f]
+# CHECK-NOFP: vcmp.u32 cs, q1, q4  @ encoding: [0x23,0xfe,0x09,0x0f]
+vcmp.u32 cs, q1, q4
+
+# CHECK: vcmp.f16 gt, q4, zr  @ encoding: [0x39,0xfe,0x6f,0x1f]
+# CHECK-NOFP-NOT: vcmp.f16 gt, q4, zr  @ encoding: [0x39,0xfe,0x6f,0x1f]
+vcmp.f16 gt, q4, zr
+
+# CHECK: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOFP: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+vqdmladhx.s8 q1, q6, q6
+
+# CHECK: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOFP: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+vqdmladhx.s16 q0, q1, q4
+
+# CHECK: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOFP: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+vqdmladhx.s32 q0, q3, q7
+
+# CHECK: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOFP: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+vqdmladh.s8 q0, q1, q1
+
+# CHECK: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOFP: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+vqdmladh.s16 q0, q2, q2
+
+# CHECK: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOFP: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+vqdmladh.s32 q1, q5, q7
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+vqrdmladhx.s8 q0, q7, q0
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+vqrdmladhx.s16 q0, q0, q1
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+vqrdmladhx.s32 q1, q0, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmladhx.s32 q1, q1, q0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmladhx.s32 q1, q0, q1
+
+# CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+vqrdmladh.s8 q0, q6, q2
+
+# CHECK: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOFP: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+vqrdmladh.s16 q1, q5, q4
+
+# CHECK: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOFP: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+vqrdmladh.s32 q0, q2, q2
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOFP: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+vqdmlsdhx.s8 q1, q4, q7
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOFP: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+vqdmlsdhx.s16 q0, q2, q5
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOFP: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+vqdmlsdhx.s32 q3, q4, q6
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOFP: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+vqdmlsdh.s8 q0, q3, q6
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOFP: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+vqdmlsdh.s16 q0, q4, q1
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOFP: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+vqdmlsdh.s32 q2, q5, q0
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+vqrdmlsdhx.s8 q0, q3, q1
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOFP: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+vqrdmlsdhx.s16 q0, q1, q4
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOFP: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+vqrdmlsdhx.s32 q1, q6, q3
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOFP: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+vqrdmlsdh.s8 q3, q3, q0
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+vqrdmlsdh.s16 q0, q7, q4
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+vqrdmlsdh.s32 q0, q6, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqrdmlsdh.s32 q0, q0, q7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqrdmlsdh.s32 q0, q6, q0
+
+# CHECK: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+vcmul.f16 q6, q2, q5, #0
+
+# CHECK: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+vcmul.f16 q1, q0, q5, #90
+
+# CHECK: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+vcmul.f16 q1, q0, q5, #180
+
+# CHECK: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+vcmul.f16 q1, q0, q5, #270
+
+# CHECK: vcmul.f16 q1, q0, q1, #270  @ encoding: [0x30,0xee,0x03,0x3e]
+# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q1, #270  @ encoding: [0x30,0xee,0x03,0x3e]
+vcmul.f16 q1, q0, q1, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmul.f16 q1, q0, q5, #300
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vcmul.f32 q1, q1, q5, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vcmul.f32 q1, q5, q1, #0
+
+# CHECK: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOFP-NOT: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+vcmul.f32 q1, q7, q5, #0
+
+# CHECK: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOFP-NOT: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+vcmul.f32 q3, q4, q2, #90
+
+# CHECK: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOFP-NOT: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+vcmul.f32 q5, q1, q3, #180
+
+# CHECK: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOFP-NOT: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+vcmul.f32 q0, q7, q4, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcmul.f32 q1, q0, q5, #300
+
+# CHECK: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOFP: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+vmullb.s8 q2, q6, q0
+
+# CHECK: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOFP: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+vmullb.s16 q3, q4, q3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vmullb.s32 q3, q4, q3
+
+# CHECK: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOFP: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+vmullb.s32 q3, q5, q6
+
+# CHECK: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+vmullt.s8 q0, q6, q2
+
+# CHECK: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOFP: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+vmullt.s16 q0, q0, q2
+
+# CHECK: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOFP: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+vmullt.s32 q2, q4, q4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vmullt.s32 q4, q4, q2
+
+# CHECK: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOFP: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+vmullb.p8 q2, q3, q7
+
+# CHECK: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOFP: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+vmullb.p16 q0, q1, q3
+
+# CHECK: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOFP: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+vmullt.p8 q1, q1, q7
+
+# CHECK: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOFP: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+vmullt.p16 q0, q7, q7
+
+# CHECK: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOFP: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+vmulh.s8 q0, q4, q5
+
+# CHECK: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+vmulh.s16 q0, q7, q4
+
+# CHECK: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOFP: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+vmulh.s32 q0, q7, q4
+
+# CHECK: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOFP: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+vmulh.u8 q3, q5, q2
+
+# CHECK: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOFP: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+vmulh.u16 q2, q7, q4
+
+# CHECK: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOFP: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+vmulh.u32 q1, q3, q2
+
+# CHECK: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+vrmulh.s8 q1, q1, q2
+
+# CHECK: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOFP: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+vrmulh.s16 q1, q1, q2
+
+# CHECK: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOFP: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+vrmulh.s32 q3, q1, q0
+
+# CHECK: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOFP: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+vrmulh.u8 q1, q6, q0
+
+# CHECK: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOFP: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+vrmulh.u16 q4, q3, q6
+
+# CHECK: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOFP: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+vrmulh.u32 q1, q2, q2
+
+# CHECK: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOFP: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+vqmovnb.s16 q0, q1
+
+# CHECK: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOFP: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+vqmovnt.s16 q2, q0
+
+# CHECK: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOFP: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+vqmovnb.s32 q0, q5
+
+# CHECK: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOFP: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+vqmovnt.s32 q0, q1
+
+# CHECK: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+vqmovnb.u16 q0, q4
+
+# CHECK: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOFP: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+vqmovnt.u16 q0, q7
+
+# CHECK: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOFP: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+vqmovnb.u32 q0, q4
+
+# CHECK: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOFP: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+vqmovnt.u32 q0, q2
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+vcvtt.f16.f32 q1, q4
+
+# CHECK: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOFP-NOT: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+vcvtb.f32.f16 q0, q3
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOFP: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+vqmovunb.s16 q0, q3
+
+# CHECK: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOFP: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+vqmovunt.s16 q4, q1
+
+# CHECK: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOFP: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+vqmovunb.s32 q1, q7
+
+# CHECK: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOFP: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+vqmovunt.s32 q0, q2
+
+# CHECK: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOFP: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+vmovnb.i16 q1, q5
+
+# CHECK: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOFP: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+vmovnt.i16 q0, q0
+
+# CHECK: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOFP: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+vmovnb.i32 q1, q0
+
+# CHECK: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOFP: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+vmovnt.i32 q3, q3
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOFP: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+vmaxa.s8 q0, q7
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+vmaxa.s16 q1, q0
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOFP: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+vmaxa.s32 q1, q0
+
+# CHECK: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+# CHECK-NOFP-NOT: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+vmaxnma.f16 q1, q1
+
+# CHECK: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+# CHECK-NOFP-NOT: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+vmaxnma.f32 q2, q6
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOFP: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+vmina.s8 q1, q7
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOFP: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+vmina.s16 q1, q4
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOFP: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+vmina.s32 q0, q7
+
+# CHECK: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+# CHECK-NOFP-NOT: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+vminnma.f16 q0, q2
+
+# CHECK: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+# CHECK-NOFP-NOT: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+vminnma.f32 q0, q1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+vhcadd.s8 q3, q7, q5, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s8 q3, q7, q5, #0
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+vhcadd.s16 q0, q0, q6, #90
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOFP: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+vhcadd.s16 q3, q1, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vhcadd.s32 q3, q4, q5, #0
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOFP: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+vhcadd.s32 q3, q4, q5, #90
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOFP: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+vhcadd.s32 q6, q7, q2, #270
+
+# CHECK: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOFP: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+vadc.i32 q1, q0, q2
+
+# CHECK: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOFP: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+vadci.i32 q0, q1, q1
+
+# CHECK: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOFP: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+vcadd.i8 q1, q0, q2, #90
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i8 q1, q0, q2, #0
+
+# CHECK: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOFP: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+vcadd.i16 q0, q2, q3, #90
+
+# CHECK: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOFP: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+vcadd.i16 q0, q5, q5, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i16 q1, q0, q2, #0
+
+# CHECK: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOFP: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+vcadd.i32 q4, q2, q5, #90
+
+# CHECK: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOFP: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+vcadd.i32 q5, q5, q0, #270
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vcadd.i32 q4, q2, q5, #0
+
+# CHECK: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOFP: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+vsbc.i32 q3, q1, q1
+
+# CHECK: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOFP: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+vsbci.i32 q2, q6, q2
+
+# CHECK: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+vqdmullb.s16 q0, q4, q5
+
+# CHECK: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q6, q5
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+vqdmullt.s32 q0, q7, q5
+
+# CHECK: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e]
+# CHECK-NOFP: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e]
+vld20.8 {q0, q1}, [sp]
+
+# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
+# CHECK-NOFP: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
+vld20.8 {q0, q1}, [r0]
+
+# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
+# CHECK-NOFP: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
+vld20.8 {q0, q1}, [r0]!
+
+# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
+# CHECK-NOFP: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
+vld20.8 {q0, q1}, [r11]
+
+# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
+# CHECK-NOFP: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
+vld20.8 {q5, q6}, [r0]!
+
+# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
+# CHECK-NOFP: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
+vld21.8 {q0, q1}, [r0]
+
+# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
+# CHECK-NOFP: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
+vld21.8 {q3, q4}, [r0]!
+
+# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
+# CHECK-NOFP: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
+vld20.16 {q0, q1}, [r0]
+
+# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
+# CHECK-NOFP: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
+vld20.16 {q0, q1}, [r0]!
+
+# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
+# CHECK-NOFP: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
+vld20.16 {q0, q1}, [r11]
+
+# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
+# CHECK-NOFP: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
+vld20.16 {q5, q6}, [r0]!
+
+# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
+# CHECK-NOFP: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
+vld21.16 {q0, q1}, [r0]
+
+# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
+# CHECK-NOFP: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
+vld21.16 {q3, q4}, [r0]!
+
+# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
+# CHECK-NOFP: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
+vld20.32 {q0, q1}, [r0]
+
+# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
+# CHECK-NOFP: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
+vld20.32 {q0, q1}, [r0]!
+
+# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
+# CHECK-NOFP: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
+vld20.32 {q0, q1}, [r11]
+
+# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
+# CHECK-NOFP: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
+vld20.32 {q5, q6}, [r0]!
+
+# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
+# CHECK-NOFP: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
+vld21.32 {q0, q1}, [r0]
+
+# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
+# CHECK-NOFP: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
+vld21.32 {q3, q4}, [r0]!
+
+# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
+# CHECK-NOFP: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
+vst20.8 {q0, q1}, [r0]
+
+# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
+# CHECK-NOFP: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
+vst20.8 {q0, q1}, [r0]!
+
+# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
+# CHECK-NOFP: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
+vst20.8 {q0, q1}, [r11]
+
+# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
+# CHECK-NOFP: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
+vst20.8 {q5, q6}, [r0]!
+
+# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
+# CHECK-NOFP: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
+vst21.8 {q0, q1}, [r0]
+
+# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
+# CHECK-NOFP: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
+vst21.8 {q3, q4}, [r0]!
+
+# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
+# CHECK-NOFP: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
+vst20.16 {q0, q1}, [r0]
+
+# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
+# CHECK-NOFP: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
+vst20.16 {q0, q1}, [r0]!
+
+# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
+# CHECK-NOFP: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
+vst20.16 {q0, q1}, [r11]
+
+# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
+# CHECK-NOFP: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
+vst20.16 {q5, q6}, [r0]!
+
+# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
+# CHECK-NOFP: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
+vst21.16 {q0, q1}, [r0]
+
+# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
+# CHECK-NOFP: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
+vst21.16 {q3, q4}, [r0]!
+
+# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
+# CHECK-NOFP: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
+vst20.32 {q0, q1}, [r0]
+
+# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
+# CHECK-NOFP: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
+vst20.32 {q0, q1}, [r0]!
+
+# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
+# CHECK-NOFP: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
+vst20.32 {q0, q1}, [r11]
+
+# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
+# CHECK-NOFP: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
+vst20.32 {q5, q6}, [r0]!
+
+# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
+# CHECK-NOFP: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
+vst21.32 {q0, q1}, [r0]
+
+# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
+# CHECK-NOFP: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
+vst21.32 {q3, q4}, [r0]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.8 {q0, q1}, [sp]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.64 {q0, q1}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
+vld20.32 {q0, q2}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.32 {q0, q1, q2}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.32 {q0}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vld20.32 q0, q1, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
+vld20.32 {q7, q8}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
+vld20.32 {d0, d1}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vld22.32 {q0, q1}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.32 {q0, q1}, [pc]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld20.32 {q0, q1}, [r0, #4]
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
+# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
+vld40.8 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
+# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
+vld40.8 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
+# CHECK-NOFP: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
+vld40.8 {q0, q1, q2, q3}, [r11]
+
+# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
+# CHECK-NOFP: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
+vld40.8 {q3, q4, q5, q6}, [r0]!
+
+# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
+# CHECK-NOFP: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
+vld41.8 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
+# CHECK-NOFP: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
+vld41.8 {q4, q5, q6, q7}, [r0]!
+
+# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
+# CHECK-NOFP: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
+vld42.8 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
+# CHECK-NOFP: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
+vld42.8 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
+# CHECK-NOFP: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
+vld43.8 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
+# CHECK-NOFP: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
+vld43.8 {q4, q5, q6, q7}, [r0]!
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
+# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
+vld40.16 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
+# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
+vld40.16 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
+# CHECK-NOFP: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
+vld40.16 {q0, q1, q2, q3}, [r11]
+
+# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
+# CHECK-NOFP: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
+vld40.16 {q3, q4, q5, q6}, [r0]!
+
+# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
+# CHECK-NOFP: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
+vld41.16 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
+# CHECK-NOFP: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
+vld41.16 {q4, q5, q6, q7}, [r0]!
+
+# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
+# CHECK-NOFP: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
+vld42.16 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
+# CHECK-NOFP: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
+vld42.16 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
+# CHECK-NOFP: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
+vld43.16 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
+# CHECK-NOFP: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
+vld43.16 {q4, q5, q6, q7}, [r0]!
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
+# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
+vld40.32 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
+# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
+vld40.32 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
+# CHECK-NOFP: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
+vld40.32 {q0, q1, q2, q3}, [r11]
+
+# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
+# CHECK-NOFP: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
+vld40.32 {q3, q4, q5, q6}, [r0]!
+
+# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
+# CHECK-NOFP: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
+vld41.32 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
+# CHECK-NOFP: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
+vld41.32 {q4, q5, q6, q7}, [r0]!
+
+# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
+# CHECK-NOFP: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
+vld42.32 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
+# CHECK-NOFP: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
+vld42.32 {q0, q1, q2, q3}, [r0]!
+
+# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
+# CHECK-NOFP: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
+vld43.32 {q0, q1, q2, q3}, [r0]
+
+# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
+# CHECK-NOFP: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
+vld43.32 {q4, q5, q6, q7}, [r0]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.64 {q0, q1, q2, q3}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
+vld40.32 {q0, q2, q3, q4}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.32 {q0, q1, q2, q3, q4}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.32 {q0, q1}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.32 {q0, q1, q2}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vld40.32 q0, q1, q2, q3, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
+vld40.32 {q5, q6, q7, q8}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
+vld40.32 {d0, d1, d2, d3}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vld44.32 {q0, q1, q2, q3}, [r0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.32 {q0, q1, q2, q3}, [pc]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vld40.32 {q0, q1, q2, q3}, [r0, #4]
+
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+vldrb.u8 q0, [r0]
+
+# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]
+# CHECK-NOFP: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]
+vldrb.u8 q1, [r0]
+
+# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]
+vldrb.u8 q0, [r11]
+
+# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]
+# CHECK-NOFP: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]
+vldrb.u8 q3, [r11]
+
+# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]
+vldrb.u8 q0, [r4, #56]
+
+# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]
+# CHECK-NOFP: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]
+vldrb.u8 q4, [r4, #56]
+
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+vldrb.u8 q0, [r8, #56]
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+vldrb.u8 q5, [r4, #56]!
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+vldrb.u8 q5, [r4, #56]!
+
+# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]
+vldrb.u8 q5, [r4], #-25
+
+# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]
+vldrb.u8 q5, [r10], #-25
+
+# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]
+vldrb.u8 q5, [sp, #-25]
+
+# CHECK: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe]
+vldrb.u8 q5, [sp, #-127]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrb.u8 q0, [r0, #128]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrb.u8 q0, [r0, #-128]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrb.u8 q0, [r0], #128
+
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+vstrb.8 q0, [r0]
+
+# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]
+# CHECK-NOFP: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]
+vstrb.8 q1, [r0]
+
+# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]
+vstrb.8 q0, [r11]
+
+# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]
+# CHECK-NOFP: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]
+vstrb.8 q3, [r11]
+
+# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]
+vstrb.8 q0, [r4, #56]
+
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+vstrb.8 q4, [r4, #56]
+
+# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]
+vstrb.8 q0, [r8, #56]
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+vstrb.8 q5, [r4, #56]!
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+vstrb.8 q5, [r4, #56]!
+
+# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]
+vstrb.8 q5, [r4], #-25
+
+# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]
+vstrb.8 q5, [r10], #-25
+
+# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]
+vstrb.8 q5, [sp, #-25]
+
+# CHECK: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe]
+vstrb.8 q5, [sp, #127]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrb.u8 q0, [r0, #128]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrb.u8 q0, [r0, #-128]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrb.u8 q0, [r0], #128
+
+# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]
+# CHECK-NOFP: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]
+vldrb.u16 q0, [r0]
+
+# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]
+# CHECK-NOFP: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]
+vldrb.u16 q1, [r0]
+
+# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]
+# CHECK-NOFP: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]
+vldrb.u16 q0, [r7]
+
+# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]
+# CHECK-NOFP: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]
+vldrb.u16 q3, [r7]
+
+# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]
+# CHECK-NOFP: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]
+vldrb.u16 q0, [r4, #56]
+
+# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]
+# CHECK-NOFP: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]
+vldrb.u16 q4, [r4, #56]
+
+# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]
+# CHECK-NOFP: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]
+vldrb.u16 q0, [r2, #56]
+
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+vldrb.u16 q5, [r4, #56]!
+
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+vldrb.u16 q5, [r4, #56]!
+
+# CHECK: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae]
+vldrb.u16 q5, [r4], #-1
+
+# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]
+vldrb.u16 q5, [r3], #-25
+
+# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]
+vldrb.u16 q5, [r6, #-25]
+
+# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]
+# CHECK-NOFP: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]
+vldrb.u16 q5, [r6, #-64]
+
+# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]
+# CHECK-NOFP: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]
+vldrb.s16 q0, [r0]
+
+# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]
+# CHECK-NOFP: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]
+vldrb.s16 q1, [r0]
+
+# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]
+# CHECK-NOFP: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]
+vldrb.s16 q0, [r7]
+
+# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]
+# CHECK-NOFP: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]
+vldrb.s16 q3, [r7]
+
+# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]
+# CHECK-NOFP: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]
+vldrb.s16 q0, [r4, #56]
+
+# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]
+# CHECK-NOFP: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]
+vldrb.s16 q4, [r4, #56]
+
+# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]
+# CHECK-NOFP: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]
+vldrb.s16 q0, [r2, #56]
+
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+vldrb.s16 q5, [r4, #56]!
+
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+vldrb.s16 q5, [r4, #56]!
+
+# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]
+vldrb.s16 q5, [r4], #-25
+
+# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]
+vldrb.s16 q5, [r3], #-25
+
+# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]
+vldrb.s16 q5, [r6, #-25]
+
+# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]
+# CHECK-NOFP: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]
+vldrb.s16 q5, [r6, #-64]
+
+# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]
+# CHECK-NOFP: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]
+vstrb.16 q0, [r0]
+
+# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]
+# CHECK-NOFP: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]
+vstrb.16 q1, [r0]
+
+# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]
+# CHECK-NOFP: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]
+vstrb.16 q0, [r7]
+
+# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]
+# CHECK-NOFP: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]
+vstrb.16 q3, [r7]
+
+# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]
+# CHECK-NOFP: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]
+vstrb.16 q0, [r4, #56]
+
+# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]
+# CHECK-NOFP: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]
+vstrb.16 q4, [r4, #56]
+
+# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]
+# CHECK-NOFP: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]
+vstrb.16 q0, [r5, #56]
+
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+vstrb.16 q5, [r4, #56]!
+
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+vstrb.16 q5, [r4, #56]!
+
+# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]
+vstrb.16 q5, [r4], #-25
+
+# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]
+vstrb.16 q5, [r3], #-25
+
+# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]
+vstrb.16 q5, [r2, #-25]
+
+# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]
+# CHECK-NOFP: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]
+vstrb.16 q5, [r2, #-64]
+
+# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
+# CHECK-NOFP: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
+vldrb.u32 q0, [r0]
+
+# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]
+# CHECK-NOFP: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]
+vldrb.u32 q1, [r0]
+
+# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]
+# CHECK-NOFP: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]
+vldrb.u32 q0, [r7]
+
+# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]
+# CHECK-NOFP: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]
+vldrb.u32 q3, [r7]
+
+# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]
+# CHECK-NOFP: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]
+vldrb.u32 q0, [r4, #56]
+
+# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]
+# CHECK-NOFP: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]
+vldrb.u32 q4, [r4, #56]
+
+# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]
+# CHECK-NOFP: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]
+vldrb.u32 q0, [r2, #56]
+
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+vldrb.u32 q5, [r4, #56]!
+
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+vldrb.u32 q5, [r4, #56]!
+
+# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]
+vldrb.u32 q5, [r4], #-25
+
+# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]
+vldrb.u32 q5, [r3], #-25
+
+# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]
+vldrb.u32 q5, [r6, #-25]
+
+# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]
+# CHECK-NOFP: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]
+vldrb.u32 q5, [r6, #-64]
+
+# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]
+# CHECK-NOFP: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]
+vldrb.s32 q0, [r0]
+
+# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]
+# CHECK-NOFP: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]
+vldrb.s32 q1, [r0]
+
+# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]
+# CHECK-NOFP: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]
+vldrb.s32 q0, [r7]
+
+# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]
+# CHECK-NOFP: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]
+vldrb.s32 q3, [r7]
+
+# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]
+# CHECK-NOFP: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]
+vldrb.s32 q0, [r4, #56]
+
+# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]
+# CHECK-NOFP: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]
+vldrb.s32 q4, [r4, #56]
+
+# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]
+# CHECK-NOFP: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]
+vldrb.s32 q0, [r2, #56]
+
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+vldrb.s32 q5, [r4, #56]!
+
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+vldrb.s32 q5, [r4, #56]!
+
+# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]
+vldrb.s32 q5, [r4], #-25
+
+# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]
+vldrb.s32 q5, [r3], #-25
+
+# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]
+vldrb.s32 q5, [r6, #-25]
+
+# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]
+# CHECK-NOFP: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]
+vldrb.s32 q5, [r6, #-64]
+
+# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]
+# CHECK-NOFP: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]
+vstrb.32 q0, [r0]
+
+# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]
+# CHECK-NOFP: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]
+vstrb.32 q1, [r0]
+
+# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]
+# CHECK-NOFP: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]
+vstrb.32 q0, [r7]
+
+# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]
+# CHECK-NOFP: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]
+vstrb.32 q3, [r7]
+
+# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]
+# CHECK-NOFP: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]
+vstrb.32 q0, [r4, #56]
+
+# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]
+# CHECK-NOFP: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]
+vstrb.32 q4, [r4, #56]
+
+# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]
+# CHECK-NOFP: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]
+vstrb.32 q0, [r5, #56]
+
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+vstrb.32 q5, [r4, #56]!
+
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+vstrb.32 q5, [r4, #56]!
+
+# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]
+vstrb.32 q5, [r4], #-25
+
+# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]
+vstrb.32 q5, [r3], #-25
+
+# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]
+vstrb.32 q5, [r2, #-25]
+
+# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]
+# CHECK-NOFP: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]
+vstrb.32 q5, [r2, #-64]
+
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+vldrh.u16 q0, [r0]
+
+# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]
+# CHECK-NOFP: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]
+vldrh.u16 q1, [r0]
+
+# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]
+vldrh.u16 q0, [r11]
+
+# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]
+# CHECK-NOFP: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]
+vldrh.u16 q3, [r11]
+
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+vldrh.u16 q0, [r4, #56]
+
+# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]
+# CHECK-NOFP: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]
+vldrh.u16 q4, [r4, #56]
+
+# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]
+vldrh.u16 q0, [r8, #56]
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+vldrh.u16 q5, [r4, #56]!
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+vldrh.u16 q5, [r4, #56]!
+
+# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]
+vldrh.u16 q5, [r4], #-26
+
+# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]
+vldrh.u16 q5, [r10], #-26
+
+# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]
+vldrh.u16 q5, [sp, #-26]
+
+# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]
+vldrh.u16 q5, [sp, #-64]
+
+# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]
+vldrh.u16 q5, [sp, #-254]
+
+# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]
+vldrh.u16 q5, [r10], #254
+
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+vstrh.16 q0, [r0]
+
+# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]
+# CHECK-NOFP: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]
+vstrh.16 q1, [r0]
+
+# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]
+vstrh.16 q0, [r11]
+
+# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]
+# CHECK-NOFP: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]
+vstrh.16 q3, [r11]
+
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+vstrh.16 q0, [r4, #56]
+
+# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]
+# CHECK-NOFP: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]
+vstrh.16 q4, [r4, #56]
+
+# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]
+vstrh.16 q0, [r8, #56]
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+vstrh.16 q5, [r4, #56]!
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+vstrh.16 q5, [r4, #56]!
+
+# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]
+vstrh.16 q5, [r4], #-26
+
+# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]
+vstrh.16 q5, [r10], #-26
+
+# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]
+vstrh.16 q5, [sp, #-26]
+
+# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]
+vstrh.16 q5, [sp, #-64]
+
+# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]
+vstrh.16 q5, [sp, #-254]
+
+# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]
+vstrh.16 q5, [r10], #254
+
+# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]
+# CHECK-NOFP: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]
+vldrh.u32 q0, [r0]
+
+# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]
+# CHECK-NOFP: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]
+vldrh.u32 q1, [r0]
+
+# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]
+# CHECK-NOFP: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]
+vldrh.u32 q0, [r7]
+
+# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]
+# CHECK-NOFP: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]
+vldrh.u32 q3, [r7]
+
+# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]
+# CHECK-NOFP: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]
+vldrh.u32 q0, [r4, #56]
+
+# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]
+# CHECK-NOFP: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]
+vldrh.u32 q4, [r4, #56]
+
+# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]
+# CHECK-NOFP: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]
+vldrh.u32 q0, [r2, #56]
+
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+vldrh.u32 q5, [r4, #56]!
+
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+vldrh.u32 q5, [r4, #56]!
+
+# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]
+vldrh.u32 q5, [r4], #-26
+
+# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]
+vldrh.u32 q5, [r3], #-26
+
+# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]
+vldrh.u32 q5, [r6, #-26]
+
+# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]
+vldrh.u32 q5, [r6, #-64]
+
+# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]
+vldrh.u32 q5, [r6, #-254]
+
+# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]
+# CHECK-NOFP: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]
+vldrh.u32 q5, [r4, #254]!
+
+# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]
+# CHECK-NOFP: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]
+vldrh.s32 q0, [r0]
+
+# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]
+# CHECK-NOFP: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]
+vldrh.s32 q1, [r0]
+
+# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]
+# CHECK-NOFP: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]
+vldrh.s32 q0, [r7]
+
+# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]
+# CHECK-NOFP: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]
+vldrh.s32 q3, [r7]
+
+# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]
+# CHECK-NOFP: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]
+vldrh.s32 q0, [r4, #56]
+
+# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]
+# CHECK-NOFP: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]
+vldrh.s32 q4, [r4, #56]
+
+# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]
+# CHECK-NOFP: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]
+vldrh.s32 q0, [r2, #56]
+
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+vldrh.s32 q5, [r4, #56]!
+
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+vldrh.s32 q5, [r4, #56]!
+
+# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]
+vldrh.s32 q5, [r4], #-26
+
+# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]
+vldrh.s32 q5, [r3], #-26
+
+# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]
+vldrh.s32 q5, [r6, #-26]
+
+# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]
+vldrh.s32 q5, [r6, #-64]
+
+# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]
+vldrh.s32 q5, [r6, #-254]
+
+# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]
+# CHECK-NOFP: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]
+vldrh.s32 q5, [r4, #254]!
+
+# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]
+# CHECK-NOFP: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]
+vstrh.32 q0, [r0]
+
+# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]
+# CHECK-NOFP: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]
+vstrh.32 q1, [r0]
+
+# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]
+# CHECK-NOFP: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]
+vstrh.32 q0, [r7]
+
+# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]
+# CHECK-NOFP: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]
+vstrh.32 q3, [r7]
+
+# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]
+# CHECK-NOFP: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]
+vstrh.32 q0, [r4, #56]
+
+# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]
+# CHECK-NOFP: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]
+vstrh.32 q4, [r4, #56]
+
+# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]
+# CHECK-NOFP: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]
+vstrh.32 q0, [r5, #56]
+
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+vstrh.32 q5, [r4, #56]!
+
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+vstrh.32 q5, [r4, #56]!
+
+# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]
+vstrh.32 q5, [r4], #-26
+
+# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]
+vstrh.32 q5, [r3], #-26
+
+# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]
+vstrh.32 q5, [r2, #-26]
+
+# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]
+vstrh.32 q5, [r2, #-64]
+
+# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]
+vstrh.32 q5, [r2, #-254]
+
+# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]
+# CHECK-NOFP: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]
+vstrh.32 q5, [r4, #254]!
+
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+vldrw.u32 q0, [r0]
+
+# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]
+# CHECK-NOFP: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]
+vldrw.u32 q1, [r0]
+
+# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]
+vldrw.u32 q0, [r11]
+
+# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]
+# CHECK-NOFP: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]
+vldrw.u32 q3, [r11]
+
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+vldrw.u32 q0, [r4, #56]
+
+# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]
+# CHECK-NOFP: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]
+vldrw.u32 q4, [r4, #56]
+
+# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]
+vldrw.u32 q0, [r8, #56]
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+vldrw.u32 q5, [r4, #56]!
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+vldrw.u32 q5, [r4, #56]!
+
+# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]
+vldrw.u32 q5, [r4], #-28
+
+# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]
+vldrw.u32 q5, [r10], #-28
+
+# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]
+vldrw.u32 q5, [sp, #-28]
+
+# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]
+vldrw.u32 q5, [sp, #-64]
+
+# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]
+vldrw.u32 q5, [sp, #-508]
+
+# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]
+vldrw.u32 q5, [r4, #508]!
+
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+vstrw.32 q0, [r0]
+
+# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]
+# CHECK-NOFP: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]
+vstrw.32 q1, [r0]
+
+# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]
+vstrw.32 q0, [r11]
+
+# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]
+# CHECK-NOFP: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]
+vstrw.32 q3, [r11]
+
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+vstrw.32 q0, [r4, #56]
+
+# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]
+# CHECK-NOFP: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]
+vstrw.32 q4, [r4, #56]
+
+# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]
+vstrw.32 q0, [r8, #56]
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+vstrw.32 q5, [r4, #56]!
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+vstrw.32 q5, [r4, #56]!
+
+# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]
+vstrw.32 q5, [r4], #-28
+
+# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]
+vstrw.32 q5, [r10], #-28
+
+# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]
+vstrw.32 q5, [sp, #-28]
+
+# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]
+vstrw.32 q5, [sp, #-64]
+
+# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]
+vstrw.32 q5, [sp, #-508]
+
+# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]
+vstrw.32 q5, [r4, #508]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrb.16 q0, [r8]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrh.u32 q0, [r8]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrw.32 q5, [sp, #-64]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrw.32 q5, [sp, #-3]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrw.32 q5, [sp, #512]
+
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+vldrb.u8 q0, [r0, q1]
+
+# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]
+# CHECK-NOFP: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]
+vldrb.u8 q3, [r10, q1]
+
+# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]
+# CHECK-NOFP: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]
+vldrb.u16 q0, [r0, q1]
+
+# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]
+# CHECK-NOFP: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]
+vldrb.u16 q3, [r9, q1]
+
+# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]
+# CHECK-NOFP: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]
+vldrb.s16 q0, [r0, q1]
+
+# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]
+# CHECK-NOFP: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]
+vldrb.s16 q3, [sp, q1]
+
+# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]
+# CHECK-NOFP: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]
+vldrb.u32 q0, [r0, q1]
+
+# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]
+# CHECK-NOFP: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]
+vldrb.u32 q3, [r0, q1]
+
+# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]
+# CHECK-NOFP: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]
+vldrb.s32 q0, [r0, q1]
+
+# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]
+# CHECK-NOFP: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]
+vldrb.s32 q3, [r0, q1]
+
+# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]
+# CHECK-NOFP: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]
+vldrh.u16 q0, [r0, q1]
+
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+vldrh.u16 q3, [r0, q1]
+
+# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]
+# CHECK-NOFP: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]
+vldrh.u32 q0, [r0, q1]
+
+# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]
+# CHECK-NOFP: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]
+vldrh.u32 q3, [r0, q1]
+
+# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]
+# CHECK-NOFP: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]
+vldrh.s32 q0, [r0, q1]
+
+# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]
+# CHECK-NOFP: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]
+vldrh.s32 q3, [r0, q1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrb.u8 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrb.u16 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrb.s16 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrb.u32 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrb.s32 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.u16 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.u32 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.s32 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.u16 q0, [r0, q0, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.u32 q0, [r0, q0, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrh.s32 q0, [r0, q0, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrw.u32 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrw.u32 q0, [r0, q0, uxtw #2]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrd.u64 q0, [r0, q0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
+vldrd.u64 q0, [r0, q0, uxtw #3]
+
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+vldrh.u16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+vldrw.u32 q0, [r0, q1]
+
+# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]
+# CHECK-NOFP: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]
+vldrw.u32 q3, [r0, q1]
+
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+vldrw.u32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]
+vldrw.u32 q0, [sp, q1, uxtw #2]
+
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+vldrd.u64 q0, [r0, q1]
+
+# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]
+# CHECK-NOFP: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]
+vldrd.u64 q3, [r0, q1]
+
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+vldrd.u64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]
+vldrd.u64 q0, [sp, q1, uxtw #3]
+
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+vstrb.8 q0, [r0, q1]
+
+# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]
+# CHECK-NOFP: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]
+vstrb.8 q3, [r10, q1]
+
+# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]
+# CHECK-NOFP: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]
+vstrb.8 q3, [r0, q3]
+
+# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]
+# CHECK-NOFP: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]
+vstrb.16 q0, [r0, q1]
+
+# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]
+# CHECK-NOFP: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]
+vstrb.16 q3, [sp, q1]
+
+# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]
+# CHECK-NOFP: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]
+vstrb.16 q3, [r0, q3]
+
+# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]
+# CHECK-NOFP: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]
+vstrb.32 q0, [r0, q1]
+
+# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]
+# CHECK-NOFP: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]
+vstrb.32 q3, [r0, q1]
+
+# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]
+# CHECK-NOFP: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]
+vstrb.32 q3, [r0, q3]
+
+# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]
+# CHECK-NOFP: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]
+vstrh.16 q0, [r0, q1]
+
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+vstrh.16 q3, [r0, q1]
+
+# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]
+# CHECK-NOFP: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]
+vstrh.16 q3, [r0, q3]
+
+# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]
+# CHECK-NOFP: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]
+vstrh.32 q0, [r0, q1]
+
+# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]
+# CHECK-NOFP: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]
+vstrh.32 q3, [r0, q1]
+
+# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]
+# CHECK-NOFP: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]
+vstrh.32 q3, [r0, q3]
+
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+vstrh.16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]
+# CHECK-NOFP: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]
+vstrh.32 q3, [r8, q3, uxtw #1]
+
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+vstrw.32 q0, [r0, q1]
+
+# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]
+# CHECK-NOFP: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]
+vstrw.32 q3, [r0, q1]
+
+# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]
+# CHECK-NOFP: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]
+vstrw.32 q3, [r0, q3]
+
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+vstrw.32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]
+vstrw.32 q0, [sp, q1, uxtw #2]
+
+# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]
+vstrd.64 q0, [r0, q1]
+
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+vstrd.64 q3, [r0, q1]
+
+# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]
+# CHECK-NOFP: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]
+vstrd.64 q3, [r0, q3]
+
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+vstrd.64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]
+vstrd.64 q0, [sp, q1, uxtw #3]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
+vstrw.32 q9, [sp, q1, uxtw #2]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrh.16 q3, [pc, q1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrd.64 q0, [r0, q1, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrd.u64 q0, [r0, q1, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrd.64 q0, [r0, q1, uxtw #2]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrd.u64 q0, [r0, q1, uxtw #2]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrw.u32 q0, [r0, q1, uxtw #1]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrh.16 q0, [r0, q1, uxtw #2]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrb.32 q0, [r11, q1, uxtw #1]
+
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+vldrw.u32 q0, [q1]
+
+# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]
+vldrw.u32 q7, [q1]
+
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+vldrw.u32 q7, [q1]!
+
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+vldrw.u32 q7, [q1, #4]
+
+# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]
+vldrw.u32 q7, [q1, #-4]
+
+# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]
+vldrw.u32 q7, [q1, #508]
+
+# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]
+vldrw.u32 q7, [q1, #-508]
+
+# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]
+vldrw.u32 q7, [q1, #264]
+
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+vldrw.u32 q7, [q1, #4]!
+
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+vstrw.32 q0, [q1]
+
+# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]
+vstrw.32 q7, [q1]
+
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+vstrw.32 q7, [q1]!
+
+# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]
+vstrw.32 q7, [q7]
+
+# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]
+vstrw.32 q7, [q1, #4]
+
+# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]
+vstrw.32 q7, [q1, #-4]
+
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+vstrw.32 q7, [q1, #508]
+
+# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]
+vstrw.32 q7, [q1, #-508]
+
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+vstrw.32 q7, [q1, #264]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
+vstrw.32 q8, [q1]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrw.32 q4, [q1, #3]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vldrw.u32 q7, [q1, #512]
+
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+vldrd.u64 q0, [q1]
+
+# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]
+vldrd.u64 q7, [q1]
+
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+vldrd.u64 q7, [q1]!
+
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+vldrd.u64 q7, [q1, #8]
+
+# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]
+vldrd.u64 q7, [q1, #-8]
+
+# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]
+vldrd.u64 q7, [q1, #1016]
+
+# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]
+vldrd.u64 q7, [q1, #-1016]
+
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+vldrd.u64 q7, [q1, #264]
+
+# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]
+vldrd.u64 q7, [q1, #624]
+
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+vldrd.u64 q7, [q1, #264]
+
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+vldrd.u64 q7, [q1, #-1016]!
+
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+vstrd.64 q0, [q1]
+
+# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]
+vstrd.64 q7, [q1]
+
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+vstrd.64 q7, [q1]!
+
+# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]
+vstrd.64 q7, [q7]
+
+# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]
+vstrd.64 q7, [q1, #8]
+
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+vstrd.64 q7, [q1, #-8]!
+
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+vstrd.64 q7, [q1, #1016]
+
+# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]
+vstrd.64 q7, [q1, #-1016]
+
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+vstrd.64 q7, [q1, #264]
+
+# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]
+vstrd.64 q7, [q1, #624]
+
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+vstrd.64 q7, [q1, #264]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
+vldrd.u64 q8, [q1]!
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrd.64 q7, [q1, #1024]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrd.64 q4, [q1, #3]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vstrd.64 q4, [q1, #4]
+
+# CHECK: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+# CHECK-NOFP: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+wlstp.8     lr, r0, #1668
+
+# CHECK: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+# CHECK-NOFP: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+wlstp.16     lr, r0, #1668
+
+# CHECK: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+# CHECK-NOFP: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+wlstp.32     lr, r4, #2706
+
+# CHECK: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# CHECK-NOFP: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+wlstp.64     lr, lr, #3026
+
+# CHECK: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+# CHECK-NOFP: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+wlstp.8     lr, r5, #3436
+
+# CHECK: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+# CHECK-NOFP: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+wlstp.16     lr, r1, #1060
+
+# CHECK: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+# CHECK-NOFP: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+wlstp.32     lr, r7, #4036
+
+# CHECK: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+# CHECK-NOFP: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+wlstp.8     lr, r1, #538
+
+# CHECK: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# CHECK-NOFP: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+wlstp.8     lr, r10, #1404
+
+# CHECK: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# CHECK-NOFP: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+wlstp.8     lr, r10, #1408
+
+# CHECK: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# CHECK-NOFP: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+wlstp.8     lr, r10, #2358
+
+# CHECK: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# CHECK-NOFP: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+wlstp.8     lr, r10, #4086
+
+# CHECK: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+# CHECK-NOFP: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+wlstp.8     lr, r11, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+wlstp.8     lr, r10, #1443
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+wlstp.8     lr, r10, #4096
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+wlstp.8     lr, sp, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+wlstp.16     lr, sp, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+wlstp.32     r10, r11, #1442
+
+# CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+dlstp.8     lr, r5
+
+# CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+dlstp.16     lr, r5
+
+# CHECK: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+dlstp.32     lr, r7
+
+# CHECK: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+dlstp.64     lr, r2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+dlstp.64     lr, sp
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+dlstp.64     r10, r0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+dlstp.64     lr, pc
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# CHECK-NOFP: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+letp lr, #-2
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# CHECK-NOFP: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+letp lr, #-8
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# CHECK-NOFP: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+letp lr, #-4094
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+letp r0, #-8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+letp lr, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+letp lr, #-4096
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOFP: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+lctp
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOFP: it eq @ encoding: [0x08,0xbf]
+it eq
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOFP: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+lctpeq
+
+# CHECK: vqdmullb.s16 q0, q1, q0  @ encoding: [0x32,0xee,0x01,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, q0  @ encoding: [0x32,0xee,0x01,0x0f]
+vqdmullb.s16 q0, q1, q0
+
+# CHECK: vqdmullt.s16 q0, q0, q5  @ encoding: [0x30,0xee,0x0b,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q0, q5  @ encoding: [0x30,0xee,0x0b,0x1f]
+vqdmullt.s16 q0, q0, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
+vqdmullb.s32 q0, q1, q0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
+vqdmullt.s32 q0, q0, q5
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOFP: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+vsub.i8 q0, q3, r3
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOFP: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+vsub.i16 q0, q7, lr
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOFP: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+vsub.i32 q1, q5, r10
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOFP: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+vadd.i8 q1, q4, r7
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOFP: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+vadd.i16 q0, q6, r11
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOFP: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+vadd.i32 q0, q1, r6
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOFP: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+vqsub.s8 q2, q2, r8
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOFP: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+vqsub.s16 q1, q4, r0
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOFP: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+vqsub.s32 q0, q2, r0
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+vqsub.u8 q0, q1, r2
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOFP: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+vqsub.u16 q0, q2, r6
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+vqsub.u32 q0, q2, r2
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOFP: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+vqadd.s8 q0, q6, r1
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOFP: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+vqadd.s16 q3, q4, r2
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOFP: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+vqadd.s32 q0, q5, r11
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOFP: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+vqadd.u8 q0, q1, r8
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOFP: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+vqadd.u16 q0, q5, r9
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOFP: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+vqadd.u32 q0, q0, r7
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+vqdmullb.s16 q0, q1, r6
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+vqdmullt.s16 q0, q1, r0
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+vqdmullt.s32 q0, q4, r5
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOFP-NOT: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+vsub.f16 q0, q3, r7
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOFP-NOT: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+vsub.f32 q1, q1, r10
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOFP-NOT: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+vadd.f16 q0, q1, lr
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOFP-NOT: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+vadd.f32 q1, q4, r4
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOFP: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+vhsub.s8 q0, q3, lr
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOFP: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+vhsub.s16 q0, q0, r6
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOFP: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+vhsub.s32 q1, q2, r7
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOFP: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+vhsub.u8 q1, q6, r5
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOFP: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+vhsub.u16 q0, q4, r10
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOFP: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+vhsub.u32 q0, q4, r12
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+vhadd.s8 q0, q2, r1
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+vhadd.s16 q0, q2, r1
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOFP: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+vhadd.s32 q0, q0, r10
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOFP: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+vhadd.u8 q0, q5, lr
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOFP: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+vhadd.u16 q1, q2, r2
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOFP: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+vhadd.u32 q0, q2, r11
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+vqrshl.s8 q0, r0
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+vqrshl.s16 q0, r3
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOFP: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+vqrshl.s32 q0, lr
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+vqrshl.u8 q0, r0
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOFP: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+vqrshl.u16 q0, r2
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+vqrshl.u32 q0, r3
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+vqshl.s8 q0, r0
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOFP: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+vqshl.s16 q1, r1
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+vqshl.s32 q0, r3
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOFP: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+vqshl.u8 q0, r1
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOFP: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+vqshl.u16 q0, r11
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOFP: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+vqshl.u32 q0, lr
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOFP: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+vrshl.s8 q0, r6
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOFP: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+vrshl.s16 q0, lr
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOFP: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+vrshl.s32 q0, r4
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOFP: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+vrshl.u8 q0, r0
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+vrshl.u16 q0, r10
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOFP: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+vrshl.u32 q0, r1
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+vshl.s8 q0, lr
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+vshl.s16 q0, lr
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOFP: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+vshl.s32 q0, r1
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+vshl.u8 q0, r10
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOFP: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+vshl.u16 q1, r10
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOFP: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+vshl.u32 q0, r12
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOFP: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+vbrsr.8 q0, q4, r8
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOFP: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+vbrsr.16 q0, q1, r1
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOFP: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+vbrsr.32 q0, q6, r0
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOFP: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+vmul.i8 q0, q0, r12
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOFP: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+vmul.i16 q0, q4, r7
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOFP: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+vmul.i32 q0, q1, r11
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOFP-NOT: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+vmul.f16 q0, q0, r10
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOFP-NOT: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+vmul.f32 q0, q1, r7
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOFP: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+vqdmulh.s8 q0, q1, r6
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOFP: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+vqdmulh.s16 q0, q2, r2
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOFP: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+vqdmulh.s32 q1, q3, r8
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOFP: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+vqrdmulh.s8 q0, q2, r6
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+vqrdmulh.s16 q0, q0, r2
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+vqrdmulh.s32 q0, q0, r2
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOFP-NOT: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+vfmas.f16 q0, q0, r12
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOFP-NOT: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+vfmas.f32 q0, q3, lr
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+vmlas.s8 q0, q0, r6
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOFP: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+vmlas.s16 q0, q2, r9
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+vmlas.s32 q0, q7, r6
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOFP: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+vmlas.u8 q0, q5, lr
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+vmlas.u16 q0, q3, r12
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOFP: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+vmlas.u32 q1, q1, r11
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOFP-NOT: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+vfma.f16 q1, q1, r6
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOFP-NOT: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+vfmas.f32 q7, q4, r6
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOFP: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+vmla.s8 q0, q3, r8
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+vmla.s16 q1, q3, r10
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOFP: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+vmla.s32 q1, q3, r1
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOFP: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+vmla.u8 q0, q7, r10
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOFP: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+vmla.u16 q0, q0, r7
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOFP: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+vmla.u32 q1, q6, r10
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOFP: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+vqdmlash.s8 q0, q0, r5
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOFP: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+vqdmlash.s16 q0, q5, lr
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOFP: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+vqdmlash.s32 q0, q2, r3
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOFP: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+vqdmlash.u8 q0, q4, r2
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOFP: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+vqdmlash.u16 q1, q4, r2
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOFP: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+vqdmlash.u32 q1, q5, r0
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOFP: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+vqdmlah.s8 q0, q3, r3
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOFP: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+vqdmlah.s16 q5, q3, r9
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOFP: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+vqdmlah.s32 q0, q1, r11
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOFP: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+vqdmlah.u8 q0, q2, lr
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOFP: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+vqdmlah.u16 q0, q3, r10
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOFP: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+vqdmlah.u32 q1, q5, r2
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOFP: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+vqrdmlash.s8 q0, q5, r10
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOFP: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+vqrdmlash.s16 q0, q3, r2
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOFP: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+vqrdmlash.s32 q0, q0, r4
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOFP: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+vqrdmlash.u8 q0, q4, r9
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+vqrdmlash.u16 q0, q6, r12
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOFP: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+vqrdmlash.u32 q0, q3, r7
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+vqrdmlah.s8 q0, q5, r11
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOFP: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+vqrdmlah.s16 q0, q2, r10
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+vqrdmlah.s32 q0, q4, r11
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+vqrdmlah.u8 q0, q4, r2
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOFP: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+vqrdmlah.u16 q0, q6, r1
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+vqrdmlah.u32 q0, q4, r2
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOFP: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+viwdup.u8 q0, lr, r1, #1
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOFP: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+viwdup.u16 q1, r10, r1, #8
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOFP: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+viwdup.u32 q6, r10, r5, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+viwdup.u32 q6, r10, r5, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+viwdup.u32 q6, r3, r5, #4
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOFP: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+vdwdup.u8 q0, r12, r11, #8
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOFP: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+vdwdup.u16 q0, r12, r1, #2
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOFP: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+vdwdup.u32 q0, r0, r7, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vdwdup.u32 q0, r0, r7, #9
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOFP: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+vidup.u8 q0, lr, #2
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOFP: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+vidup.u16 q0, lr, #4
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOFP: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+vidup.u32 q0, r12, #1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vidup.u32 q0, r12, #3
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+vddup.u8 q0, r4, #4
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+vddup.u16 q0, r10, #4
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOFP: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+vddup.u32 q2, r0, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vddup.u32 q2, r0, #5
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+vctp.8 lr
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+vctp.16 r0
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+vctp.32 r10
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+vctp.64 r1
+
+# CHECK: vcmp.f16 eq, q4, r12  @ encoding: [0x39,0xfe,0x4c,0x0f]
+# CHECK-NOFP-NOT: vcmp.f16 eq, q4, r12  @ encoding: [0x39,0xfe,0x4c,0x0f]
+vcmp.f16 eq, q4, r12
+
+# CHECK: vcmp.f32 ne, q3, r0  @ encoding: [0x37,0xee,0xc0,0x0f]
+# CHECK-NOFP-NOT: vcmp.f32 ne, q3, r0  @ encoding: [0x37,0xee,0xc0,0x0f]
+vcmp.f32 ne, q3, r0
+
+# CHECK: vcmp.i8 eq, q1, r0  @ encoding: [0x03,0xfe,0x40,0x0f]
+# CHECK-NOFP: vcmp.i8 eq, q1, r0  @ encoding: [0x03,0xfe,0x40,0x0f]
+vcmp.i8 eq, q1, r0
+
+# CHECK: vcmp.s8 le, q1, r0  @ encoding: [0x03,0xfe,0xe0,0x1f]
+# CHECK-NOFP: vcmp.s8 le, q1, r0  @ encoding: [0x03,0xfe,0xe0,0x1f]
+vcmp.s8 le, q1, r0
+
+# CHECK: vcmp.u8 cs, q1, r0  @ encoding: [0x03,0xfe,0x60,0x0f]
+# CHECK-NOFP: vcmp.u8 cs, q1, r0  @ encoding: [0x03,0xfe,0x60,0x0f]
+vcmp.u8 cs, q1, r0
+
+# CHECK: vcmp.i16 eq, q5, r10  @ encoding: [0x1b,0xfe,0x4a,0x0f]
+# CHECK-NOFP: vcmp.i16 eq, q5, r10  @ encoding: [0x1b,0xfe,0x4a,0x0f]
+vcmp.i16 eq, q5, r10
+
+# CHECK: vcmp.i32 eq, q1, r4  @ encoding: [0x23,0xfe,0x44,0x0f]
+# CHECK-NOFP: vcmp.i32 eq, q1, r4  @ encoding: [0x23,0xfe,0x44,0x0f]
+vcmp.i32 eq, q1, r4
+
+# CHECK: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+# CHECK-NOFP: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+vpnot
+
+# CHECK: vmov.8 q0[1], r8  @ encoding: [0x40,0xee,0x30,0x8b]
+# CHECK-NOFP: vmov.8 q0[1], r8  @ encoding: [0x40,0xee,0x30,0x8b]
+vmov.8 q0[1], r8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.8 q0[16], r8
+
+# CHECK: vmov.16 q0[2], r5  @ encoding: [0x20,0xee,0x30,0x5b]
+# CHECK-NOFP: vmov.16 q0[2], r5  @ encoding: [0x20,0xee,0x30,0x5b]
+vmov.16 q0[2], r5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.16 q0[8], r5
+
+# CHECK: vmov.32 q6[3], r11  @ encoding: [0x2d,0xee,0x10,0xbb]
+# CHECK-NOFP: vmov.32 q6[3], r11  @ encoding: [0x2d,0xee,0x10,0xbb]
+vmov.32 q6[3], r11
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.32 q6[4], r11
+
+# CHECK: vmov.32 r0, q1[0]  @ encoding: [0x12,0xee,0x10,0x0b]
+# CHECK-NOFP: vmov.32 r0, q1[0]  @ encoding: [0x12,0xee,0x10,0x0b]
+vmov.32 r0, q1[0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.32 r0, q1[4]
+
+# CHECK: vmov.s16 r1, q2[7]  @ encoding: [0x35,0xee,0x70,0x1b]
+# CHECK-NOFP: vmov.s16 r1, q2[7]  @ encoding: [0x35,0xee,0x70,0x1b]
+vmov.s16 r1, q2[7]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.s16 r1, q2[8]
+
+# CHECK: vmov.s8 r0, q4[13]  @ encoding: [0x79,0xee,0x30,0x0b]
+# CHECK-NOFP: vmov.s8 r0, q4[13]  @ encoding: [0x79,0xee,0x30,0x0b]
+vmov.s8 r0, q4[13]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.s8 r0, q4[16]
+
+# CHECK: vmov.u16 r0, q1[4]  @ encoding: [0x93,0xee,0x30,0x0b]
+# CHECK-NOFP: vmov.u16 r0, q1[4]  @ encoding: [0x93,0xee,0x30,0x0b]
+vmov.u16 r0, q1[4]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.u16 r0, q1[8]
+
+# CHECK: vmov.u8 r0, q5[7]  @ encoding: [0xfa,0xee,0x70,0x0b]
+# CHECK-NOFP: vmov.u8 r0, q5[7]  @ encoding: [0xfa,0xee,0x70,0x0b]
+vmov.u8 r0, q5[7]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmov.u8 r0, q5[16]
+
+# CHECK: vmov    lr, r7, q4[2], q4[0]  @ encoding: [0x07,0xec,0x0e,0x8f]
+# CHECK-NOFP: vmov    lr, r7, q4[2], q4[0]  @ encoding: [0x07,0xec,0x0e,0x8f]
+vmov    lr, r7, q4[2], q4[0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Q-registers must be the same
+vmov    lr, r7, q5[2], q4[0]
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Q-register indexes must be 2 and 0 or 3 and 1
+vmov    lr, r7, q4[2], q4[1]
+
+# CHECK: vmov    q3[3], q3[1], r4, r1  @ encoding: [0x11,0xec,0x14,0x6f]
+# CHECK-NOFP: vmov    q3[3], q3[1], r4, r1  @ encoding: [0x11,0xec,0x14,0x6f]
+vmov    q3[3], q3[1], r4, r1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Q-registers must be the same
+vmov    q4[3], q3[1], r4, r1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Q-register indexes must be 2 and 0 or 3 and 1
+vmov    q3[2], q3[1], r4, r1
+
+# CHECK: vmov.i32 q0, #0x1bff  @ encoding: [0x81,0xef,0x5b,0x0c]
+# CHECK-NOFP: vmov.i32 q0, #0x1bff  @ encoding: [0x81,0xef,0x5b,0x0c]
+vmov.i32 q0, #0x1bff
+
+# CHECK: vmov.i16 q0, #0x5c  @ encoding: [0x85,0xef,0x5c,0x08]
+# CHECK-NOFP: vmov.i16 q0, #0x5c  @ encoding: [0x85,0xef,0x5c,0x08]
+vmov.i16 q0, #0x5c
+
+# CHECK: vmov.i8 q0, #0x4c  @ encoding: [0x84,0xef,0x5c,0x0e]
+# CHECK-NOFP: vmov.i8 q0, #0x4c  @ encoding: [0x84,0xef,0x5c,0x0e]
+vmov.i8 q0, #0x4c
+
+# CHECK: vmov.f32 q0, #-3.625000e+00  @ encoding: [0x80,0xff,0x5d,0x0f]
+# CHECK-NOFP: vmov.f32 q0, #-3.625000e+00  @ encoding: [0x80,0xff,0x5d,0x0f]
+vmov.f32 q0, #-3.625000e+00
+
+# CHECK: vmov.f32 s16, s1  @ encoding: [0xb0,0xee,0x60,0x8a]
+# CHECK-NOFP: vmov.f32 s16, s1  @ encoding: [0xb0,0xee,0x60,0x8a]
+vmov.f32 s16, s1
+
+# CHECK: vmov.f64 d0, d1  @ encoding: [0xb0,0xee,0x41,0x0b]
+# CHECK-NOFP: vmov.f64 d0, d1  @ encoding: [0xb0,0xee,0x41,0x0b]
+vmov.f64 d0, d1
+
+# CHECK: vmov.i64 q0, #0xff0000ffffffffff  @ encoding: [0x81,0xff,0x7f,0x0e]
+# CHECK-NOFP: vmov.i64 q0, #0xff0000ffffffffff  @ encoding: [0x81,0xff,0x7f,0x0e]
+vmov.i64 q0, #0xff0000ffffffffff
+
+# CHECK: vorr.i16 q0, #0x12  @ encoding: [0x81,0xef,0x52,0x09]
+# CHECK-NOFP: vorr.i16 q0, #0x12  @ encoding: [0x81,0xef,0x52,0x09]
+vorr.i16 q0, #0x12
+
+# CHECK: vorr.i32 q0, #0x1200  @ encoding: [0x81,0xef,0x52,0x03]
+# CHECK-NOFP: vorr.i32 q0, #0x1200  @ encoding: [0x81,0xef,0x52,0x03]
+vorr.i32 q0, #0x1200
+
+# CHECK: vorr.i16 q0, #0xed  @ encoding: [0x86,0xff,0x5d,0x09]
+# CHECK-NOFP: vorr.i16 q0, #0xed  @ encoding: [0x86,0xff,0x5d,0x09]
+vorn.i16 q0, #0xff12
+
+# CHECK: vorr.i32 q0, #0xed00  @ encoding: [0x86,0xff,0x5d,0x03]
+# CHECK-NOFP: vorr.i32 q0, #0xed00  @ encoding: [0x86,0xff,0x5d,0x03]
+vorn.i32 q0, #0xffff12ff
+
+# CHECK: vorr.i32 q0, #0xed0000  @ encoding: [0x86,0xff,0x5d,0x05]
+# CHECK-NOFP: vorr.i32 q0, #0xed0000  @ encoding: [0x86,0xff,0x5d,0x05]
+vorn.i32 q0, #0xff12ffff
+
+# CHECK: vorr.i32 q0, #0xed000000  @ encoding: [0x86,0xff,0x5d,0x07]
+# CHECK-NOFP: vorr.i32 q0, #0xed000000  @ encoding: [0x86,0xff,0x5d,0x07]
+vorn.i32 q0, #0x12ffffff
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i16 q0, #0xed00
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i16 q0, #0x00ed
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i32 q0, #0xed000000
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i32 q0, #0x00ed0000
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i32 q0, #0x0000ed00
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vorn.i32 q0, #0x000000ed
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+# CHECK-NOFP: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+vrmlsldavh.s32 lr, r11, q6, q5
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOFP: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+vcvtb.f16.f32 q1, q4
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+vcvtt.f32.f16 q0, q1
+
+# CHECK: vcvt.f16.s16 q0, q1  @ encoding: [0xb7,0xff,0x42,0x06]
+# CHECK-NOFP-NOT: vcvt.f16.s16 q0, q1  @ encoding: [0xb7,0xff,0x42,0x06]
+vcvt.f16.s16 q0, q1
+
+# CHECK: vcvt.f16.u16 q0, q4  @ encoding: [0xb7,0xff,0xc8,0x06]
+# CHECK-NOFP-NOT: vcvt.f16.u16 q0, q4  @ encoding: [0xb7,0xff,0xc8,0x06]
+vcvt.f16.u16 q0, q4
+
+# CHECK: vcvt.s16.f16 q0, q0  @ encoding: [0xb7,0xff,0x40,0x07]
+# CHECK-NOFP-NOT: vcvt.s16.f16 q0, q0  @ encoding: [0xb7,0xff,0x40,0x07]
+vcvt.s16.f16 q0, q0
+
+# CHECK: vcvt.u16.f16 q0, q0  @ encoding: [0xb7,0xff,0xc0,0x07]
+# CHECK-NOFP-NOT: vcvt.u16.f16 q0, q0  @ encoding: [0xb7,0xff,0xc0,0x07]
+vcvt.u16.f16 q0, q0
+
+# CHECK: vcvt.f32.s32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x06]
+# CHECK-NOFP-NOT: vcvt.f32.s32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x06]
+vcvt.f32.s32 q0, q0
+
+# CHECK: vcvt.f32.u32 q0, q0  @ encoding: [0xbb,0xff,0xc0,0x06]
+# CHECK-NOFP-NOT: vcvt.f32.u32 q0, q0  @ encoding: [0xbb,0xff,0xc0,0x06]
+vcvt.f32.u32 q0, q0
+
+# CHECK: vcvt.s32.f32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x07]
+# CHECK-NOFP-NOT: vcvt.s32.f32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x07]
+vcvt.s32.f32 q0, q0
+
+# CHECK: vcvt.u32.f32 q0, q2  @ encoding: [0xbb,0xff,0xc4,0x07]
+# CHECK-NOFP-NOT: vcvt.u32.f32 q0, q2  @ encoding: [0xbb,0xff,0xc4,0x07]
+vcvt.u32.f32 q0, q2
+# CHECK: vbic.i16 q0, #0x22  @ encoding: [0x82,0xef,0x72,0x09]
+# CHECK-NOFP: vbic.i16 q0, #0x22  @ encoding: [0x82,0xef,0x72,0x09]
+vbic.i16 q0, #0x22
+
+# CHECK: vbic.i32 q0, #0x1100  @ encoding: [0x81,0xef,0x71,0x03]
+# CHECK-NOFP: vbic.i32 q0, #0x1100  @ encoding: [0x81,0xef,0x71,0x03]
+vbic.i32 q0, #0x1100
+
+# CHECK: vbic.i16 q0, #0xdd  @ encoding: [0x85,0xff,0x7d,0x09]
+# CHECK-NOFP: vbic.i16 q0, #0xdd  @ encoding: [0x85,0xff,0x7d,0x09]
+vand.i16 q0, #0xff22
+
+# CHECK: vbic.i16 q0, #0xdd00  @ encoding: [0x85,0xff,0x7d,0x0b]
+# CHECK-NOFP: vbic.i16 q0, #0xdd00  @ encoding: [0x85,0xff,0x7d,0x0b]
+vand.i16 q0, #0x22ff
+
+# CHECK: vbic.i32 q0, #0xee  @ encoding: [0x86,0xff,0x7e,0x01]
+# CHECK-NOFP: vbic.i32 q0, #0xee  @ encoding: [0x86,0xff,0x7e,0x01]
+vand.i32 q0, #0xffffff11
+
+# CHECK: vbic.i32 q0, #0xee00  @ encoding: [0x86,0xff,0x7e,0x03]
+# CHECK-NOFP: vbic.i32 q0, #0xee00  @ encoding: [0x86,0xff,0x7e,0x03]
+vand.i32 q0, #0xffff11ff
+
+# CHECK: vbic.i32 q0, #0xee0000  @ encoding: [0x86,0xff,0x7e,0x05]
+# CHECK-NOFP: vbic.i32 q0, #0xee0000  @ encoding: [0x86,0xff,0x7e,0x05]
+vand.i32 q0, #0xff11ffff
+
+# CHECK: vbic.i32 q0, #0xee000000  @ encoding: [0x86,0xff,0x7e,0x07]
+# CHECK-NOFP: vbic.i32 q0, #0xee000000  @ encoding: [0x86,0xff,0x7e,0x07]
+vand.i32 q0, #0x11ffffff
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i16 q0, #0xed00
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i16 q0, #0x00ed
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i32 q0, #0xed000000
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i32 q0, #0x00ed0000
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i32 q0, #0x0000ed00
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vand.i32 q0, #0x000000ed
+
+###############################################################################
+# The following tests were added to test mnemonic clashes with existing scalar
+# Floating Point instructions.
+###############################################################################
+
+# CHECK: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
+# CHECK-NOFP-NOT: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
+vrintr.f32.f32 s0, s1
+
+# CHECK: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
+# CHECK-NOFP-NOT: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
+vrintr.f64.f64 d0, d1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vrintr.f32.f32 q0, q1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+vrintr.f64 q0, q1
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+vcvtt.f64.f16 d0, s0
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOFP-NOT: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+vcvtt.f16.f64 s1, d2
+
+vcvtt.f16.f32 q1, q4
+# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
+
+vcvta.s32.f32 s2, s3
+# CHECK: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
+# CHECK-NOFP-NOT: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
+
+vcvta.s16.f16 q0, q7
+# CHECK: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
+# CHECK-NOFP-NOT: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
+
+vaddeq.f32 q0, q1, q2
+# ERROR: [[@LINE-1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
+
+vadd.f32 q0, q1, q2
+# CHECK:  vadd.f32  q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0d]
+# CHECK-NOFP-NOT:  vadd.f32  q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0d]
+
+vcmul.f16 q0, q1, q2, #90
+# CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+# CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
+
+vpste
+vmint.s8 q0, q1, q2
+vmine.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
+# CHECK-NOFP: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
+# CHECK: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOFP: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+
+vpste
+vmult.i8 q0, q1, q2
+vmule.i16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+
+vpste
+vmulltt.p8 q0, q1, q2
+vmullbe.p16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK-NOFP: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
+# CHECK: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+# CHECK-NOFP: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
+
+vpste
+vmvnt q0, q1
+vmvne q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmvnt q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
+# CHECK-NOFP: vmvnt q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
+# CHECK: vmvne q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
+# CHECK-NOFP: vmvne q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
+
+vpste
+vornt.s8 q0, q1, q2
+vorne.s8 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vornt q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
+# CHECK-NOFP: vornt q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
+# CHECK: vorne q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
+# CHECK-NOFP: vorne q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
+
+vpste
+vpselt.s16 q0, q1, q2
+vpsele.i32 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+
+vqadd.s8 q0, q1, q2
+# CHECK: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
+# CHECK-NOFP: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
+
+vpst
+vqaddt.s16 q0, q1, q2
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK-NOFP: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
+# CHECK-NOFP: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
+
+vqdmullt.s16 q0, q1, q2
+# CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
+
+vpste
+vqdmulltt.s32 q0, q1, q2
+vqdmullbe.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK-NOFP: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
+# CHECK: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+# CHECK-NOFP: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
+
+vqrshl.u32 q0, r0
+# CHECK: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+
+vpste
+vqrshlt.u16 q0, r0
+vqrshle.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+# CHECK-NOFP: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+
+vpste
+vrshlt.u16 q0, q1, q2
+vrshle.s32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK-NOFP: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+# CHECK-NOFP: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+
+vpste
+vshlt.s8 q0, r0
+vshle.u32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK-NOFP: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
+# CHECK-NOFP: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
+
+vshllt.s8 q0, q1, #1
+# CHECK: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
+# CHECK-NOFP: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
+
+vpste
+vshlltt.s16 q0, q1, #4
+vshllbe.u16 q0, q1, #8
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOFP: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOFP: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+
+vpste
+vqnegt.s8 q0, q1
+vqnege.s16 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
+# CHECK-NOFP: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
+# CHECK: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]
+# CHECK-NOFP: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]
+
+vpste
+vnegt.s8 q0, q1
+vnege.s8 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK-NOFP: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK-NOFP: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+
+vpste
+vmult.i16 q0, q1, q2
+vmule.i16 q1, q2, q3
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+# CHECK-NOFP: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+
+vpste
+vcmpt.i8 eq, q0, r0
+vcmpe.i16 ne, q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
+# CHECK-NOFP: vcmpt.i8 eq, q0, r0 @ encoding: [0x01,0xfe,0x40,0x0f]
+# CHECK: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
+# CHECK-NOFP: vcmpe.i16 ne, q0, r0 @ encoding: [0x11,0xfe,0xc0,0x0f]
+
+# SDCOMP-50323: ensure the scalar FP instructions VCMP and VCMPE are
+# still correctly distinguished, in spite of VCMPE sometimes being a
+# VPT-suffixed version of VCMP with identical encoding.
+vcmp.f16  s0,s1
+vcmpe.f16 s0,s1
+# CHECK: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
+# CHECK: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
+# CHECK-NOFP-NOT: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
+# CHECK-NOFP-NOT: vcmpe.f16 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x09]
+
+###############################################################################
+# The following tests were added to test load store aliases.
+###############################################################################
+
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+vldrb.s8 q0, [r0]
+
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+vldrb.f8 q0, [r0]
+
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+vldrb.8 q0, [r0]
+
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+vldrb.s8 q0, [r8, #56]
+
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+vldrb.f8 q0, [r8, #56]
+
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+# CHECK-NOFP: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+vldrb.8 q0, [r8, #56]
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+vldrb.s8 q5, [r4, #56]!
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+vldrb.f8 q5, [r4, #56]!
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOFP: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+vldrb.8 q5, [r4, #56]!
+
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+vstrb.u8 q0, [r0]
+
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+vstrb.s8 q0, [r0]
+
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+# CHECK-NOFP: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+vstrb.f8 q0, [r0]
+
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+vstrb.u8 q4, [r4, #56]
+
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+vstrb.s8 q4, [r4, #56]
+
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+# CHECK-NOFP: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+vstrb.f8 q4, [r4, #56]
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+vstrb.u8 q5, [r4, #56]!
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+vstrb.s8 q5, [r4, #56]!
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOFP: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+vstrb.f8 q5, [r4, #56]!
+
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+vldrh.s16 q0, [r0]
+
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+vldrh.f16 q0, [r0]
+
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+vldrh.16 q0, [r0]
+
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+vldrh.s16 q0, [r4, #56]
+
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+vldrh.f16 q0, [r4, #56]
+
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+# CHECK-NOFP: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+vldrh.16 q0, [r4, #56]
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+vldrh.s16 q5, [r4, #56]!
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+vldrh.f16 q5, [r4, #56]!
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+vldrh.16 q5, [r4, #56]!
+
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+vstrh.u16 q0, [r0]
+
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+vstrh.s16 q0, [r0]
+
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+vstrh.f16 q0, [r0]
+
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+vstrh.u16 q0, [r4, #56]
+
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+vstrh.s16 q0, [r4, #56]
+
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+# CHECK-NOFP: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+vstrh.f16 q0, [r4, #56]
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+vstrh.u16 q5, [r4, #56]!
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+vstrh.s16 q5, [r4, #56]!
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOFP: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+vstrh.f16 q5, [r4, #56]!
+
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+vldrw.s32 q0, [r0]
+
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+vldrw.f32 q0, [r0]
+
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+vldrw.32 q0, [r0]
+
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+vldrw.s32 q0, [r4, #56]
+
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+vldrw.f32 q0, [r4, #56]
+
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+# CHECK-NOFP: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+vldrw.32 q0, [r4, #56]
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+vldrw.s32 q5, [r4, #56]!
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+vldrw.f32 q5, [r4, #56]!
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+vldrw.32 q5, [r4, #56]!
+
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+vstrw.u32 q0, [r0]
+
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+vstrw.s32 q0, [r0]
+
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+vstrw.f32 q0, [r0]
+
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+vstrw.u32 q0, [r4, #56]
+
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+vstrw.s32 q0, [r4, #56]
+
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+# CHECK-NOFP: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+vstrw.f32 q0, [r4, #56]
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+vstrw.u32 q5, [r4, #56]!
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+vstrw.s32 q5, [r4, #56]!
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOFP: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+vstrw.f32 q5, [r4, #56]!
+
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+vldrb.s8 q0, [r0, q1]
+
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+vldrb.f8 q0, [r0, q1]
+
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+# CHECK-NOFP: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+vldrb.8 q0, [r0, q1]
+
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+vldrh.s16 q3, [r0, q1]
+
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+vldrh.f16 q3, [r0, q1]
+
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+# CHECK-NOFP: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+vldrh.16 q3, [r0, q1]
+
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+vldrh.s16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+vldrh.f16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+# CHECK-NOFP: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+vldrh.16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+vldrw.s32 q0, [r0, q1]
+
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+vldrw.f32 q0, [r0, q1]
+
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+vldrw.32 q0, [r0, q1]
+
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+vldrw.s32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+vldrw.f32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+# CHECK-NOFP: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+vldrw.32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+vldrd.s64 q0, [r0, q1]
+
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+vldrd.f64 q0, [r0, q1]
+
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+vldrd.64 q0, [r0, q1]
+
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+vldrd.s64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+vldrd.f64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+# CHECK-NOFP: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+vldrd.64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+vstrb.u8 q0, [r0, q1]
+
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+vstrb.s8 q0, [r0, q1]
+
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+# CHECK-NOFP: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+vstrb.f8 q0, [r0, q1]
+
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+vstrh.u16 q3, [r0, q1]
+
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+vstrh.s16 q3, [r0, q1]
+
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+# CHECK-NOFP: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+vstrh.f16 q3, [r0, q1]
+
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+vstrh.u16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+vstrh.s16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+# CHECK-NOFP: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+vstrh.f16 q0, [r0, q1, uxtw #1]
+
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+vstrw.u32 q0, [r0, q1]
+
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+vstrw.s32 q0, [r0, q1]
+
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+vstrw.f32 q0, [r0, q1]
+
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+vstrw.u32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+vstrw.s32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+# CHECK-NOFP: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+vstrw.f32 q0, [r0, q1, uxtw #2]
+
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+vstrd.u64 q3, [r0, q1]
+
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+vstrd.s64 q3, [r0, q1]
+
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+# CHECK-NOFP: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+vstrd.f64 q3, [r0, q1]
+
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+vstrd.u64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+vstrd.s64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+# CHECK-NOFP: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+vstrd.f64 q0, [r0, q1, uxtw #3]
+
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+vldrw.s32 q0, [q1]
+
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+vldrw.f32 q0, [q1]
+
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+# CHECK-NOFP: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+vldrw.32 q0, [q1]
+
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+vldrw.s32 q7, [q1]!
+
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+vldrw.f32 q7, [q1]!
+
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+vldrw.32 q7, [q1]!
+
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+vldrw.s32 q7, [q1, #4]
+
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+vldrw.f32 q7, [q1, #4]
+
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+vldrw.32 q7, [q1, #4]
+
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+vldrw.s32 q7, [q1, #4]!
+
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+vldrw.f32 q7, [q1, #4]!
+
+# CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+# CHECK-NOFP: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
+vldrw.u32 q7, [q1, #4]!
+
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+vstrw.u32 q0, [q1]
+
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+vstrw.s32 q0, [q1]
+
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+# CHECK-NOFP: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+vstrw.f32 q0, [q1]
+
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+vstrw.u32 q7, [q1]!
+
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+vstrw.s32 q7, [q1]!
+
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+vstrw.f32 q7, [q1]!
+
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+vstrw.u32 q7, [q1, #508]
+
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+vstrw.s32 q7, [q1, #508]
+
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+vstrw.f32 q7, [q1, #508]
+
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+vstrw.u32 q7, [q1, #264]!
+
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+vstrw.s32 q7, [q1, #264]!
+
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOFP: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+vstrw.f32 q7, [q1, #264]!
+
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+vldrd.s64 q0, [q1]
+
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+vldrd.f64 q0, [q1]
+
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+# CHECK-NOFP: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+vldrd.64 q0, [q1]
+
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+vldrd.s64 q7, [q1]!
+
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+vldrd.f64 q7, [q1]!
+
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+vldrd.64 q7, [q1]!
+
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+vldrd.s64 q7, [q1, #8]
+
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+vldrd.f64 q7, [q1, #8]
+
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+vldrd.64 q7, [q1, #8]
+
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+vldrd.s64 q7, [q1, #-1016]!
+
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+vldrd.f64 q7, [q1, #-1016]!
+
+# CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+# CHECK-NOFP: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
+vldrd.64 q7, [q1, #-1016]!
+
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+vstrd.u64 q0, [q1]
+
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+vstrd.s64 q0, [q1]
+
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+# CHECK-NOFP: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+vstrd.f64 q0, [q1]
+
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+vstrd.u64 q7, [q1]!
+
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+vstrd.s64 q7, [q1]!
+
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+vstrd.f64 q7, [q1]!
+
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+vstrd.u64 q7, [q1, #1016]
+
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+vstrd.s64 q7, [q1, #1016]
+
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+vstrd.f64 q7, [q1, #1016]
+
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+vstrd.u64 q7, [q1, #-8]!
+
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+vstrd.s64 q7, [q1, #-8]!
+
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+# CHECK-NOFP: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+vstrd.f64 q7, [q1, #-8]!
+
+vpste
+vstrwt.f32 q7, [q1, #264]!
+vldrde.64 q7, [q1, #8]
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOFP: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOFP: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+
+# The following tests have to go last because of the NOFP-NOT checks inside the
+# VPT block.
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+vpte.i8 eq, q0, q0
+vminnmavt.f32 lr, q3
+vminnmave.f32 lr, q3
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vmaxnmt.f16 q1, q6, q2  @ encoding: [0x1c,0xff,0x54,0x2f]
+# CHECK-NOFP-NOT: vmaxnmt.f16 q1, q6, q2  @ encoding: [0x1c,0xff,0x54,0x2f]
+# CHECK-NOFP-NOT: vmaxnme.f16 q1, q6, q2  @ encoding: [0x1c,0xff,0x54,0x2f]
+vpte.i8 eq, q0, q0
+vmaxnmt.f16 q1, q6, q2
+vmaxnme.f16 q1, q6, q2
+
+vpstet
+vcvtbt.f16.f32 q0, q1
+vcvtne.s16.f16 q0, q1
+vcvtmt.s16.f16 q0, q1
+# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
+# CHECK: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
+# CHECK: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK-NOFP-NOT: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
+# CHECK: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+# CHECK-NOFP-NOT: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
+
+vpste
+vcvtmt.u32.f32 q0, q1
+vcvtne.s32.f32 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vtmt.u32.f32 q0, q1 @ encoding: [0xbb,0xff,0xc2,0x03]
+# CHECK-NOFP-NOT: vtmt.u32.f32 q0, q1 @ encoding: [0xbb,0xff,0xc2,0x03]
+# CHECK: vcvtne.s32.f32 q0, q1 @ encoding: [0xbb,0xff,0x42,0x01]
+# CHECK-NOFP-NOT: vcvtne.s32.f32 q0, q1 @ encoding: [0xbb,0xff,0x42,0x01]
+
+it ne
+vcvtne.s32.f32 s0, s1
+# CHECK: it ne @ encoding: [0x18,0xbf]
+# CHECK: vcvtne.s32.f32 s0, s1 @ encoding: [0xbd,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvtne.s32.f32 s0, s1 @ encoding: [0xbd,0xee,0xe0,0x0a]
+
+
+it eq
+vaddeq.f32 s0, s1
+# CHECK:  it  eq @ encoding: [0x08,0xbf]
+# CHECK: vaddeq.f32  s0, s0, s1 @ encoding: [0x30,0xee,0x20,0x0a]
+# CHECK-NOFP-NOT: vaddeq.f32  s0, s0, s1 @ encoding: [0x30,0xee,0x20,0x0a]
+
+vpst
+vaddt.f16 q0, q1, q2
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vaddt.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d]
+# CHECK-NOFP-NOT: vaddt.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d]
+
+vpste
+vcmult.f16 q0, q1, q2, #180
+vcmule.f16 q0, q1, q2, #180
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+# CHECK-NOFP-NOT: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
+
+it ge
+vcvttge.f64.f16 d3, s1
+# CHECK: it ge @ encoding: [0xa8,0xbf]
+# CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
+# CHECK-NOFP-NOT: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
+
+vpste
+vmult.f16 q0, q1, q2
+vmule.f16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
+# CHECK-NOFP-NOT: vmult.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
+# CHECK: vmule.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
+# CHECK-NOFP-NOT: vmule.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
+
+vpste
+vrintnt.f16 q0, q1
+vrintne.f32 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vrintnt.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x04]
+# CHECK-NOFP-NOT: vrintnt.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x04]
+# CHECK: vrintne.f32 q0, q1 @ encoding: [0xba,0xff,0x42,0x04]
+# CHECK-NOFP-NOT: vrintne.f32 q0, q1 @ encoding: [0xba,0xff,0x42,0x04]
+
+ite eq
+vmuleq.f64 d0, d0, d1
+vmulne.f64 d1, d0, d2
+# CHECK: ite eq @ encoding: [0x0c,0xbf]
+# CHECK: vmuleq.f64 d0, d0, d1 @ encoding: [0x20,0xee,0x01,0x0b]
+# CHECK-NOFP-NOT: vmuleq.f64 d0, d0, d1 @ encoding: [0x20,0xee,0x01,0x0b]
+# CHECK: vmulne.f64 d1, d0, d2 @ encoding: [0x20,0xee,0x02,0x1b]
+# CHECK-NOFP-NOT: vmulne.f64 d1, d0, d2 @ encoding: [0x20,0xee,0x02,0x1b]
+
+it eq
+vnegeq.f32 s0, s1
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK: vnegeq.f32 s0, s1 @ encoding: [0xb1,0xee,0x60,0x0a]
+# CHECK-NOFP-NOT: vnegeq.f32 s0, s1 @ encoding: [0xb1,0xee,0x60,0x0a]
+
+itt eq
+vnmuleq.f32 s0, s1, s2
+vmuleq.f32 s0, s1, s2
+# CHECK: itt eq @ encoding: [0x04,0xbf]
+# CHECK: vnmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0xc1,0x0a]
+# CHECK-NOFP-NOT: vnmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0xc1,0x0a]
+# CHECK: vmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0x81,0x0a]
+# CHECK-NOFP-NOT: vmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0x81,0x0a]
+
+itt eq
+vcmpeq.f32 s0, s1
+vcmpeeq.f32 s0, s1
+# CHECK: itt eq @ encoding: [0x04,0xbf]
+# CHECK: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
+# CHECK-NOFP-NOT: vcmpeq.f32 s0, s1 @ encoding: [0xb4,0xee,0x60,0x0a]
+# CHECK: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcmpeeq.f32 s0, s1 @ encoding: [0xb4,0xee,0xe0,0x0a]
+
+vpte.f32 lt, q3, r1
+vcvtt.u32.f32 q2, q0
+vcvte.u32.f32 q1, q0
+# CHECK: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvtt.u32.f32 q2, q0          @ encoding: [0xbb,0xff,0xc0,0x47]
+# CHECK-NOFP-NOT: vcvtt.u32.f32 q2, q0          @ encoding: [0xbb,0xff,0xc0,0x47]
+# CHECK: vcvte.u32.f32 q1, q0          @ encoding: [0xbb,0xff,0xc0,0x27]
+# CHECK-NOFP-NOT: vcvte.u32.f32 q1, q0          @ encoding: [0xbb,0xff,0xc0,0x27]
+
+vpte.f32 lt, q3, r1
+vcvttt.f16.f32 q2, q0
+vcvtte.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvttt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK-NOFP-NOT: vcvttt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x5e]
+# CHECK: vcvtte.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x3e]
+
+vpte.f32 lt, q3, r1
+vcvtbt.f16.f32 q2, q0
+vcvtbe.f32.f16 q1, q0
+# CHECK: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xc1,0x9f]
+# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1      @ encoding: [0x77,0xee,0xe1,0x8f]
+# CHECK: vcvtbt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK-NOFP-NOT: vcvtbt.f16.f32 q2, q0          @ encoding: [0x3f,0xee,0x01,0x4e]
+# CHECK: vcvtbe.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x2e]
+# CHECK-NOFP-NOT: vcvtbe.f32.f16 q1, q0          @ encoding: [0x3f,0xfe,0x01,0x2e]
+
+ite eq
+vcvtteq.f16.f32 s0, s1
+vcvttne.f16.f32 s0, s1
+# CHECK: ite eq                      @ encoding: [0x0c,0xbf]
+# CHECK: vcvtteq.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvtteq.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK: vcvttne.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvttne.f16.f32 s0, s1          @ encoding: [0xb3,0xee,0xe0,0x0a]
+
+ite eq
+vcvteq.u32.f32 s0, s1
+vcvtne.f32.u32 s0, s1
+# CHECK: ite eq                      @ encoding: [0x0c,0xbf]
+# CHECK: vcvteq.u32.f32 s0, s1          @ encoding: [0xbc,0xee,0xe0,0x0a]
+# CHECK-NOFP-NOT: vcvteq.u32.f32 s0, s1          @ encoding: [0xbc,0xee,0xe0,0x0a]
+# CHECK: vcvtne.f32.u32  s0, s1          @ encoding: [0xb8,0xee,0x60,0x0a]
+# CHECK-NOFP-NOT: vcvtne.f32.u32  s0, s1          @ encoding: [0xb8,0xee,0x60,0x0a]
diff --git a/llvm/test/MC/ARM/no-mve.s b/llvm/test/MC/ARM/no-mve.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/no-mve.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding  < %s 2>%t
+# RUN: FileCheck < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s &>%t
+# RUN: FileCheck --check-prefix=CHECK-MVE < %t %s
+
+# CHECK-MVE: instruction requires: mve.fp
+# CHECK: invalid instruction
+vcadd.f32 q1, q2, q3, #270
+
+# CHECK-MVE: instruction requires: mve.fp
+# CHECK: invalid instruction
+vadd.f32 q1, q2, q3
+
+# CHECK-MVE: vadd.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x46,0x28]
+# CHECK: invalid instruction
+vadd.i16 q1, q2, q3
diff --git a/llvm/test/MC/ARM/ras-extension.s b/llvm/test/MC/ARM/ras-extension.s
--- a/llvm/test/MC/ARM/ras-extension.s
+++ b/llvm/test/MC/ARM/ras-extension.s
@@ -1,6 +1,9 @@
 @ RUN: llvm-mc -triple   armv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=ARM
 @ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=THUMB
+@ RUN: llvm-mc -triple thumbv8.1m.main-none-eabi -show-encoding %s | FileCheck %s --check-prefix=THUMB
+@ RUN: not llvm-mc -triple thumbv8m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=FAIL
 
   esb
 @ ARM:   esb   @ encoding: [0x10,0xf0,0x20,0xe3]
 @ THUMB: esb.w @ encoding: [0xaf,0xf3,0x10,0x80]
+@ FAIL: instruction requires: ras
diff --git a/llvm/test/MC/ARM/thumbv8.1m-vmrs-vmsr.s b/llvm/test/MC/ARM/thumbv8.1m-vmrs-vmsr.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/thumbv8.1m-vmrs-vmsr.s
@@ -0,0 +1,98 @@
+// RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve -show-encoding < %s \
+// RUN: | FileCheck --check-prefix=CHECK %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,+mve -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
+// RUN:   FileCheck --check-prefix=ERROR-NOSEC < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,-mve,+vfp2 -show-encoding < %s 2> %t \
+// RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
+// RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
+// RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve,-vfp2 -show-encoding < %s \
+// RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,-mve,-vfp2 -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=ERROR-NONE < %t %s
+// RUN: not llvm-mc -triple=thumbv8m.main-none-eabi -mattr=+8msecext,+vfp2 -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOVFP: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+// CHECK-NOMVE: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+// CHECK-NOSEC: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+// CHECK: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+vmsr fpscr_nzcvqc, r0
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOVFP: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+// CHECK-NOMVE: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+// CHECK-NOSEC: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+// CHECK: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+vmrs r10, fpscr_nzcvqc
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOVFP: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+// CHECK-NOMVE: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+vmrs r0, fpcxtns
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOVFP: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+// CHECK-NOMVE: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+vmsr fpcxtns, r10
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOVFP: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+// CHECK-NOMVE: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+vmsr fpcxts, r5
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOVFP: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+// CHECK-NOMVE: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+vmrs r3, fpcxtns
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOVFP: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+// CHECK-NOMVE: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+vmrs r0, fpcxts
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOSEC: vmrs r0, vpr              @ encoding: [0xfc,0xee,0x10,0x0a]
+// CHECK: vmrs r0, vpr              @ encoding: [0xfc,0xee,0x10,0x0a]
+vmrs r0, vpr
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOSEC: vmrs r4, p0              @ encoding: [0xfd,0xee,0x10,0x4a]
+// CHECK: vmrs r4, p0              @ encoding: [0xfd,0xee,0x10,0x4a]
+vmrs r4, p0
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOSEC: vmsr vpr, r0              @ encoding: [0xec,0xee,0x10,0x0a]
+// CHECK: vmsr vpr, r0              @ encoding: [0xec,0xee,0x10,0x0a]
+vmsr vpr, r0
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOSEC: vmsr p0, r4              @ encoding: [0xed,0xee,0x10,0x4a]
+// CHECK: vmsr p0, r4              @ encoding: [0xed,0xee,0x10,0x4a]
+vmsr p0, r4
diff --git a/llvm/test/MC/ARM/thumbv8.1m.s b/llvm/test/MC/ARM/thumbv8.1m.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/thumbv8.1m.s
@@ -0,0 +1,868 @@
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
+// RUN:   | FileCheck --check-prefix=CHECK %s
+// RUN:     FileCheck --check-prefix=ERROR < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+fp-armv8,+fullfp16,+fp-only-sp -show-encoding < %s 2>%t \
+// RUN:   | FileCheck --check-prefix=CHECK-FP %s
+// RUN:     FileCheck --check-prefix=ERROR-FP < %t %s
+
+// Check that .arm is invalid
+// ERROR: target does not support ARM mode
+// ERROR-FP: target does not support ARM mode
+.arm
+
+// Make sure the addition of CLRM does not mess up normal register lists
+// ERROR: invalid operand for instruction
+// ERROR-FP: invalid operand for instruction
+push {r0, apsr}
+
+// Instruction availibility checks
+
+// 'Branch Future and Low Overhead Loop instructions'
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bf #-2, #10
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bf #0, #10
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bf #7, #10
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfx #-4, r3
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfx #0, r3
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfx #13, r3
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfl #-2, #20
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfl #0, #20
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfl #13, #20
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bf #4, #65536
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bf #4, #-65538
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bfl #4, #262144
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bfl #4, #-262146
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfcsel #-2, #10, #2, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfcsel #0, #10, #2, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
+bfcsel #13, #10, #15, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bfcsel #4, #65536, #6, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
+bfcsel #4, #-65538, #8, eq
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
+bfcsel #4, #65534, #10, eq
+
+// CHECK: bf  .Lbranch, .Ltarget      @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
+// CHECK-FP: bf  .Lbranch, .Ltarget      @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
+bf  .Lbranch, .Ltarget
+
+// CHECK: bfcsel  .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
+// CHECK-FP: bfcsel  .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
+bfcsel  .Lbranch, .Lthen, .Lelse, ne
+
+// CHECK: bfx .Lbranch, r3            @ encoding: [0x63'A',0xf0'A',0x01'A',0xe0'A']
+// CHECK-FP: bfx .Lbranch, r3            @ encoding: [0x63'A',0xf0'A',0x01'A',0xe0'A']
+bfx .Lbranch, r3
+
+// CHECK: bfl .Lbranch, .Ltarget      @ encoding: [B,0xf0'B',0x01'B',0xc0'B']
+// CHECK-FP: bfl .Lbranch, .Ltarget      @ encoding: [B,0xf0'B',0x01'B',0xc0'B']
+bfl .Lbranch, .Ltarget
+
+// CHECK: bflx .Lbranch, r7           @ encoding: [0x77'A',0xf0'A',0x01'A',0xe0'A']
+// CHECK-FP: bflx .Lbranch, r7           @ encoding: [0x77'A',0xf0'A',0x01'A',0xe0'A']
+bflx .Lbranch, r7
+
+// CHECK: wls lr, r2, .Lend           @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
+// CHECK-FP: wls lr, r2, .Lend           @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
+wls lr, r2, .Lend
+
+// CHECK: dls lr, r2                  @ encoding: [0x42,0xf0,0x01,0xe0]
+// CHECK-FP: dls lr, r2                  @ encoding: [0x42,0xf0,0x01,0xe0]
+dls lr, r2
+
+// CHECK: le lr, .Lstart              @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
+// CHECK-FP: le lr, .Lstart              @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
+le lr, .Lstart
+
+// CHECK: le  .Lstart                 @ encoding: [0x2f'A',0xf0'A',0x01'A',0xc0'A']
+// CHECK-FP: le  .Lstart                 @ encoding: [0x2f'A',0xf0'A',0x01'A',0xc0'A']
+le .Lstart
+
+// CHECK: dls     lr, lr  @ encoding: [0x4e,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, lr  @ encoding: [0x4e,0xf0,0x01,0xe0]
+dls     lr, lr
+
+// CHECK: dls     lr, r0  @ encoding: [0x40,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r0  @ encoding: [0x40,0xf0,0x01,0xe0]
+dls     lr, r0
+
+// CHECK: dls     lr, r1  @ encoding: [0x41,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r1  @ encoding: [0x41,0xf0,0x01,0xe0]
+dls     lr, r1
+
+// CHECK: dls     lr, r10  @ encoding: [0x4a,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r10  @ encoding: [0x4a,0xf0,0x01,0xe0]
+dls     lr, r10
+
+// CHECK: dls     lr, r11  @ encoding: [0x4b,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r11  @ encoding: [0x4b,0xf0,0x01,0xe0]
+dls     lr, r11
+
+// CHECK: dls     lr, r12  @ encoding: [0x4c,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r12  @ encoding: [0x4c,0xf0,0x01,0xe0]
+dls     lr, r12
+
+// CHECK: dls     lr, r2  @ encoding: [0x42,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r2  @ encoding: [0x42,0xf0,0x01,0xe0]
+dls     lr, r2
+
+// CHECK: dls     lr, r3  @ encoding: [0x43,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r3  @ encoding: [0x43,0xf0,0x01,0xe0]
+dls     lr, r3
+
+// CHECK: dls     lr, r5  @ encoding: [0x45,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r5  @ encoding: [0x45,0xf0,0x01,0xe0]
+dls     lr, r5
+
+// CHECK: dls     lr, r6  @ encoding: [0x46,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r6  @ encoding: [0x46,0xf0,0x01,0xe0]
+dls     lr, r6
+
+// CHECK: dls     lr, r7  @ encoding: [0x47,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r7  @ encoding: [0x47,0xf0,0x01,0xe0]
+dls     lr, r7
+
+// CHECK: dls     lr, r8  @ encoding: [0x48,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r8  @ encoding: [0x48,0xf0,0x01,0xe0]
+dls     lr, r8
+
+// CHECK: dls     lr, r9  @ encoding: [0x49,0xf0,0x01,0xe0]
+// CHECK-FP: dls     lr, r9  @ encoding: [0x49,0xf0,0x01,0xe0]
+dls     lr, r9
+
+// CHECK: le      #-106  @ encoding: [0x2f,0xf0,0x35,0xc8]
+// CHECK-FP: le      #-106  @ encoding: [0x2f,0xf0,0x35,0xc8]
+le      #-106
+
+// CHECK: le      #-1172  @ encoding: [0x2f,0xf0,0x4b,0xc2]
+// CHECK-FP: le      #-1172  @ encoding: [0x2f,0xf0,0x4b,0xc2]
+le      #-1172
+
+// CHECK: le      #-1210  @ encoding: [0x2f,0xf0,0x5d,0xca]
+// CHECK-FP: le      #-1210  @ encoding: [0x2f,0xf0,0x5d,0xca]
+le      #-1210
+
+// CHECK: le      #-1260  @ encoding: [0x2f,0xf0,0x77,0xc2]
+// CHECK-FP: le      #-1260  @ encoding: [0x2f,0xf0,0x77,0xc2]
+le      #-1260
+
+// CHECK: le      #-1262  @ encoding: [0x2f,0xf0,0x77,0xca]
+// CHECK-FP: le      #-1262  @ encoding: [0x2f,0xf0,0x77,0xca]
+le      #-1262
+
+// CHECK: le      #-1284  @ encoding: [0x2f,0xf0,0x83,0xc2]
+// CHECK-FP: le      #-1284  @ encoding: [0x2f,0xf0,0x83,0xc2]
+le      #-1284
+
+// CHECK: le      #-1286  @ encoding: [0x2f,0xf0,0x83,0xca]
+// CHECK-FP: le      #-1286  @ encoding: [0x2f,0xf0,0x83,0xca]
+le      #-1286
+
+// CHECK: le      #-1556  @ encoding: [0x2f,0xf0,0x0b,0xc3]
+// CHECK-FP: le      #-1556  @ encoding: [0x2f,0xf0,0x0b,0xc3]
+le      #-1556
+
+// CHECK: le      #-178  @ encoding: [0x2f,0xf0,0x59,0xc8]
+// CHECK-FP: le      #-178  @ encoding: [0x2f,0xf0,0x59,0xc8]
+le      #-178
+
+// CHECK: le      #-1882  @ encoding: [0x2f,0xf0,0xad,0xcb]
+// CHECK-FP: le      #-1882  @ encoding: [0x2f,0xf0,0xad,0xcb]
+le      #-1882
+
+// CHECK: le      #-1900  @ encoding: [0x2f,0xf0,0xb7,0xc3]
+// CHECK-FP: le      #-1900  @ encoding: [0x2f,0xf0,0xb7,0xc3]
+le      #-1900
+
+// CHECK: le      #-1910  @ encoding: [0x2f,0xf0,0xbb,0xcb]
+// CHECK-FP: le      #-1910  @ encoding: [0x2f,0xf0,0xbb,0xcb]
+le      #-1910
+
+// CHECK: le      #-2076  @ encoding: [0x2f,0xf0,0x0f,0xc4]
+// CHECK-FP: le      #-2076  @ encoding: [0x2f,0xf0,0x0f,0xc4]
+le      #-2076
+
+// CHECK: le      #-2266  @ encoding: [0x2f,0xf0,0x6d,0xcc]
+// CHECK-FP: le      #-2266  @ encoding: [0x2f,0xf0,0x6d,0xcc]
+le      #-2266
+
+// CHECK: le      #-2324  @ encoding: [0x2f,0xf0,0x8b,0xc4]
+// CHECK-FP: le      #-2324  @ encoding: [0x2f,0xf0,0x8b,0xc4]
+le      #-2324
+
+// CHECK: le      #-2328  @ encoding: [0x2f,0xf0,0x8d,0xc4]
+// CHECK-FP: le      #-2328  @ encoding: [0x2f,0xf0,0x8d,0xc4]
+le      #-2328
+
+// CHECK: le      #-2456  @ encoding: [0x2f,0xf0,0xcd,0xc4]
+// CHECK-FP: le      #-2456  @ encoding: [0x2f,0xf0,0xcd,0xc4]
+le      #-2456
+
+// CHECK: le      #-246  @ encoding: [0x2f,0xf0,0x7b,0xc8]
+// CHECK-FP: le      #-246  @ encoding: [0x2f,0xf0,0x7b,0xc8]
+le      #-246
+
+// CHECK: le      #-2476  @ encoding: [0x2f,0xf0,0xd7,0xc4]
+// CHECK-FP: le      #-2476  @ encoding: [0x2f,0xf0,0xd7,0xc4]
+le      #-2476
+
+// CHECK: le      #-2578  @ encoding: [0x2f,0xf0,0x09,0xcd]
+// CHECK-FP: le      #-2578  @ encoding: [0x2f,0xf0,0x09,0xcd]
+le      #-2578
+
+// CHECK: le      #-262  @ encoding: [0x2f,0xf0,0x83,0xc8]
+// CHECK-FP: le      #-262  @ encoding: [0x2f,0xf0,0x83,0xc8]
+le      #-262
+
+// CHECK: le      #-2660  @ encoding: [0x2f,0xf0,0x33,0xc5]
+// CHECK-FP: le      #-2660  @ encoding: [0x2f,0xf0,0x33,0xc5]
+le      #-2660
+
+// CHECK: le      #-2722  @ encoding: [0x2f,0xf0,0x51,0xcd]
+// CHECK-FP: le      #-2722  @ encoding: [0x2f,0xf0,0x51,0xcd]
+le      #-2722
+
+// CHECK: le      #-2868  @ encoding: [0x2f,0xf0,0x9b,0xc5]
+// CHECK-FP: le      #-2868  @ encoding: [0x2f,0xf0,0x9b,0xc5]
+le      #-2868
+
+// CHECK: le      #-2882  @ encoding: [0x2f,0xf0,0xa1,0xcd]
+// CHECK-FP: le      #-2882  @ encoding: [0x2f,0xf0,0xa1,0xcd]
+le      #-2882
+
+// CHECK: le      #-3154  @ encoding: [0x2f,0xf0,0x29,0xce]
+// CHECK-FP: le      #-3154  @ encoding: [0x2f,0xf0,0x29,0xce]
+le      #-3154
+
+// CHECK: le      #-3274  @ encoding: [0x2f,0xf0,0x65,0xce]
+// CHECK-FP: le      #-3274  @ encoding: [0x2f,0xf0,0x65,0xce]
+le      #-3274
+
+// CHECK: le      #-3352  @ encoding: [0x2f,0xf0,0x8d,0xc6]
+// CHECK-FP: le      #-3352  @ encoding: [0x2f,0xf0,0x8d,0xc6]
+le      #-3352
+
+// CHECK: le      #-338  @ encoding: [0x2f,0xf0,0xa9,0xc8]
+// CHECK-FP: le      #-338  @ encoding: [0x2f,0xf0,0xa9,0xc8]
+le      #-338
+
+// CHECK: le      #-3458  @ encoding: [0x2f,0xf0,0xc1,0xce]
+// CHECK-FP: le      #-3458  @ encoding: [0x2f,0xf0,0xc1,0xce]
+le      #-3458
+
+// CHECK: le      #-3480  @ encoding: [0x2f,0xf0,0xcd,0xc6]
+// CHECK-FP: le      #-3480  @ encoding: [0x2f,0xf0,0xcd,0xc6]
+le      #-3480
+
+// CHECK: le      #-3542  @ encoding: [0x2f,0xf0,0xeb,0xce]
+// CHECK-FP: le      #-3542  @ encoding: [0x2f,0xf0,0xeb,0xce]
+le      #-3542
+
+// CHECK: le      #-3644  @ encoding: [0x2f,0xf0,0x1f,0xc7]
+// CHECK-FP: le      #-3644  @ encoding: [0x2f,0xf0,0x1f,0xc7]
+le      #-3644
+
+// CHECK: le      #-3676  @ encoding: [0x2f,0xf0,0x2f,0xc7]
+// CHECK-FP: le      #-3676  @ encoding: [0x2f,0xf0,0x2f,0xc7]
+le      #-3676
+
+// CHECK: le      #-3692  @ encoding: [0x2f,0xf0,0x37,0xc7]
+// CHECK-FP: le      #-3692  @ encoding: [0x2f,0xf0,0x37,0xc7]
+le      #-3692
+
+// CHECK: le      #-3860  @ encoding: [0x2f,0xf0,0x8b,0xc7]
+// CHECK-FP: le      #-3860  @ encoding: [0x2f,0xf0,0x8b,0xc7]
+le      #-3860
+
+// CHECK: le      #-3986  @ encoding: [0x2f,0xf0,0xc9,0xcf]
+// CHECK-FP: le      #-3986  @ encoding: [0x2f,0xf0,0xc9,0xcf]
+le      #-3986
+
+// CHECK: le      #-4006  @ encoding: [0x2f,0xf0,0xd3,0xcf]
+// CHECK-FP: le      #-4006  @ encoding: [0x2f,0xf0,0xd3,0xcf]
+le      #-4006
+
+// CHECK: le      #-4034  @ encoding: [0x2f,0xf0,0xe1,0xcf]
+// CHECK-FP: le      #-4034  @ encoding: [0x2f,0xf0,0xe1,0xcf]
+le      #-4034
+
+// CHECK: le      #-4060  @ encoding: [0x2f,0xf0,0xef,0xc7]
+// CHECK-FP: le      #-4060  @ encoding: [0x2f,0xf0,0xef,0xc7]
+le      #-4060
+
+// CHECK: le      #-4068  @ encoding: [0x2f,0xf0,0xf3,0xc7]
+// CHECK-FP: le      #-4068  @ encoding: [0x2f,0xf0,0xf3,0xc7]
+le      #-4068
+
+// CHECK: le      #-478  @ encoding: [0x2f,0xf0,0xef,0xc8]
+// CHECK-FP: le      #-478  @ encoding: [0x2f,0xf0,0xef,0xc8]
+le      #-478
+
+// CHECK: le      #-544  @ encoding: [0x2f,0xf0,0x11,0xc1]
+// CHECK-FP: le      #-544  @ encoding: [0x2f,0xf0,0x11,0xc1]
+le      #-544
+
+// CHECK: le      #-586  @ encoding: [0x2f,0xf0,0x25,0xc9]
+// CHECK-FP: le      #-586  @ encoding: [0x2f,0xf0,0x25,0xc9]
+le      #-586
+
+// CHECK: le      #-606  @ encoding: [0x2f,0xf0,0x2f,0xc9]
+// CHECK-FP: le      #-606  @ encoding: [0x2f,0xf0,0x2f,0xc9]
+le      #-606
+
+// CHECK: le      #-656  @ encoding: [0x2f,0xf0,0x49,0xc1]
+// CHECK-FP: le      #-656  @ encoding: [0x2f,0xf0,0x49,0xc1]
+le      #-656
+
+// CHECK: le      #-740  @ encoding: [0x2f,0xf0,0x73,0xc1]
+// CHECK-FP: le      #-740  @ encoding: [0x2f,0xf0,0x73,0xc1]
+le      #-740
+
+// CHECK: le      #-762  @ encoding: [0x2f,0xf0,0x7d,0xc9]
+// CHECK-FP: le      #-762  @ encoding: [0x2f,0xf0,0x7d,0xc9]
+le      #-762
+
+// CHECK: le      #-862  @ encoding: [0x2f,0xf0,0xaf,0xc9]
+// CHECK-FP: le      #-862  @ encoding: [0x2f,0xf0,0xaf,0xc9]
+le      #-862
+
+// CHECK: le      #-870  @ encoding: [0x2f,0xf0,0xb3,0xc9]
+// CHECK-FP: le      #-870  @ encoding: [0x2f,0xf0,0xb3,0xc9]
+le      #-870
+
+// CHECK: le      lr, #-1080  @ encoding: [0x0f,0xf0,0x1d,0xc2]
+// CHECK-FP: le      lr, #-1080  @ encoding: [0x0f,0xf0,0x1d,0xc2]
+le      lr, #-1080
+
+// CHECK: le      lr, #-1104  @ encoding: [0x0f,0xf0,0x29,0xc2]
+// CHECK-FP: le      lr, #-1104  @ encoding: [0x0f,0xf0,0x29,0xc2]
+le      lr, #-1104
+
+// CHECK: le      lr, #-1152  @ encoding: [0x0f,0xf0,0x41,0xc2]
+// CHECK-FP: le      lr, #-1152  @ encoding: [0x0f,0xf0,0x41,0xc2]
+le      lr, #-1152
+
+// CHECK: le      lr, #-1462  @ encoding: [0x0f,0xf0,0xdb,0xca]
+// CHECK-FP: le      lr, #-1462  @ encoding: [0x0f,0xf0,0xdb,0xca]
+le      lr, #-1462
+
+// CHECK: le      lr, #-1470  @ encoding: [0x0f,0xf0,0xdf,0xca]
+// CHECK-FP: le      lr, #-1470  @ encoding: [0x0f,0xf0,0xdf,0xca]
+le      lr, #-1470
+
+// CHECK: le      lr, #-1612  @ encoding: [0x0f,0xf0,0x27,0xc3]
+// CHECK-FP: le      lr, #-1612  @ encoding: [0x0f,0xf0,0x27,0xc3]
+le      lr, #-1612
+
+// CHECK: le      lr, #-1632  @ encoding: [0x0f,0xf0,0x31,0xc3]
+// CHECK-FP: le      lr, #-1632  @ encoding: [0x0f,0xf0,0x31,0xc3]
+le      lr, #-1632
+
+// CHECK: le      lr, #-1694  @ encoding: [0x0f,0xf0,0x4f,0xcb]
+// CHECK-FP: le      lr, #-1694  @ encoding: [0x0f,0xf0,0x4f,0xcb]
+le      lr, #-1694
+
+// CHECK: le      lr, #-1714  @ encoding: [0x0f,0xf0,0x59,0xcb]
+// CHECK-FP: le      lr, #-1714  @ encoding: [0x0f,0xf0,0x59,0xcb]
+le      lr, #-1714
+
+// CHECK: le      lr, #-1850  @ encoding: [0x0f,0xf0,0x9d,0xcb]
+// CHECK-FP: le      lr, #-1850  @ encoding: [0x0f,0xf0,0x9d,0xcb]
+le      lr, #-1850
+
+// CHECK: le      lr, #-1878  @ encoding: [0x0f,0xf0,0xab,0xcb]
+// CHECK-FP: le      lr, #-1878  @ encoding: [0x0f,0xf0,0xab,0xcb]
+le      lr, #-1878
+
+// CHECK: le      lr, #-1896  @ encoding: [0x0f,0xf0,0xb5,0xc3]
+// CHECK-FP: le      lr, #-1896  @ encoding: [0x0f,0xf0,0xb5,0xc3]
+le      lr, #-1896
+
+// CHECK: le      lr, #-1922  @ encoding: [0x0f,0xf0,0xc1,0xcb]
+// CHECK-FP: le      lr, #-1922  @ encoding: [0x0f,0xf0,0xc1,0xcb]
+le      lr, #-1922
+
+// CHECK: le      lr, #-1926  @ encoding: [0x0f,0xf0,0xc3,0xcb]
+// CHECK-FP: le      lr, #-1926  @ encoding: [0x0f,0xf0,0xc3,0xcb]
+le      lr, #-1926
+
+// CHECK: le      lr, #-2  @ encoding: [0x0f,0xf0,0x01,0xc8]
+// CHECK-FP: le      lr, #-2  @ encoding: [0x0f,0xf0,0x01,0xc8]
+le      lr, #-2
+
+// CHECK: le      lr, #-2104  @ encoding: [0x0f,0xf0,0x1d,0xc4]
+// CHECK-FP: le      lr, #-2104  @ encoding: [0x0f,0xf0,0x1d,0xc4]
+le      lr, #-2104
+
+// CHECK: le      lr, #-2116  @ encoding: [0x0f,0xf0,0x23,0xc4]
+// CHECK-FP: le      lr, #-2116  @ encoding: [0x0f,0xf0,0x23,0xc4]
+le      lr, #-2116
+
+// CHECK: le      lr, #-2144  @ encoding: [0x0f,0xf0,0x31,0xc4]
+// CHECK-FP: le      lr, #-2144  @ encoding: [0x0f,0xf0,0x31,0xc4]
+le      lr, #-2144
+
+// CHECK: le      lr, #-2188  @ encoding: [0x0f,0xf0,0x47,0xc4]
+// CHECK-FP: le      lr, #-2188  @ encoding: [0x0f,0xf0,0x47,0xc4]
+le      lr, #-2188
+
+// CHECK: le      lr, #-2344  @ encoding: [0x0f,0xf0,0x95,0xc4]
+// CHECK-FP: le      lr, #-2344  @ encoding: [0x0f,0xf0,0x95,0xc4]
+le      lr, #-2344
+
+// CHECK: le      lr, #-2456  @ encoding: [0x0f,0xf0,0xcd,0xc4]
+// CHECK-FP: le      lr, #-2456  @ encoding: [0x0f,0xf0,0xcd,0xc4]
+le      lr, #-2456
+
+// CHECK: le      lr, #-2608  @ encoding: [0x0f,0xf0,0x19,0xc5]
+// CHECK-FP: le      lr, #-2608  @ encoding: [0x0f,0xf0,0x19,0xc5]
+le      lr, #-2608
+
+// CHECK: le      lr, #-2616  @ encoding: [0x0f,0xf0,0x1d,0xc5]
+// CHECK-FP: le      lr, #-2616  @ encoding: [0x0f,0xf0,0x1d,0xc5]
+le      lr, #-2616
+
+// CHECK: le      lr, #-2622  @ encoding: [0x0f,0xf0,0x1f,0xcd]
+// CHECK-FP: le      lr, #-2622  @ encoding: [0x0f,0xf0,0x1f,0xcd]
+le      lr, #-2622
+
+// CHECK: le      lr, #-2680  @ encoding: [0x0f,0xf0,0x3d,0xc5]
+// CHECK-FP: le      lr, #-2680  @ encoding: [0x0f,0xf0,0x3d,0xc5]
+le      lr, #-2680
+
+// CHECK: le      lr, #-2694  @ encoding: [0x0f,0xf0,0x43,0xcd]
+// CHECK-FP: le      lr, #-2694  @ encoding: [0x0f,0xf0,0x43,0xcd]
+le      lr, #-2694
+
+// CHECK: le      lr, #-2850  @ encoding: [0x0f,0xf0,0x91,0xcd]
+// CHECK-FP: le      lr, #-2850  @ encoding: [0x0f,0xf0,0x91,0xcd]
+le      lr, #-2850
+
+// CHECK: le      lr, #-2860  @ encoding: [0x0f,0xf0,0x97,0xc5]
+// CHECK-FP: le      lr, #-2860  @ encoding: [0x0f,0xf0,0x97,0xc5]
+le      lr, #-2860
+
+// CHECK: le      lr, #-3004  @ encoding: [0x0f,0xf0,0xdf,0xc5]
+// CHECK-FP: le      lr, #-3004  @ encoding: [0x0f,0xf0,0xdf,0xc5]
+le      lr, #-3004
+
+// CHECK: le      lr, #-3018  @ encoding: [0x0f,0xf0,0xe5,0xcd]
+// CHECK-FP: le      lr, #-3018  @ encoding: [0x0f,0xf0,0xe5,0xcd]
+le      lr, #-3018
+
+// CHECK: le      lr, #-304  @ encoding: [0x0f,0xf0,0x99,0xc0]
+// CHECK-FP: le      lr, #-304  @ encoding: [0x0f,0xf0,0x99,0xc0]
+le      lr, #-304
+
+// CHECK: le      lr, #-3098  @ encoding: [0x0f,0xf0,0x0d,0xce]
+// CHECK-FP: le      lr, #-3098  @ encoding: [0x0f,0xf0,0x0d,0xce]
+le      lr, #-3098
+
+// CHECK: le      lr, #-3228  @ encoding: [0x0f,0xf0,0x4f,0xc6]
+// CHECK-FP: le      lr, #-3228  @ encoding: [0x0f,0xf0,0x4f,0xc6]
+le      lr, #-3228
+
+// CHECK: le      lr, #-3316  @ encoding: [0x0f,0xf0,0x7b,0xc6]
+// CHECK-FP: le      lr, #-3316  @ encoding: [0x0f,0xf0,0x7b,0xc6]
+le      lr, #-3316
+
+// CHECK: le      lr, #-3332  @ encoding: [0x0f,0xf0,0x83,0xc6]
+// CHECK-FP: le      lr, #-3332  @ encoding: [0x0f,0xf0,0x83,0xc6]
+le      lr, #-3332
+
+// CHECK: le      lr, #-3354  @ encoding: [0x0f,0xf0,0x8d,0xce]
+// CHECK-FP: le      lr, #-3354  @ encoding: [0x0f,0xf0,0x8d,0xce]
+le      lr, #-3354
+
+// CHECK: le      lr, #-3962  @ encoding: [0x0f,0xf0,0xbd,0xcf]
+// CHECK-FP: le      lr, #-3962  @ encoding: [0x0f,0xf0,0xbd,0xcf]
+le      lr, #-3962
+
+// CHECK: le      lr, #-4042  @ encoding: [0x0f,0xf0,0xe5,0xcf]
+// CHECK-FP: le      lr, #-4042  @ encoding: [0x0f,0xf0,0xe5,0xcf]
+le      lr, #-4042
+
+// CHECK: le      lr, #-4052  @ encoding: [0x0f,0xf0,0xeb,0xc7]
+// CHECK-FP: le      lr, #-4052  @ encoding: [0x0f,0xf0,0xeb,0xc7]
+le      lr, #-4052
+
+// CHECK: le      lr, #-458  @ encoding: [0x0f,0xf0,0xe5,0xc8]
+// CHECK-FP: le      lr, #-458  @ encoding: [0x0f,0xf0,0xe5,0xc8]
+le      lr, #-458
+
+// CHECK: le      lr, #-56  @ encoding: [0x0f,0xf0,0x1d,0xc0]
+// CHECK-FP: le      lr, #-56  @ encoding: [0x0f,0xf0,0x1d,0xc0]
+le      lr, #-56
+
+// CHECK: le      lr, #-582  @ encoding: [0x0f,0xf0,0x23,0xc9]
+// CHECK-FP: le      lr, #-582  @ encoding: [0x0f,0xf0,0x23,0xc9]
+le      lr, #-582
+
+// CHECK: le      lr, #-676  @ encoding: [0x0f,0xf0,0x53,0xc1]
+// CHECK-FP: le      lr, #-676  @ encoding: [0x0f,0xf0,0x53,0xc1]
+le      lr, #-676
+
+// CHECK: le      lr, #-752  @ encoding: [0x0f,0xf0,0x79,0xc1]
+// CHECK-FP: le      lr, #-752  @ encoding: [0x0f,0xf0,0x79,0xc1]
+le      lr, #-752
+
+// CHECK: le      lr, #-76  @ encoding: [0x0f,0xf0,0x27,0xc0]
+// CHECK-FP: le      lr, #-76  @ encoding: [0x0f,0xf0,0x27,0xc0]
+le      lr, #-76
+
+// CHECK: le      lr, #-802  @ encoding: [0x0f,0xf0,0x91,0xc9]
+// CHECK-FP: le      lr, #-802  @ encoding: [0x0f,0xf0,0x91,0xc9]
+le      lr, #-802
+
+// CHECK: le      lr, #-862  @ encoding: [0x0f,0xf0,0xaf,0xc9]
+// CHECK-FP: le      lr, #-862  @ encoding: [0x0f,0xf0,0xaf,0xc9]
+le      lr, #-862
+
+// CHECK: le      lr, #-902  @ encoding: [0x0f,0xf0,0xc3,0xc9]
+// CHECK-FP: le      lr, #-902  @ encoding: [0x0f,0xf0,0xc3,0xc9]
+le      lr, #-902
+
+// CHECK: le      lr, #-968  @ encoding: [0x0f,0xf0,0xe5,0xc1]
+// CHECK-FP: le      lr, #-968  @ encoding: [0x0f,0xf0,0xe5,0xc1]
+le      lr, #-968
+
+// CHECK: wls     lr, lr, #1192  @ encoding: [0x4e,0xf0,0x55,0xc2]
+// CHECK-FP: wls     lr, lr, #1192  @ encoding: [0x4e,0xf0,0x55,0xc2]
+wls     lr, lr, #1192
+
+// CHECK: wls     lr, lr, #2134  @ encoding: [0x4e,0xf0,0x2b,0xcc]
+// CHECK-FP: wls     lr, lr, #2134  @ encoding: [0x4e,0xf0,0x2b,0xcc]
+wls     lr, lr, #2134
+
+// CHECK: wls     lr, lr, #962  @ encoding: [0x4e,0xf0,0xe1,0xc9]
+// CHECK-FP: wls     lr, lr, #962  @ encoding: [0x4e,0xf0,0xe1,0xc9]
+wls     lr, lr, #962
+
+// CHECK: wls     lr, r0, #1668  @ encoding: [0x40,0xf0,0x43,0xc3]
+// CHECK-FP: wls     lr, r0, #1668  @ encoding: [0x40,0xf0,0x43,0xc3]
+wls     lr, r0, #1668
+
+// CHECK: wls     lr, r0, #2706  @ encoding: [0x40,0xf0,0x49,0xcd]
+// CHECK-FP: wls     lr, r0, #2706  @ encoding: [0x40,0xf0,0x49,0xcd]
+wls     lr, r0, #2706
+
+// CHECK: wls     lr, r0, #3026  @ encoding: [0x40,0xf0,0xe9,0xcd]
+// CHECK-FP: wls     lr, r0, #3026  @ encoding: [0x40,0xf0,0xe9,0xcd]
+wls     lr, r0, #3026
+
+// CHECK: wls     lr, r0, #3436  @ encoding: [0x40,0xf0,0xb7,0xc6]
+// CHECK-FP: wls     lr, r0, #3436  @ encoding: [0x40,0xf0,0xb7,0xc6]
+wls     lr, r0, #3436
+
+// CHECK: wls     lr, r1, #1060  @ encoding: [0x41,0xf0,0x13,0xc2]
+// CHECK-FP: wls     lr, r1, #1060  @ encoding: [0x41,0xf0,0x13,0xc2]
+wls     lr, r1, #1060
+
+// CHECK: wls     lr, r1, #4036  @ encoding: [0x41,0xf0,0xe3,0xc7]
+// CHECK-FP: wls     lr, r1, #4036  @ encoding: [0x41,0xf0,0xe3,0xc7]
+wls     lr, r1, #4036
+
+// CHECK: wls     lr, r1, #538  @ encoding: [0x41,0xf0,0x0d,0xc9]
+// CHECK-FP: wls     lr, r1, #538  @ encoding: [0x41,0xf0,0x0d,0xc9]
+wls     lr, r1, #538
+
+// CHECK: wls     lr, r10, #1404  @ encoding: [0x4a,0xf0,0xbf,0xc2]
+// CHECK-FP: wls     lr, r10, #1404  @ encoding: [0x4a,0xf0,0xbf,0xc2]
+wls     lr, r10, #1404
+
+// CHECK: wls     lr, r10, #1408  @ encoding: [0x4a,0xf0,0xc1,0xc2]
+// CHECK-FP: wls     lr, r10, #1408  @ encoding: [0x4a,0xf0,0xc1,0xc2]
+wls     lr, r10, #1408
+
+// CHECK: wls     lr, r10, #2358  @ encoding: [0x4a,0xf0,0x9b,0xcc]
+// CHECK-FP: wls     lr, r10, #2358  @ encoding: [0x4a,0xf0,0x9b,0xcc]
+wls     lr, r10, #2358
+
+// CHECK: wls     lr, r10, #4086  @ encoding: [0x4a,0xf0,0xfb,0xcf]
+// CHECK-FP: wls     lr, r10, #4086  @ encoding: [0x4a,0xf0,0xfb,0xcf]
+wls     lr, r10, #4086
+
+// CHECK: wls     lr, r11, #1442  @ encoding: [0x4b,0xf0,0xd1,0xca]
+// CHECK-FP: wls     lr, r11, #1442  @ encoding: [0x4b,0xf0,0xd1,0xca]
+wls     lr, r11, #1442
+
+// CHECK: wls     lr, r11, #2678  @ encoding: [0x4b,0xf0,0x3b,0xcd]
+// CHECK-FP: wls     lr, r11, #2678  @ encoding: [0x4b,0xf0,0x3b,0xcd]
+wls     lr, r11, #2678
+
+// CHECK: wls     lr, r11, #3610  @ encoding: [0x4b,0xf0,0x0d,0xcf]
+// CHECK-FP: wls     lr, r11, #3610  @ encoding: [0x4b,0xf0,0x0d,0xcf]
+wls     lr, r11, #3610
+
+// CHECK: wls     lr, r12, #206  @ encoding: [0x4c,0xf0,0x67,0xc8]
+// CHECK-FP: wls     lr, r12, #206  @ encoding: [0x4c,0xf0,0x67,0xc8]
+wls     lr, r12, #206
+
+// CHECK: wls     lr, r12, #2896  @ encoding: [0x4c,0xf0,0xa9,0xc5]
+// CHECK-FP: wls     lr, r12, #2896  @ encoding: [0x4c,0xf0,0xa9,0xc5]
+wls     lr, r12, #2896
+
+// CHECK: wls     lr, r12, #3258  @ encoding: [0x4c,0xf0,0x5d,0xce]
+// CHECK-FP: wls     lr, r12, #3258  @ encoding: [0x4c,0xf0,0x5d,0xce]
+wls     lr, r12, #3258
+
+// CHECK: wls     lr, r2, #3242  @ encoding: [0x42,0xf0,0x55,0xce]
+// CHECK-FP: wls     lr, r2, #3242  @ encoding: [0x42,0xf0,0x55,0xce]
+wls     lr, r2, #3242
+
+// CHECK: wls     lr, r2, #3832  @ encoding: [0x42,0xf0,0x7d,0xc7]
+// CHECK-FP: wls     lr, r2, #3832  @ encoding: [0x42,0xf0,0x7d,0xc7]
+wls     lr, r2, #3832
+
+// CHECK: wls     lr, r2, #872  @ encoding: [0x42,0xf0,0xb5,0xc1]
+// CHECK-FP: wls     lr, r2, #872  @ encoding: [0x42,0xf0,0xb5,0xc1]
+wls     lr, r2, #872
+
+// CHECK: wls     lr, r3, #3514  @ encoding: [0x43,0xf0,0xdd,0xce]
+// CHECK-FP: wls     lr, r3, #3514  @ encoding: [0x43,0xf0,0xdd,0xce]
+wls     lr, r3, #3514
+
+// CHECK: wls     lr, r3, #3636  @ encoding: [0x43,0xf0,0x1b,0xc7]
+// CHECK-FP: wls     lr, r3, #3636  @ encoding: [0x43,0xf0,0x1b,0xc7]
+wls     lr, r3, #3636
+
+// CHECK: wls     lr, r3, #3942  @ encoding: [0x43,0xf0,0xb3,0xcf]
+// CHECK-FP: wls     lr, r3, #3942  @ encoding: [0x43,0xf0,0xb3,0xcf]
+wls     lr, r3, #3942
+
+// CHECK: wls     lr, r3, #712  @ encoding: [0x43,0xf0,0x65,0xc1]
+// CHECK-FP: wls     lr, r3, #712  @ encoding: [0x43,0xf0,0x65,0xc1]
+wls     lr, r3, #712
+
+// CHECK: wls     lr, r4, #2146  @ encoding: [0x44,0xf0,0x31,0xcc]
+// CHECK-FP: wls     lr, r4, #2146  @ encoding: [0x44,0xf0,0x31,0xcc]
+wls     lr, r4, #2146
+
+// CHECK: wls     lr, r4, #2486  @ encoding: [0x44,0xf0,0xdb,0xcc]
+// CHECK-FP: wls     lr, r4, #2486  @ encoding: [0x44,0xf0,0xdb,0xcc]
+wls     lr, r4, #2486
+
+// CHECK: wls     lr, r5, #1906  @ encoding: [0x45,0xf0,0xb9,0xcb]
+// CHECK-FP: wls     lr, r5, #1906  @ encoding: [0x45,0xf0,0xb9,0xcb]
+wls     lr, r5, #1906
+
+// CHECK: wls     lr, r5, #3396  @ encoding: [0x45,0xf0,0xa3,0xc6]
+// CHECK-FP: wls     lr, r5, #3396  @ encoding: [0x45,0xf0,0xa3,0xc6]
+wls     lr, r5, #3396
+
+// CHECK: wls     lr, r6, #3326  @ encoding: [0x46,0xf0,0x7f,0xce]
+// CHECK-FP: wls     lr, r6, #3326  @ encoding: [0x46,0xf0,0x7f,0xce]
+wls     lr, r6, #3326
+
+// CHECK: wls     lr, r6, #416  @ encoding: [0x46,0xf0,0xd1,0xc0]
+// CHECK-FP: wls     lr, r6, #416  @ encoding: [0x46,0xf0,0xd1,0xc0]
+wls     lr, r6, #416
+
+// CHECK: wls     lr, r6, #422  @ encoding: [0x46,0xf0,0xd3,0xc8]
+// CHECK-FP: wls     lr, r6, #422  @ encoding: [0x46,0xf0,0xd3,0xc8]
+wls     lr, r6, #422
+
+// CHECK: wls     lr, r7, #3474  @ encoding: [0x47,0xf0,0xc9,0xce]
+// CHECK-FP: wls     lr, r7, #3474  @ encoding: [0x47,0xf0,0xc9,0xce]
+wls     lr, r7, #3474
+
+// CHECK: wls     lr, r7, #3640  @ encoding: [0x47,0xf0,0x1d,0xc7]
+// CHECK-FP: wls     lr, r7, #3640  @ encoding: [0x47,0xf0,0x1d,0xc7]
+wls     lr, r7, #3640
+
+// CHECK: wls     lr, r8, #2700  @ encoding: [0x48,0xf0,0x47,0xc5]
+// CHECK-FP: wls     lr, r8, #2700  @ encoding: [0x48,0xf0,0x47,0xc5]
+wls     lr, r8, #2700
+
+// CHECK: wls     lr, r9, #1114  @ encoding: [0x49,0xf0,0x2d,0xca]
+// CHECK-FP: wls     lr, r9, #1114  @ encoding: [0x49,0xf0,0x2d,0xca]
+wls     lr, r9, #1114
+
+// CHECK: wls     lr, r9, #1984  @ encoding: [0x49,0xf0,0xe1,0xc3]
+// CHECK-FP: wls     lr, r9, #1984  @ encoding: [0x49,0xf0,0xe1,0xc3]
+wls     lr, r9, #1984
+
+// CHECK: wls     lr, r9, #3758  @ encoding: [0x49,0xf0,0x57,0xcf]
+// CHECK-FP: wls     lr, r9, #3758  @ encoding: [0x49,0xf0,0x57,0xcf]
+wls     lr, r9, #3758
+
+// CHECK: wls     lr, r9, #3796  @ encoding: [0x49,0xf0,0x6b,0xc7]
+// CHECK-FP: wls     lr, r9, #3796  @ encoding: [0x49,0xf0,0x6b,0xc7]
+wls     lr, r9, #3796
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+wls r10, r9, #2
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+wls lr, r9, #1
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+wls lr, r9, #-2
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop end is out of range or not a positive multiple of 2
+wls lr, r9, #4096
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+le lr, #-1
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+le lr, #2
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: loop start is out of range or not a negative multiple of 2
+le lr, #-4096
+
+// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction
+// ERROR-FP: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+le r10, #-4
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 s7, r8 @ encoding: [0x03,0xee,0x90,0x89]
+vmov.f16 s7, r8
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 s10, r5 @ encoding: [0x05,0xee,0x10,0x59]
+vmov.f16 s10, r5
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 s31, r10 @ encoding: [0x0f,0xee,0x90,0xa9]
+vmov.f16 s31, r10
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 r8, s7 @ encoding: [0x13,0xee,0x90,0x89]
+vmov.f16 r8, s7
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 r5, s10 @ encoding: [0x15,0xee,0x10,0x59]
+vmov.f16 r5, s10
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instruction requires: 16-bit fp registers
+# CHECK-FP: vmov.f16 r10, s31        @ encoding: [0x1f,0xee,0x90,0xa9]
+vmov.f16 r10, s31
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [r0, r12] or r14
+vmov.f16 sp, s10
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [r0, r12] or r14
+vmov.f16 s10, sp
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [s0, s31]
+vmov.f16 r10, d1
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [s0, s31]
+vmov.f16 r10, s32
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [s0, s31]
+vmov.f16 d1, r10
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR-FP: operand must be a register in range [s0, s31]
+vmov.f16 s32, r10
+
+# CHECK: cinc    lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+# CHECK-FP: cinc    lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+csinc   lr, r2, r2, hs
+
+# CHECK: cinc    lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+# CHECK-FP: cinc    lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+cinc    lr, r7, pl
+
+# CHECK: cinv    lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+# CHECK-FP: cinv    lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+cinv    lr, r12, hs
+
+# CHECK: cneg    lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+# CHECK-FP: cneg    lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+csneg   lr, r10, r10, lo
+
+# CHECK: csel    r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+# CHECK-FP: csel    r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+csel    r9, r9, r11, vc
+
+# CHECK: cset    lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+# CHECK-FP: cset    lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+cset    lr, eq
+
+# CHECK: csetm   lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+# CHECK-FP: csetm   lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+csetm   lr, hs
+
+# CHECK: csinc   lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+# CHECK-FP: csinc   lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+csinc   lr, r10, r7, le
+
+# CHECK: csinv   lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+# CHECK-FP: csinv   lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+csinv   lr, r5, zr, hs
+
+# CHECK: cinv    lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+# CHECK-FP: cinv    lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+csinv   lr, r2, r2, mi
+
+# CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
+# CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
+csel r0, r0, r1, eq
diff --git a/llvm/test/MC/ARM/vscclrm-asm.s b/llvm/test/MC/ARM/vscclrm-asm.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/vscclrm-asm.s
@@ -0,0 +1,39 @@
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK %s
+// RUN:   FileCheck --check-prefix=ERROR < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t
+// RUN: FileCheck --check-prefix=NOSEC < %t %s
+
+// CHECK: vscclrm            {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]
+// NOSEC: instruction requires: ARMv8-M Security Extensions
+vscclrm {s0-s3, vpr}
+
+// CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
+// NOSEC: instruction requires: ARMv8-M Security Extensions
+vscclrm {s3-s8, vpr}
+
+// CHECK: vscclrm            {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} @ encoding: [0x9f,0xec,0x0c,0x9a]
+vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
+
+// CHECK: vscclrm            {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]
+vscclrm {s31, vpr}
+
+// CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
+vscclrm {d0-d1, vpr}
+
+// CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
+vscclrm {d5-d7, vpr}
+
+// CHECK: it                 hi @ encoding: [0x88,0xbf]
+it hi
+// CHECK: vscclrmhi          {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} @ encoding: [0xdf,0xec,0x1d,0x1a]
+vscclrmhi {s3-s31, vpr}
+
+// ERROR: non-contiguous register range
+vscclrm {s0, s3-s4, vpr}
+
+// ERROR: register expected
+vscclrm {s32, vpr}
+
+// ERROR: invalid operand for instruction
+vscclrm {s0-s1}
diff --git a/llvm/test/MC/ARM/vstrldr_sys.s b/llvm/test/MC/ARM/vstrldr_sys.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/ARM/vstrldr_sys.s
@@ -0,0 +1,461 @@
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,+mve,+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK %s
+// RUN:   FileCheck --check-prefix=ERROR < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-vfp2,+mve,+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
+// RUN:   FileCheck --check-prefix=ERROR-NOVFP < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,-mve,+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
+// RUN:   FileCheck --check-prefix=ERROR-NOMVE < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,+mve,-8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
+// RUN:   FileCheck --check-prefix=ERROR-NOSEC < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-vfp2,-mve,-8msecext -show-encoding < %s 2>%t
+// RUN:   FileCheck --check-prefix=ERROR-NONE < %t %s
+// RUN: not llvm-mc -triple=thumbv8m.main-none-eabi -mattr=+vfp2,+8msecext -show-encoding < %s 2>%t
+// RUN:   FileCheck --check-prefix=ERROR-V8M < %t %s
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK-NOMVE: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK-NOVFP: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+vstr fpscr, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+// CHECK-NOMVE: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+// CHECK-NOVFP: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+// CHECK: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+vstr fpscr_nzcvqc, [r9, #-24]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+// CHECK-NOMVE: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+// CHECK-NOVFP: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+// CHECK: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+vstr fpscr_nzcvqc, [r9, #-24]!
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+// CHECK-NOMVE: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+// CHECK-NOVFP: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+// CHECK: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+vstr fpscr_nzcvqc, [r9], #-24
+
+// CHECK-NOSEC: it hi @ encoding: [0x88,0xbf]
+// CHECK-NOMVE: it hi @ encoding: [0x88,0xbf]
+// CHECK-NOVFP: it hi @ encoding: [0x88,0xbf]
+// CHECK: it hi @ encoding: [0x88,0xbf]
+it hi
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK-NOMVE: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK-NOVFP: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+// CHECK: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+vstrhi fpscr, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK-NOMVE: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK-NOVFP: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+vldr fpscr, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+// CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+// CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+// CHECK: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+vldr fpscr_nzcvqc, [r9, #-24]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+// CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+// CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+// CHECK: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+vldr fpscr_nzcvqc, [r9, #-24]!
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+// CHECK-NOMVE: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+// CHECK-NOVFP: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+// CHECK: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+vldr fpscr_nzcvqc, [r9], #-24
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+// CHECK-NOMVE: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+// CHECK-NOVFP: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+// CHECK: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+vldr fpscr_nzcvqc, [sp], #-52
+
+// CHECK-NOSEC: it hi @ encoding: [0x88,0xbf]
+// CHECK-NOMVE: it hi @ encoding: [0x88,0xbf]
+// CHECK-NOVFP: it hi @ encoding: [0x88,0xbf]
+// CHECK: it hi @ encoding: [0x88,0xbf]
+it hi
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: fp registers
+// CHECK-NOSEC: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK-NOMVE: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK-NOVFP: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+// CHECK: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+vldrhi fpscr, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+// CHECK-NOVFP: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+// CHECK: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+vstr fpcxts, [r12, #508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+// CHECK-NOVFP: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+// CHECK: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+vstr fpcxts, [r12, #508]!
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+// CHECK-NOVFP: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+// CHECK: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+vstr fpcxts, [r12], #508
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+// CHECK-NOVFP: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+// CHECK: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+vstr fpcxts, [sp], #-24
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+// CHECK-NOVFP: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+// CHECK: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+vldr fpcxts, [r12, #508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+// CHECK-NOVFP: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+// CHECK: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+vldr fpcxts, [r12, #508]!
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+// CHECK-NOVFP: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+// CHECK: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+vldr fpcxts, [r12], #508
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+// CHECK-NOVFP: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+// CHECK: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+vldr fpcxts, [sp], #-24
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+// CHECK: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+vstr fpcxtns, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+// CHECK: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+vstr fpcxtns, [r9, #-24]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+// CHECK: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+vstr fpcxtns, [r6, #500]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+// CHECK: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+vstr fpcxtns, [lr, #-508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+// CHECK: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+vstr fpcxtns, [r12, #508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+// CHECK-NOVFP: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+// CHECK: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+vstr fpcxtns, [sp], #-24
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+// CHECK: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+vldr fpcxtns, [r0]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+// CHECK: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+vldr fpcxtns, [r9, #-24]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+// CHECK: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+vldr fpcxtns, [r6, #500]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+// CHECK: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+vldr fpcxtns, [lr, #-508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+// CHECK: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+vldr fpcxtns, [r12, #508]
+
+// ERROR-V8M: instruction requires: armv8.1m.main
+// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
+// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
+// CHECK-NOMVE: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+// CHECK-NOVFP: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+// CHECK: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+vldr fpcxtns, [sp], #-24
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+// CHECK: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+vstr vpr, [r6, #500]
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+// CHECK: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+vstr p0, [lr, #-508]
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+// CHECK: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+vstr vpr, [r6, #500]!
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+// CHECK: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+vstr p0, [lr, #-508]!
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+// CHECK: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+vstr vpr, [r6], #500
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+// CHECK: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+vstr p0, [lr], #-508
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+// CHECK: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+vstr p0, [sp], #-24
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+// CHECK: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+vldr vpr, [r6, #500]
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+// CHECK: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+vldr p0, [lr, #-508]
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+// CHECK: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+vldr vpr, [r6, #500]!
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+// CHECK: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+vldr p0, [lr, #-508]!
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+// CHECK: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+vldr vpr, [r6], #500
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+// CHECK: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+vldr p0, [lr], #-508
+
+// ERROR-V8M: instruction requires: mve armv8.1m.main
+// ERROR-NONE: instruction requires: mve
+// CHECK-NOSEC: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+// ERROR-NOMVE: instruction requires: mve
+// CHECK-NOVFP: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+// CHECK: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+vldr p0, [sp], #-24
+
+// ERROR-NOSEC: invalid instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpcxtns, [pc, #4]!
+
+// ERROR-NOSEC: invalid instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vstr fpcxtns, [r0, #-507]
+
+// ERROR-NOSEC: invalid instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpcxtns, [r2, #512]
+
+// ERROR-NOSEC: invalid instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpcxtns, [pc], #-24
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vstr vpr, [r0, #-507]
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr p0, [r2, #512]
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr p0, [r2, #2]
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr p0, [pc], #4
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpscr, [pc, #4]!
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpscr_nzcvqc, [r8], #-53
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr fpscr_nzcvqc, [r8], #2
+
+// ERROR-NOSEC: invalid operand for instruction
+// ERROR-NOMVE: invalid operand for instruction
+// ERROR-NOVFP: invalid operand for instruction
+// ERROR: invalid operand for instruction
+vldr  fpscr_nzcvqc, [pc], #-52
+
diff --git a/llvm/test/MC/Disassembler/ARM/clrm.txt b/llvm/test/MC/Disassembler/ARM/clrm.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/clrm.txt
@@ -0,0 +1,20 @@
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+
+[0x9f,0xe8,0x0f,0x00]
+# CHECK: clrm {r0, r1, r2, r3} @ encoding: [0x9f,0xe8,0x0f,0x00]
+
+[0x9f,0xe8,0xff,0xdf]
+# CHECK: clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} @ encoding: [0x9f,0xe8,0xff,0xdf]
+
+[0x9f,0xe8,0x00,0x10]
+# CHECK: clrm {r12} @ encoding: [0x9f,0xe8,0x00,0x10]
+
+[0x9f,0xe8,0x00,0x40]
+# CHECK: clrm {lr} @ encoding: [0x9f,0xe8,0x00,0x40]
+
+[0x9f,0xe8,0x00,0x80]
+# CHECK: clrm {apsr} @ encoding: [0x9f,0xe8,0x00,0x80]
+
+[0x9f,0xe8,0x00,0x00]
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/ARM/mve.s b/llvm/test/MC/Disassembler/ARM/mve.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/mve.s
@@ -0,0 +1,4557 @@
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+[0x50 0xea 0xef 0x51]
+# CHECK: asrl r0, r1, #23 @ encoding: [0x50,0xea,0xef,0x51]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction 
+
+[0x5e 0xea 0xef 0x61]
+# CHECK: asrl lr, r1, #27 @ encoding: [0x5e,0xea,0xef,0x61]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x50 0xea 0x2d 0x41]
+# CHECK: asrl r0, r1, r4 @ encoding: [0x50,0xea,0x2d,0x41]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xcf 0x21]
+# CHECK: lsll    lr, r1, #11  @ encoding: [0x5e,0xea,0xcf,0x21]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x0d 0x41]
+# CHECK: lsll    lr, r1, r4  @ encoding: [0x5e,0xea,0x0d,0x41]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x1f 0x31]
+# CHECK: lsrl    lr, r1, #12  @ encoding: [0x5e,0xea,0x1f,0x31]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0x2d 0x83]
+# CHECK: sqrshrl lr, r3, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x7f 0x4f]
+# CHECK: sqshl   lr, #17  @ encoding: [0x5e,0xea,0x7f,0x4f]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0x3f 0x7b]
+# CHECK: sqshll  lr, r11, #28  @ encoding: [0x5f,0xea,0x3f,0x7b]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xef 0x2f]
+# CHECK: srshr   lr, #11  @ encoding: [0x5e,0xea,0xef,0x2f]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0xef 0x5b]
+# CHECK: srshrl  lr, r11, #23  @ encoding: [0x5f,0xea,0xef,0x5b]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x2d 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x5b 0xea 0x2d 0xcf]
+# CHECK: sqrshr  r11, r12  @ encoding: [0x5b,0xea,0x2d,0xcf]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x5e 0xea 0x0d 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x5b 0xea 0x0d 0xcf]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x5f 0xea 0x0d 0x41]
+# CHECK: uqrshll lr, r1, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x50 0xea 0x4f 0x0f]
+# CHECK: uqshl   r0, #1  @ encoding: [0x50,0xea,0x4f,0x0f]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0xcf 0x17]
+# CHECK: uqshll  lr, r7, #7  @ encoding: [0x5f,0xea,0xcf,0x17]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x50 0xea 0x9f 0x2f]
+# CHECK: urshr   r0, #10  @ encoding: [0x50,0xea,0x9f,0x2f]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x51 0xea 0x5f 0x79]
+# CHECK: urshrl  r0, r9, #29  @ encoding: [0x51,0xea,0x5f,0x79]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x82 0xee 0x07 0x0f]
+# CHECK: vabav.s8  r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x92 0xee 0x07 0x0f]
+# CHECK: vabav.s16 r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0xa2 0xee 0x07 0x0f]
+# CHECK: vabav.s32 r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x82 0xfe 0x07 0x0f]
+# CHECK: vabav.u8 r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x92 0xfe 0x07 0x0f]
+# CHECK: vabav.u16  r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0xa2 0xfe 0x07 0x0f]
+# CHECK: vabav.u32  r0, q1, q3
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vabavt.s16 lr, q3, q4  @ encoding: [0x96,0xee,0x09,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vabave.s16 lr, q3, q4  @ encoding: [0x96,0xee,0x09,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0x96,0xee,0x09,0xef]
+[0x96,0xee,0x09,0xef]
+
+# CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x00,0xef]
+
+# CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xf5,0xee,0x20,0xef]
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc9,0xee,0x04,0x0f]
+
+# CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xfe,0x02,0x0f]
+
+# CHECK: vminnmv.f16 lr, q3  @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x86,0xef]
+
+# CHECK: vminnmv.f32 lr, q1  @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x82,0xef]
+
+# CHECK: vminnmav.f16 lr, q0  @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xfe,0x80,0xef]
+
+# CHECK: vminnmav.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0    @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vminnmavt.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vminnmave.f32 lr, q3  @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xec,0xee,0x86,0xef]
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x80,0xef]
+
+# CHECK: vminv.s16 lr, q0  @ encoding: [0xe6,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x80,0xef]
+
+# CHECK: vminv.s32 lr, q2  @ encoding: [0xea,0xee,0x84,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x84,0xef]
+
+# CHECK: vminv.u8 r0, q0  @ encoding: [0xe2,0xfe,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x80,0x0f]
+
+# CHECK: vminv.u32 r10, q3  @ encoding: [0xea,0xfe,0x86,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x86,0xaf]
+
+# CHECK: vminav.s16 r0, q0  @ encoding: [0xe4,0xee,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x80,0x0f]
+
+# CHECK: vminav.s8 r0, q1  @ encoding: [0xe0,0xee,0x82,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x82,0x0f]
+
+# CHECK: vminav.s32 lr, q1  @ encoding: [0xe8,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x82,0xef]
+
+# CHECK: vmaxnmv.f16 lr, q1  @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x02,0xef]
+
+# CHECK: vmaxnmv.f32 r10, q1  @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x02,0xaf]
+
+# CHECK: vmaxv.s8 lr, q4  @ encoding: [0xe2,0xee,0x08,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x08,0xef]
+
+# CHECK: vmaxv.s16 lr, q0  @ encoding: [0xe6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x00,0xef]
+
+# CHECK: vmaxv.s32 r1, q1  @ encoding: [0xea,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x02,0x1f]
+
+# CHECK: vmaxv.u8 r0, q4  @ encoding: [0xe2,0xfe,0x08,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x08,0x0f]
+
+# CHECK: vmaxv.u16 r0, q1  @ encoding: [0xe6,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xfe,0x02,0x0f]
+
+# CHECK: vmaxv.u32 r1, q0  @ encoding: [0xea,0xfe,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x00,0x1f]
+
+# CHECK: vmaxav.s8 lr, q6  @ encoding: [0xe0,0xee,0x0c,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x0c,0xef]
+
+# CHECK: vmaxav.s16 r0, q6  @ encoding: [0xe4,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x0c,0x0f]
+
+# CHECK: vmaxav.s32 r10, q7  @ encoding: [0xe8,0xee,0x0e,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x0e,0xaf]
+
+# CHECK: vmlav.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0xee]
+
+# CHECK: vmlav.s32 lr, q0, q4  @ encoding: [0xf1,0xee,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xee,0x08,0xee]
+
+# CHECK: vmlav.u16 lr, q0, q7  @ encoding: [0xf0,0xfe,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xfe,0x0e,0xee]
+
+# CHECK: vmlav.u32 lr, q0, q0  @ encoding: [0xf1,0xfe,0x00,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xfe,0x00,0xee]
+
+# CHECK: vmlava.s16 lr, q0, q4  @ encoding: [0xf0,0xee,0x28,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x28,0xee]
+
+# CHECK: vmladavx.s16 r0, q0, q7  @ encoding: [0xf0,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0x1e]
+
+# CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x2e,0xfe]
+
+# CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf6,0xee,0x00,0xef]
+
+# CHECK: vmlav.u8 lr, q1, q7  @ encoding: [0xf2,0xfe,0x0e,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf2,0xfe,0x0e,0xef]
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2  @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xee,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x86,0xee,0x20,0xff]
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1  @ encoding: [0x8e,0xfe,0x22,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xfe,0x22,0xef]
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1  @ encoding: [0x88,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1  @ encoding: [0xd9,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xd9,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6  @ encoding: [0x8f,0xee,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0x0c,0x0e]
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4  @ encoding: [0xda,0xfe,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xda,0xfe,0x08,0xee]
+
+# CHECK: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x58,0x0f]
+
+# CHECK: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xff,0x52,0x6f]
+
+# CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x5e,0x66]
+
+# CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x54,0x06]
+
+# CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xef,0x54,0x06]
+
+# CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x54,0x06]
+
+# CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x54,0x06]
+
+# CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x54,0x06]
+
+# CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x4e,0x66]
+
+# CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x44,0x06]
+
+# CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xef,0x44,0x06]
+
+# CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x44,0x06]
+
+# CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x44,0x06]
+
+# CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x44,0x06]
+
+# CHECK: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0xce,0x0f]
+
+# CHECK: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0x4c,0x0f]
+
+# CHECK: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0x48,0x1f]
+
+# CHECK: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xfe,0x40,0x0f]
+
+# CHECK: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xfe,0x44,0x1f]
+
+# CHECK: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfe,0x40,0x2f]
+
+# CHECK: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfe,0x44,0x1f]
+
+# CHECK: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x05,0x0e]
+
+# CHECK: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x0b,0x3e]
+
+# CHECK: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xaf,0xee,0x40,0x0f]
+
+# CHECK: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x03,0x2e]
+
+# CHECK: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x01,0x1e]
+
+# CHECK: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xab,0xfe,0x40,0x0f]
+
+# CHECK: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x0b,0x0e]
+
+# CHECK: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x07,0x1e]
+
+# CHECK: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x01,0x1e]
+
+# CHECK: vshllt.s16 q0, q0, #14  @ encoding: [0xbe,0xee,0x40,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbe,0xee,0x40,0x1f]
+
+# CHECK: vshllt.s16 q0, q0, #11  @ encoding: [0xbb,0xee,0x40,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xee,0x40,0x1f]
+
+# CHECK: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfe,0x44,0x0f]
+
+# CHECK: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xfe,0xc7,0x0f]
+
+# CHECK: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xfe,0xc5,0x1f]
+
+# CHECK: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0xc9,0x0f]
+
+# CHECK: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0xc5,0x1f]
+
+# CHECK: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0xc5,0x2f]
+
+# CHECK: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0xc3,0x1f]
+
+# CHECK: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xee,0xc1,0x0f]
+
+# CHECK: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xee,0xc5,0x1f]
+
+# CHECK: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xfe,0xc4,0x0f]
+
+# CHECK: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0xc0,0x1f]
+
+# CHECK: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0xc2,0x1f]
+
+# CHECK: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x93,0xfe,0xce,0x0f]
+
+# CHECK: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xee,0xce,0x0f]
+
+# CHECK: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xee,0xc2,0x1f]
+
+# CHECK: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xee,0xcc,0x0f]
+
+# CHECK: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x96,0xee,0xc4,0x1f]
+
+# CHECK: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xee,0x4f,0x0f]
+
+# CHECK: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xfe,0x47,0x3f]
+
+# CHECK: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x43,0x0f]
+
+# CHECK: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x95,0xee,0x43,0x1f]
+
+# CHECK: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xee,0x4c,0x0f]
+
+# CHECK: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xee,0x42,0x1f]
+
+# CHECK: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xfe,0x46,0x0f]
+
+# CHECK: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xfe,0x44,0x1f]
+
+# CHECK: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9d,0xee,0x48,0x3f]
+
+# CHECK: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfe,0x44,0x0f]
+
+# CHECK: vbic q0, q1, q7  @ encoding: [0x12,0xef,0x5e,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x5e,0x01]
+
+# CHECK: vrev64.8 q0, q4  @ encoding: [0xb0,0xff,0x48,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x48,0x00]
+
+# CHECK: vrev64.16 q1, q3  @ encoding: [0xb4,0xff,0x46,0x20]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x46,0x20]
+
+# CHECK: vrev64.32 q0, q2  @ encoding: [0xb8,0xff,0x44,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x44,0x00]
+
+# CHECK: vrev32.8 q0, q1  @ encoding: [0xb0,0xff,0xc2,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xc2,0x00]
+
+# CHECK: vrev32.16 q0, q5  @ encoding: [0xb4,0xff,0xca,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xca,0x00]
+
+# CHECK: vrev16.8 q0, q2  @ encoding: [0xb0,0xff,0x44,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x44,0x01]
+
+# CHECK: vmvn q0, q2  @ encoding: [0xb0,0xff,0xc4,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xc4,0x05]
+
+# CHECK: veor q2, q1, q7  @ encoding: [0x02,0xff,0x5e,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x5e,0x41]
+
+# CHECK: vorn q0, q3, q2  @ encoding: [0x36,0xef,0x54,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xef,0x54,0x01]
+
+# CHECK: vorr q1, q2, q1  @ encoding: [0x24,0xef,0x52,0x21]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xef,0x52,0x21]
+
+# CHECK: vand q0, q2, q0  @ encoding: [0x04,0xef,0x50,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xef,0x50,0x01]
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x56,0x09]
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x56,0xc9]
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x5c,0xe9]
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xff,0x4a,0x0b]
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xff,0x44,0x2b]
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xff,0x40,0x0b]
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x4a,0x0b]
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xef,0x40,0xcb]
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0xab]
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x4a,0x68]
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xff,0x4c,0x08]
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xff,0x4c,0x08]
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xef,0x44,0x08]
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x42,0x48]
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0x08]
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x50,0x22]
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xef,0x52,0x02]
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x5a,0x02]
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x5c,0x02]
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x52,0x02]
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x5e,0x22]
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x5c,0x00]
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x5a,0x00]
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x58,0x00]
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x54,0x00]
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x5c,0x80]
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x54,0x00]
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x07]
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x48,0x27]
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x44,0x47]
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xff,0x48,0x27]
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x44,0x07]
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xff,0x48,0x07]
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xef,0x42,0x01]
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x40,0x01]
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xef,0x42,0x01]
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x4c,0x21]
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xff,0x4a,0x41]
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xff,0x40,0x41]
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x02]
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xef,0x42,0x22]
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xef,0x4a,0x02]
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x44,0x02]
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x4a,0x02]
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xff,0x48,0x42]
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xef,0x40,0x00]
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x44,0x80]
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x42,0x00]
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x46,0x60]
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x46,0x00]
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x46,0x00]
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x10,0x8b]
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xae,0xee,0x30,0xeb]
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xee,0x10,0x9b]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xa0,0xee,0x30,0x1b]
+[0xa0,0xee,0x30,0x1b]
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x42,0x44]
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x48,0x04]
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x40,0x04]
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xce,0x04]
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xce,0x84]
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xca,0xe4]
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0xc0,0x23]
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0xc2,0x03]
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0xc4,0xe3]
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0x42,0x23]
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0x44,0x03]
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0x4e,0x03]
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xc0,0x07]
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xc4,0xc7]
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xc4,0xe7]
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x48,0x47]
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x44,0x07]
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x4a,0x07]
+
+# CHECK: vrintn.f16 q1, q0  @ encoding: [0xb6,0xff,0x40,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0x40,0x24]
+
+# CHECK: vrintn.f32 q0, q4  @ encoding: [0xba,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0x48,0x04]
+
+# CHECK: vrinta.f16 q0, q1  @ encoding: [0xb6,0xff,0x42,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0x42,0x05]
+
+# CHECK: vrinta.f32 q1, q3  @ encoding: [0xba,0xff,0x46,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0x46,0x25]
+
+# CHECK: vrintm.f16 q0, q5  @ encoding: [0xb6,0xff,0xca,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0xca,0x06]
+
+# CHECK: vrintm.f32 q0, q4  @ encoding: [0xba,0xff,0xc8,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0xc8,0x06]
+
+# CHECK: vrintp.f16 q1, q0  @ encoding: [0xb6,0xff,0xc0,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0xc0,0x27]
+
+# CHECK: vrintp.f32 q0, q1  @ encoding: [0xba,0xff,0xc2,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0xc2,0x07]
+
+# CHECK: vrintx.f16 q1, q2  @ encoding: [0xb6,0xff,0xc4,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0xc4,0x24]
+
+# CHECK: vrintx.f32 q1, q1  @ encoding: [0xba,0xff,0xc2,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0xc2,0x24]
+
+# CHECK: vrintz.f16 q1, q6  @ encoding: [0xb6,0xff,0xcc,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xff,0xcc,0x25]
+
+# CHECK: vrintz.f32 q1, q0  @ encoding: [0xba,0xff,0xc0,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0xc0,0x25]
+
+# CHECK: vmul.f16 q2, q1, q3  @ encoding: [0x12,0xff,0x56,0x4d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x56,0x4d]
+
+# CHECK: vmul.f32 q0, q0, q5  @ encoding: [0x00,0xff,0x5a,0x0d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x5a,0x0d]
+
+# CHECK: vfma.f16 q0, q2, q3  @ encoding: [0x14,0xef,0x56,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x56,0x0c]
+
+# CHECK: vfma.f32 q0, q3, q7  @ encoding: [0x06,0xef,0x5e,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xef,0x5e,0x0c]
+
+# CHECK: vfms.f16 q0, q2, q5  @ encoding: [0x34,0xef,0x5a,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xef,0x5a,0x0c]
+
+# CHECK: vfms.f32 q1, q1, q2  @ encoding: [0x22,0xef,0x54,0x2c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xef,0x54,0x2c]
+
+# CHECK: vadd.f16 q0, q0, q5  @ encoding: [0x10,0xef,0x4a,0x0d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x4a,0x0d]
+
+# CHECK: vadd.f32 q1, q3, q0  @ encoding: [0x06,0xef,0x40,0x2d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xef,0x40,0x2d]
+
+# CHECK: vcadd.f16 q2, q1, q7, #90  @ encoding: [0x82,0xfc,0x4e,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfc,0x4e,0x48]
+
+# CHECK: vcadd.f16 q2, q5, q7, #270  @ encoding: [0x8a,0xfd,0x4e,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfd,0x4e,0x48]
+
+# CHECK: vcadd.f32 q0, q4, q7, #90  @ encoding: [0x98,0xfc,0x4e,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfc,0x4e,0x08]
+
+# CHECK: vcadd.f32 q2, q2, q3, #270  @ encoding: [0x94,0xfd,0x46,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xfd,0x46,0x48]
+
+# CHECK: vabd.f16 q0, q0, q6  @ encoding: [0x30,0xff,0x4c,0x0d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xff,0x4c,0x0d]
+
+# CHECK: vabd.f32 q0, q1, q4  @ encoding: [0x22,0xff,0x48,0x0d]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x48,0x0d]
+
+# CHECK: vcvta.s16.f16 q0, q7  @ encoding: [0xb7,0xff,0x4e,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb7,0xff,0x4e,0x00]
+
+# CHECK: vcvtn.u32.f32 q7, q6  @ encoding: [0xbb,0xff,0xcc,0xe1]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0xcc,0xe1]
+
+# CHECK: vcvtp.s32.f32 q0, q7  @ encoding: [0xbb,0xff,0x4e,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0x4e,0x02]
+
+# CHECK: vcvtm.u32.f32 q1, q4  @ encoding: [0xbb,0xff,0xc8,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0xc8,0x23]
+
+# CHECK: vneg.f16 q0, q7  @ encoding: [0xb5,0xff,0xce,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0xce,0x07]
+
+# CHECK: vneg.f32 q0, q2  @ encoding: [0xb9,0xff,0xc4,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0xc4,0x07]
+
+# CHECK: vabs.f16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0x44,0x07]
+
+# CHECK: vabs.f32 q0, q0  @ encoding: [0xb9,0xff,0x40,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0x40,0x07]
+
+# CHECK: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x4c,0xc4]
+
+# CHECK: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x48,0x04]
+
+# CHECK: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x42,0x24]
+
+# CHECK: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x4e,0x24]
+
+# CHECK: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xff,0x48,0x04]
+
+# CHECK: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x44,0x44]
+
+# CHECK: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x52,0x04]
+
+# CHECK: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xef,0x56,0x84]
+
+# CHECK: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x5a,0x04]
+
+# CHECK: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xff,0x50,0x04]
+
+# CHECK: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xff,0x5a,0x04]
+
+# CHECK: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x50,0x24]
+
+# CHECK: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xef,0x5c,0x25]
+
+# CHECK: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xef,0x58,0x45]
+
+# CHECK: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x50,0x05]
+
+# CHECK: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x54,0x05]
+
+# CHECK: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xff,0x5c,0x25]
+
+# CHECK: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xff,0x50,0x05]
+
+# CHECK: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x4c,0x05]
+
+# CHECK: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xef,0x48,0x25]
+
+# CHECK: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xef,0x48,0x25]
+
+# CHECK: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xff,0x46,0x05]
+
+# CHECK: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xff,0x4c,0xa5]
+
+# CHECK: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xff,0x4e,0x25]
+
+# CHECK: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xff,0x54,0x04]
+
+# CHECK: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xff,0x54,0x04]
+
+# CHECK: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0x52,0x04]
+
+# CHECK: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xff,0x56,0x05]
+
+# CHECK: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xff,0x52,0x05]
+
+# CHECK: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xff,0x52,0x05]
+
+# CHECK: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xef,0x58,0x07]
+
+# CHECK: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xff,0x5c,0x07]
+
+# CHECK: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x95,0xef,0x54,0x27]
+
+# CHECK: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x93,0xff,0x5a,0x07]
+
+# CHECK: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbd,0xef,0x56,0x27]
+
+# CHECK: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb3,0xff,0x54,0x07]
+
+# CHECK: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xff,0x52,0x06]
+
+# CHECK: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xff,0x52,0x46]
+
+# CHECK: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0x58,0x06]
+
+# CHECK: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xef,0x56,0x22]
+
+# CHECK: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xff,0x56,0x22]
+
+# CHECK: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x96,0xef,0x52,0x02]
+
+# CHECK: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xff,0x5a,0x02]
+
+# CHECK: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa9,0xef,0x5a,0x02]
+
+# CHECK: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xff,0x52,0x02]
+
+# CHECK: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xef,0x5e,0x00]
+
+# CHECK: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xff,0x54,0x00]
+
+# CHECK: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xef,0x56,0x00]
+
+# CHECK: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xff,0x5c,0xe0]
+
+# CHECK: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xef,0x5c,0x00]
+
+# CHECK: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xff,0x5a,0x40]
+
+# CHECK: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xef,0x5c,0x05]
+
+# CHECK: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xef,0x50,0x25]
+
+# CHECK: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xef,0x54,0x45]
+
+# CHECK: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x05,0x0f]
+
+# CHECK: vcmp.f16 eq, q0, q4  @ encoding: [0x31,0xfe,0x08,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x08,0x0f]
+
+# CHECK: vcmp.f16 ne, q2, q7  @ encoding: [0x35,0xfe,0x8e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x8e,0x0f]
+
+# CHECK: vcmp.f16 ge, q0, q0  @ encoding: [0x31,0xfe,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x00,0x1f]
+
+# CHECK: vcmp.f16 lt, q0, q1  @ encoding: [0x31,0xfe,0x82,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x82,0x1f]
+
+# CHECK: vcmp.f16 gt, q1, q4  @ encoding: [0x33,0xfe,0x09,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x09,0x1f]
+
+# CHECK: vcmp.f16 le, q2, q6  @ encoding: [0x35,0xfe,0x8d,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x8d,0x1f]
+
+# CHECK: vcmp.f32 eq, q2, q5  @ encoding: [0x35,0xee,0x0a,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x0a,0x0f]
+
+# CHECK: vcmp.f32 ne, q3, q4  @ encoding: [0x37,0xee,0x88,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x88,0x0f]
+
+# CHECK: vcmp.f32 ge, q0, q7  @ encoding: [0x31,0xee,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x0e,0x1f]
+
+# CHECK: vcmp.f32 lt, q5, q2  @ encoding: [0x3b,0xee,0x84,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x84,0x1f]
+
+# CHECK: vcmp.f32 gt, q2, q7  @ encoding: [0x35,0xee,0x0f,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x0f,0x1f]
+
+# CHECK: vcmp.f32 le, q2, q4  @ encoding: [0x35,0xee,0x89,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x89,0x1f]
+
+# CHECK: vcmp.i8 eq, q4, q6  @ encoding: [0x09,0xfe,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xfe,0x0c,0x0f]
+
+# CHECK: vcmp.i8 ne, q2, q2  @ encoding: [0x05,0xfe,0x84,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xfe,0x84,0x0f]
+
+# CHECK: vcmp.s8 ge, q0, q0  @ encoding: [0x01,0xfe,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xfe,0x00,0x1f]
+
+# CHECK: vcmp.s8 lt, q2, q7  @ encoding: [0x05,0xfe,0x8e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xfe,0x8e,0x1f]
+
+# CHECK: vcmp.s8 gt, q4, q3  @ encoding: [0x09,0xfe,0x07,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xfe,0x07,0x1f]
+
+# CHECK: vcmp.s8 le, q7, q3  @ encoding: [0x0f,0xfe,0x87,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xfe,0x87,0x1f]
+
+# CHECK: vcmp.u8 hi, q1, q4  @ encoding: [0x03,0xfe,0x89,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xfe,0x89,0x0f]
+
+# CHECK: vcmp.u8 cs, q1, q4  @ encoding: [0x03,0xfe,0x09,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xfe,0x09,0x0f]
+
+# CHECK: vcmp.i16 eq, q4, q7  @ encoding: [0x19,0xfe,0x0e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xfe,0x0e,0x0f]
+
+# CHECK: vcmp.i16 ne, q2, q1  @ encoding: [0x15,0xfe,0x82,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xfe,0x82,0x0f]
+
+# CHECK: vcmp.s16 ge, q1, q7  @ encoding: [0x13,0xfe,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x0e,0x1f]
+
+# CHECK: vcmp.s16 lt, q0, q1  @ encoding: [0x11,0xfe,0x82,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x82,0x1f]
+
+# CHECK: vcmp.s16 gt, q1, q7  @ encoding: [0x13,0xfe,0x0f,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x0f,0x1f]
+
+# CHECK: vcmp.s16 le, q2, q1  @ encoding: [0x15,0xfe,0x83,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xfe,0x83,0x1f]
+
+# CHECK: vcmp.u16 hi, q1, q4  @ encoding: [0x13,0xfe,0x89,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x89,0x0f]
+
+# CHECK: vcmp.u16 cs, q1, q4  @ encoding: [0x13,0xfe,0x09,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x09,0x0f]
+
+# CHECK: vcmp.i32 eq, q2, q7  @ encoding: [0x25,0xfe,0x0e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x0e,0x0f]
+
+# CHECK: vcmp.i32 ne, q2, q4  @ encoding: [0x25,0xfe,0x88,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x88,0x0f]
+
+# CHECK: vcmp.s32 ge, q5, q5  @ encoding: [0x2b,0xfe,0x0a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xfe,0x0a,0x1f]
+
+# CHECK: vcmp.s32 lt, q2, q2  @ encoding: [0x25,0xfe,0x84,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x84,0x1f]
+
+# CHECK: vcmp.s32 gt, q0, q1  @ encoding: [0x21,0xfe,0x03,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xfe,0x03,0x1f]
+
+# CHECK: vcmp.s32 le, q5, q4  @ encoding: [0x2b,0xfe,0x89,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xfe,0x89,0x1f]
+
+# CHECK: vcmp.u32 hi, q1, q4  @ encoding: [0x23,0xfe,0x89,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x89,0x0f]
+
+# CHECK: vcmp.u32 cs, q1, q4  @ encoding: [0x23,0xfe,0x09,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x09,0x0f]
+
+# CHECK: vcmp.f16 gt, q4, zr  @ encoding: [0x39,0xfe,0x6f,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0x6f,0x1f]
+
+# CHECK: vqdmladhx.s8 q1, q6, q6  @ encoding: [0x0c,0xee,0x0c,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x0c,0x3e]
+
+# CHECK: vqdmladhx.s16 q0, q1, q4  @ encoding: [0x12,0xee,0x08,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x08,0x1e]
+
+# CHECK: vqdmladhx.s32 q0, q3, q7  @ encoding: [0x26,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xee,0x0e,0x1e]
+
+# CHECK: vqdmladh.s8 q0, q1, q1  @ encoding: [0x02,0xee,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xee,0x02,0x0e]
+
+# CHECK: vqdmladh.s16 q0, q2, q2  @ encoding: [0x14,0xee,0x04,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x04,0x0e]
+
+# CHECK: vqdmladh.s32 q1, q5, q7  @ encoding: [0x2a,0xee,0x0e,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x0e,0x2e]
+
+# CHECK: vqrdmladhx.s8 q0, q7, q0  @ encoding: [0x0e,0xee,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x01,0x1e]
+
+# CHECK: vqrdmladhx.s16 q0, q0, q1  @ encoding: [0x10,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x03,0x1e]
+
+# CHECK: vqrdmladhx.s32 q1, q0, q4  @ encoding: [0x20,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x09,0x3e]
+
+# CHECK: vqrdmladh.s8 q0, q6, q2  @ encoding: [0x0c,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x05,0x0e]
+
+# CHECK: vqrdmladh.s16 q1, q5, q4  @ encoding: [0x1a,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x09,0x2e]
+
+# CHECK: vqrdmladh.s32 q0, q2, q2  @ encoding: [0x24,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x05,0x0e]
+
+# CHECK: vqdmlsdhx.s8 q1, q4, q7  @ encoding: [0x08,0xfe,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x0e,0x3e]
+
+# CHECK: vqdmlsdhx.s16 q0, q2, q5  @ encoding: [0x14,0xfe,0x0a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x0a,0x1e]
+
+# CHECK: vqdmlsdhx.s32 q3, q4, q6  @ encoding: [0x28,0xfe,0x0c,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x0c,0x7e]
+
+# CHECK: vqdmlsdh.s8 q0, q3, q6  @ encoding: [0x06,0xfe,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x0c,0x0e]
+
+# CHECK: vqdmlsdh.s16 q0, q4, q1  @ encoding: [0x18,0xfe,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x02,0x0e]
+
+# CHECK: vqdmlsdh.s32 q2, q5, q0  @ encoding: [0x2a,0xfe,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0x4e]
+
+# CHECK: vqrdmlsdhx.s8 q0, q3, q1  @ encoding: [0x06,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x03,0x1e]
+
+# CHECK: vqrdmlsdhx.s16 q0, q1, q4  @ encoding: [0x12,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfe,0x09,0x1e]
+
+# CHECK: vqrdmlsdhx.s32 q1, q6, q3  @ encoding: [0x2c,0xfe,0x07,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x07,0x3e]
+
+# CHECK: vqrdmlsdh.s8 q3, q3, q0  @ encoding: [0x06,0xfe,0x01,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xfe,0x01,0x6e]
+
+# CHECK: vqrdmlsdh.s16 q0, q7, q4  @ encoding: [0x1e,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfe,0x09,0x0e]
+
+# CHECK: vqrdmlsdh.s32 q0, q6, q7  @ encoding: [0x2c,0xfe,0x0f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xfe,0x0f,0x0e]
+
+# CHECK: vcmul.f16 q6, q2, q5, #0  @ encoding: [0x34,0xee,0x0a,0xce]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xee,0x0a,0xce]
+
+# CHECK: vcmul.f16 q1, q0, q5, #90  @ encoding: [0x30,0xee,0x0b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x2e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #180  @ encoding: [0x30,0xee,0x0a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0a,0x3e]
+
+# CHECK: vcmul.f16 q1, q0, q5, #270  @ encoding: [0x30,0xee,0x0b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x0b,0x3e]
+
+# CHECK: vcmul.f32 q1, q7, q5, #0  @ encoding: [0x3e,0xfe,0x0a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0a,0x2e]
+
+# CHECK: vcmul.f32 q3, q4, q2, #90  @ encoding: [0x38,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x05,0x6e]
+
+# CHECK: vcmul.f32 q5, q1, q3, #180  @ encoding: [0x32,0xfe,0x06,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x06,0xbe]
+
+# CHECK: vcmul.f32 q0, q7, q4, #270  @ encoding: [0x3e,0xfe,0x09,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x09,0x1e]
+
+# CHECK: vmullb.s8 q2, q6, q0  @ encoding: [0x0d,0xee,0x00,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x00,0x4e]
+
+# CHECK: vmullb.s16 q3, q4, q3  @ encoding: [0x19,0xee,0x06,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x06,0x6e]
+
+# CHECK: vmullb.s32 q3, q5, q6  @ encoding: [0x2b,0xee,0x0c,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x0c,0x6e]
+
+# CHECK: vmullt.s8 q0, q6, q2  @ encoding: [0x0d,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s16 q0, q0, q2  @ encoding: [0x11,0xee,0x04,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xee,0x04,0x1e]
+
+# CHECK: vmullt.s32 q2, q4, q4  @ encoding: [0x29,0xee,0x08,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x29,0xee,0x08,0x5e]
+
+# CHECK: vmullb.p8 q2, q3, q7  @ encoding: [0x37,0xee,0x0e,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0e,0x4e]
+
+# CHECK: vmullb.p16 q0, q1, q3  @ encoding: [0x33,0xfe,0x06,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x06,0x0e]
+
+# CHECK: vmullt.p8 q1, q1, q7  @ encoding: [0x33,0xee,0x0e,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x0e,0x3e]
+
+# CHECK: vmullt.p16 q0, q7, q7  @ encoding: [0x3f,0xfe,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x0e,0x1e]
+
+# CHECK: vmulh.s8 q0, q4, q5  @ encoding: [0x09,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x0b,0x0e]
+
+# CHECK: vmulh.s16 q0, q7, q4  @ encoding: [0x1f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.s32 q0, q7, q4  @ encoding: [0x2f,0xee,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x09,0x0e]
+
+# CHECK: vmulh.u8 q3, q5, q2  @ encoding: [0x0b,0xfe,0x05,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x05,0x6e]
+
+# CHECK: vmulh.u16 q2, q7, q4  @ encoding: [0x1f,0xfe,0x09,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xfe,0x09,0x4e]
+
+# CHECK: vmulh.u32 q1, q3, q2  @ encoding: [0x27,0xfe,0x05,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xfe,0x05,0x2e]
+
+# CHECK: vrmulh.s8 q1, q1, q2  @ encoding: [0x03,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s16 q1, q1, q2  @ encoding: [0x13,0xee,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xee,0x05,0x3e]
+
+# CHECK: vrmulh.s32 q3, q1, q0  @ encoding: [0x23,0xee,0x01,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x01,0x7e]
+
+# CHECK: vrmulh.u8 q1, q6, q0  @ encoding: [0x0d,0xfe,0x01,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xfe,0x01,0x3e]
+
+# CHECK: vrmulh.u16 q4, q3, q6  @ encoding: [0x17,0xfe,0x0d,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x0d,0x9e]
+
+# CHECK: vrmulh.u32 q1, q2, q2  @ encoding: [0x25,0xfe,0x05,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x25,0xfe,0x05,0x3e]
+
+# CHECK: vqmovnb.s16 q0, q1  @ encoding: [0x33,0xee,0x03,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x03,0x0e]
+
+# CHECK: vqmovnt.s16 q2, q0  @ encoding: [0x33,0xee,0x01,0x5e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x01,0x5e]
+
+# CHECK: vqmovnb.s32 q0, q5  @ encoding: [0x37,0xee,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x0b,0x0e]
+
+# CHECK: vqmovnt.s32 q0, q1  @ encoding: [0x37,0xee,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x03,0x1e]
+
+# CHECK: vqmovnb.u16 q0, q4  @ encoding: [0x33,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u16 q0, q7  @ encoding: [0x33,0xfe,0x0f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x0f,0x1e]
+
+# CHECK: vqmovnb.u32 q0, q4  @ encoding: [0x37,0xfe,0x09,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x09,0x0e]
+
+# CHECK: vqmovnt.u32 q0, q2  @ encoding: [0x37,0xfe,0x05,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x05,0x1e]
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x3e]
+
+# CHECK: vcvtb.f32.f16 q0, q3  @ encoding: [0x3f,0xfe,0x07,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x07,0x0e]
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vqmovunb.s16 q0, q3  @ encoding: [0x31,0xee,0x87,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x87,0x0e]
+
+# CHECK: vqmovunt.s16 q4, q1  @ encoding: [0x31,0xee,0x83,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x83,0x9e]
+
+# CHECK: vqmovunb.s32 q1, q7  @ encoding: [0x35,0xee,0x8f,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x8f,0x2e]
+
+# CHECK: vqmovunt.s32 q0, q2  @ encoding: [0x35,0xee,0x85,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x85,0x1e]
+
+# CHECK: vmovnb.i16 q1, q5  @ encoding: [0x31,0xfe,0x8b,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x8b,0x2e]
+
+# CHECK: vmovnt.i16 q0, q0  @ encoding: [0x31,0xfe,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x81,0x1e]
+
+# CHECK: vmovnb.i32 q1, q0  @ encoding: [0x35,0xfe,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x81,0x2e]
+
+# CHECK: vmovnt.i32 q3, q3  @ encoding: [0x35,0xfe,0x87,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x87,0x7e]
+
+# CHECK: vmaxa.s8 q0, q7  @ encoding: [0x33,0xee,0x8f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x0e]
+
+# CHECK: vmaxa.s16 q1, q0  @ encoding: [0x37,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x81,0x2e]
+
+# CHECK: vmaxa.s32 q1, q0  @ encoding: [0x3b,0xee,0x81,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x81,0x2e]
+
+# CHECK: vmaxnma.f16 q1, q1  @ encoding: [0x3f,0xfe,0x83,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x83,0x2e]
+
+# CHECK: vmaxnma.f32 q2, q6  @ encoding: [0x3f,0xee,0x8d,0x4e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x8d,0x4e]
+
+# CHECK: vmina.s8 q1, q7  @ encoding: [0x33,0xee,0x8f,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x8f,0x3e]
+
+# CHECK: vmina.s16 q1, q4  @ encoding: [0x37,0xee,0x89,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x89,0x3e]
+
+# CHECK: vmina.s32 q0, q7  @ encoding: [0x3b,0xee,0x8f,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x8f,0x1e]
+
+# CHECK: vminnma.f16 q0, q2  @ encoding: [0x3f,0xfe,0x85,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x85,0x1e]
+
+# CHECK: vminnma.f32 q0, q1  @ encoding: [0x3f,0xee,0x83,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x83,0x1e]
+
+# CHECK: vhcadd.s8 q3, q7, q5, #90  @ encoding: [0x0e,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q0, q0, q6, #90  @ encoding: [0x10,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x0c,0x0f]
+
+# CHECK: vhcadd.s16 q3, q1, q0, #270  @ encoding: [0x12,0xee,0x00,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x00,0x7f]
+
+# CHECK: vhcadd.s32 q3, q4, q5, #90  @ encoding: [0x28,0xee,0x0a,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x0a,0x6f]
+
+# CHECK: vhcadd.s32 q6, q7, q2, #270  @ encoding: [0x2e,0xee,0x04,0xdf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xee,0x04,0xdf]
+
+# CHECK: vadc.i32 q1, q0, q2  @ encoding: [0x30,0xee,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x30,0xee,0x04,0x2f]
+
+# CHECK: vadci.i32 q0, q1, q1  @ encoding: [0x32,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x02,0x1f]
+
+# CHECK: vcadd.i8 q1, q0, q2, #90  @ encoding: [0x00,0xfe,0x04,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xfe,0x04,0x2f]
+
+# CHECK: vcadd.i16 q0, q2, q3, #90  @ encoding: [0x14,0xfe,0x06,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x06,0x0f]
+
+# CHECK: vcadd.i16 q0, q5, q5, #270  @ encoding: [0x1a,0xfe,0x0a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x0a,0x1f]
+
+# CHECK: vcadd.i32 q4, q2, q5, #90  @ encoding: [0x24,0xfe,0x0a,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x0a,0x8f]
+
+# CHECK: vcadd.i32 q5, q5, q0, #270  @ encoding: [0x2a,0xfe,0x00,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x00,0xbf]
+
+# CHECK: vsbc.i32 q3, q1, q1  @ encoding: [0x32,0xfe,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x02,0x6f]
+
+# CHECK: vsbci.i32 q2, q6, q2  @ encoding: [0x3c,0xfe,0x04,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xfe,0x04,0x5f]
+
+# CHECK: vqdmullb.s16 q0, q4, q5  @ encoding: [0x38,0xee,0x0b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x0b,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q6, q5  @ encoding: [0x3c,0xee,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xee,0x0b,0x1f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s32 q0, q7, q5  @ encoding: [0x3e,0xfe,0x0b,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3e,0xfe,0x0b,0x1f]
+
+# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x00,0x1e]
+
+# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x00,0x1e]
+
+# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x00,0x1e]
+
+# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x00,0xbe]
+
+# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x20,0x1e]
+
+# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x20,0x7e]
+
+# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x80,0x1e]
+
+# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x80,0x1e]
+
+# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x80,0x1e]
+
+# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x80,0xbe]
+
+# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xa0,0x1e]
+
+# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0xa0,0x7e]
+
+# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x00,0x1f]
+
+# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x00,0x1f]
+
+# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x00,0x1f]
+
+# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x00,0xbf]
+
+# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x20,0x1f]
+
+# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x20,0x7f]
+
+# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0x00,0x1e]
+
+# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x00,0x1e]
+
+# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xfc,0x00,0x1e]
+
+# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x00,0xbe]
+
+# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0x20,0x1e]
+
+# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x20,0x7e]
+
+# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0x80,0x1e]
+
+# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x80,0x1e]
+
+# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xfc,0x80,0x1e]
+
+# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x80,0xbe]
+
+# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0xa0,0x1e]
+
+# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0xa0,0x7e]
+
+# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0x00,0x1f]
+
+# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x00,0x1f]
+
+# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xfc,0x00,0x1f]
+
+# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x00,0xbf]
+
+# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xfc,0x20,0x1f]
+
+# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0xfc,0x20,0x7f]
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x01,0x1e]
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x01,0x1e]
+
+# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x01,0x1e]
+
+# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x01,0x7e]
+
+# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x21,0x1e]
+
+# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x21,0x9e]
+
+# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x41,0x1e]
+
+# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x41,0x1e]
+
+# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x61,0x1e]
+
+# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x61,0x9e]
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x81,0x1e]
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x81,0x1e]
+
+# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x81,0x1e]
+
+# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x81,0x7e]
+
+# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xa1,0x1e]
+
+# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0xa1,0x9e]
+
+# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xc1,0x1e]
+
+# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0xc1,0x1e]
+
+# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xe1,0x1e]
+
+# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0xe1,0x9e]
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x01,0x1f]
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x01,0x1f]
+
+# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xfc,0x01,0x1f]
+
+# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x01,0x7f]
+
+# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x21,0x1f]
+
+# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x21,0x9f]
+
+# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x41,0x1f]
+
+# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x41,0x1f]
+
+# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x61,0x1f]
+
+# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfc,0x61,0x9f]
+
+# CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x1e]
+
+# CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x3e]
+
+# CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x00,0x1e]
+
+# CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x00,0x7e]
+
+# CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x38,0x1e]
+
+# CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x38,0x9e]
+
+# CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xed,0x38,0x1e]
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x38,0xbe]
+
+# CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x38,0xbe]
+
+# CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xec,0x19,0xbe]
+
+# CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3a,0xec,0x19,0xbe]
+
+# CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x19,0xbe]
+
+# CHECK: vldrb.u8 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x40,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x40,0xbe]
+
+# CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x1e]
+
+# CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x3e]
+
+# CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x00,0x1e]
+
+# CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x00,0x7e]
+
+# CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x38,0x1e]
+
+# CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x38,0x9e]
+
+# CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xed,0x38,0x1e]
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x38,0xbe]
+
+# CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x38,0xbe]
+
+# CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xec,0x19,0xbe]
+
+# CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xec,0x19,0xbe]
+
+# CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x19,0xbe]
+
+# CHECK: vstrb.8 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x40,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x40,0xbe]
+
+# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0xad,0xec,0x00,0x1e]
+
+# CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfd,0x80,0x0e]
+
+# CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfd,0x80,0x2e]
+
+# CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xfd,0x80,0x0e]
+
+# CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xfd,0x80,0x6e]
+
+# CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xfd,0xb8,0x0e]
+
+# CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xfd,0xb8,0x8e]
+
+# CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0xb8,0x0e]
+
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfd,0xb8,0xae]
+
+# CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfd,0xb8,0xae]
+
+# CHECK: vldrb.u16 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xfc,0x99,0xae]
+
+# CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfc,0x99,0xae]
+
+# CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfd,0x99,0xae]
+
+# CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfd,0xc0,0xae]
+
+# CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x80,0x0e]
+
+# CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x80,0x2e]
+
+# CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xed,0x80,0x0e]
+
+# CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xed,0x80,0x6e]
+
+# CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0xb8,0x0e]
+
+# CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0xb8,0x8e]
+
+# CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xed,0xb8,0x0e]
+
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0xb8,0xae]
+
+# CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0xb8,0xae]
+
+# CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xec,0x99,0xae]
+
+# CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xec,0x99,0xae]
+
+# CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xed,0x99,0xae]
+
+# CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xed,0xc0,0xae]
+
+# CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x80,0x0e]
+
+# CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x80,0x2e]
+
+# CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x87,0xed,0x80,0x0e]
+
+# CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x87,0xed,0x80,0x6e]
+
+# CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0xb8,0x0e]
+
+# CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0xb8,0x8e]
+
+# CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x85,0xed,0xb8,0x0e]
+
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0xb8,0xae]
+
+# CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0xb8,0xae]
+
+# CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xec,0x99,0xae]
+
+# CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xec,0x99,0xae]
+
+# CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xed,0x99,0xae]
+
+# CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xed,0xc0,0xae]
+
+# CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfd,0x00,0x0f]
+
+# CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfd,0x00,0x2f]
+
+# CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xfd,0x00,0x0f]
+
+# CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xfd,0x00,0x6f]
+
+# CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xfd,0x38,0x0f]
+
+# CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xfd,0x38,0x8f]
+
+# CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x38,0x0f]
+
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfd,0x38,0xaf]
+
+# CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfd,0x38,0xaf]
+
+# CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xfc,0x19,0xaf]
+
+# CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfc,0x19,0xaf]
+
+# CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfd,0x19,0xaf]
+
+# CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfd,0x40,0xaf]
+
+# CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x0f]
+
+# CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x2f]
+
+# CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xed,0x00,0x0f]
+
+# CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x97,0xed,0x00,0x6f]
+
+# CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x38,0x0f]
+
+# CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x38,0x8f]
+
+# CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xed,0x38,0x0f]
+
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x38,0xaf]
+
+# CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x38,0xaf]
+
+# CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xec,0x19,0xaf]
+
+# CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xec,0x19,0xaf]
+
+# CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xed,0x19,0xaf]
+
+# CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xed,0x40,0xaf]
+
+# CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x0f]
+
+# CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x2f]
+
+# CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x87,0xed,0x00,0x0f]
+
+# CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x87,0xed,0x00,0x6f]
+
+# CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x38,0x0f]
+
+# CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x38,0x8f]
+
+# CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x85,0xed,0x38,0x0f]
+
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x38,0xaf]
+
+# CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x38,0xaf]
+
+# CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xec,0x19,0xaf]
+
+# CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xec,0x19,0xaf]
+
+# CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xed,0x19,0xaf]
+
+# CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xed,0x40,0xaf]
+
+# CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x80,0x1e]
+
+# CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x80,0x3e]
+
+# CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x80,0x1e]
+
+# CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x80,0x7e]
+
+# CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x9c,0x1e]
+
+# CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x9c,0x9e]
+
+# CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xed,0x9c,0x1e]
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x9c,0xbe]
+
+# CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x9c,0xbe]
+
+# CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xec,0x8d,0xbe]
+
+# CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3a,0xec,0x8d,0xbe]
+
+# CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x8d,0xbe]
+
+# CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0xa0,0xbe]
+
+# CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0xff,0xbe]
+
+# CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xec,0xff,0xbe]
+
+# CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x80,0x1e]
+
+# CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x80,0x3e]
+
+# CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x80,0x1e]
+
+# CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x80,0x7e]
+
+# CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x9c,0x1e]
+
+# CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x9c,0x9e]
+
+# CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xed,0x9c,0x1e]
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x9c,0xbe]
+
+# CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x9c,0xbe]
+
+# CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xec,0x8d,0xbe]
+
+# CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xec,0x8d,0xbe]
+
+# CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x8d,0xbe]
+
+# CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0xa0,0xbe]
+
+# CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0xff,0xbe]
+
+# CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xaa,0xec,0xff,0xbe]
+
+# CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfd,0x00,0x0f]
+
+# CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfd,0x00,0x2f]
+
+# CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9f,0xfd,0x00,0x0f]
+
+# CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9f,0xfd,0x00,0x6f]
+
+# CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xfd,0x1c,0x0f]
+
+# CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xfd,0x1c,0x8f]
+
+# CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9a,0xfd,0x1c,0x0f]
+
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xfd,0x1c,0xaf]
+
+# CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xfd,0x1c,0xaf]
+
+# CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xfc,0x0d,0xaf]
+
+# CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfc,0x0d,0xaf]
+
+# CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfd,0x0d,0xaf]
+
+# CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfd,0x20,0xaf]
+
+# CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xfd,0x7f,0xaf]
+
+# CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xfd,0x7f,0xaf]
+
+# CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xed,0x00,0x0f]
+
+# CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xed,0x00,0x2f]
+
+# CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9f,0xed,0x00,0x0f]
+
+# CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9f,0xed,0x00,0x6f]
+
+# CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xed,0x1c,0x0f]
+
+# CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xed,0x1c,0x8f]
+
+# CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9a,0xed,0x1c,0x0f]
+
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xed,0x1c,0xaf]
+
+# CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xed,0x1c,0xaf]
+
+# CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3c,0xec,0x0d,0xaf]
+
+# CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xec,0x0d,0xaf]
+
+# CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xed,0x0d,0xaf]
+
+# CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xed,0x20,0xaf]
+
+# CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xed,0x7f,0xaf]
+
+# CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbc,0xed,0x7f,0xaf]
+
+# CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xed,0x00,0x0f]
+
+# CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xed,0x00,0x2f]
+
+# CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xed,0x00,0x0f]
+
+# CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xed,0x00,0x6f]
+
+# CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xed,0x1c,0x0f]
+
+# CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xed,0x1c,0x8f]
+
+# CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xed,0x1c,0x0f]
+
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xac,0xed,0x1c,0xaf]
+
+# CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xac,0xed,0x1c,0xaf]
+
+# CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xec,0x0d,0xaf]
+
+# CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xec,0x0d,0xaf]
+
+# CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xed,0x0d,0xaf]
+
+# CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xed,0x20,0xaf]
+
+# CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xed,0x7f,0xaf]
+
+# CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xac,0xed,0x7f,0xaf]
+
+# CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x1f]
+
+# CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xed,0x00,0x3f]
+
+# CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x00,0x1f]
+
+# CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xed,0x00,0x7f]
+
+# CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x0e,0x1f]
+
+# CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xed,0x0e,0x9f]
+
+# CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xed,0x0e,0x1f]
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x0e,0xbf]
+
+# CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x0e,0xbf]
+
+# CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0xec,0x07,0xbf]
+
+# CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3a,0xec,0x07,0xbf]
+
+# CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x07,0xbf]
+
+# CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x10,0xbf]
+
+# CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xed,0x7f,0xbf]
+
+# CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xed,0x7f,0xbf]
+
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbd,0xed,0x7f,0xbf]
+
+# CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x1f]
+
+# CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xed,0x00,0x3f]
+
+# CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x00,0x1f]
+
+# CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xed,0x00,0x7f]
+
+# CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x0e,0x1f]
+
+# CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xed,0x0e,0x9f]
+
+# CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xed,0x0e,0x1f]
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x0e,0xbf]
+
+# CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x0e,0xbf]
+
+# CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xec,0x07,0xbf]
+
+# CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xec,0x07,0xbf]
+
+# CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x07,0xbf]
+
+# CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x10,0xbf]
+
+# CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xed,0x7f,0xbf]
+
+# CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa4,0xed,0x7f,0xbf]
+
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xad,0xed,0x7f,0xbf]
+
+# CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x02,0x0e]
+
+# CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9a,0xfc,0x02,0x6e]
+
+# CHECK: vldrb.u8 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x06,0x6e]
+
+# CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x82,0x0e]
+
+# CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfc,0x82,0x6e]
+
+# CHECK: vldrb.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x86,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x86,0x6e]
+
+# CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x82,0x0e]
+
+# CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9d,0xec,0x82,0x6e]
+
+# CHECK: vldrb.s16 q3, [r0, q3] @ encoding: [0x90,0xec,0x86,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x86,0x6e]
+
+# CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x02,0x0f]
+
+# CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x02,0x6f]
+
+# CHECK: vldrb.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x06,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x06,0x6f]
+
+# CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x02,0x0f]
+
+# CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x02,0x6f]
+
+# CHECK: vldrb.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x06,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x06,0x6f]
+
+# CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x92,0x0e]
+
+# CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x92,0x6e]
+
+# CHECK: vldrh.u16 q3, [r0, q3] @ encoding: [0x90,0xfc,0x96,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x96,0x6e]
+
+# CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x12,0x0f]
+
+# CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x12,0x6f]
+
+# CHECK: vldrh.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x16,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x16,0x6f]
+
+# CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x12,0x0f]
+
+# CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x12,0x6f]
+
+# CHECK: vldrh.s32 q3, [r0, q3] @ encoding: [0x90,0xec,0x16,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xec,0x16,0x6f]
+
+# CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x93,0x0e]
+
+# CHECK: vldrh.u32 q3, [r8, q3, uxtw #1] @ encoding: [0x98,0xfc,0x17,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfc,0x17,0x6f]
+
+# CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x42,0x0f]
+
+# CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x42,0x6f]
+
+# CHECK: vldrw.u32 q3, [r0, q3] @ encoding: [0x90,0xfc,0x46,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x46,0x6f]
+
+# CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0x43,0x0f]
+
+# CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9d,0xfc,0x43,0x0f]
+
+# CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xd2,0x0f]
+
+# CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xd2,0x6f]
+
+# CHECK: vldrd.u64 q3, [r0, q3] @ encoding: [0x90,0xfc,0xd6,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xd6,0x6f]
+
+# CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xfc,0xd3,0x0f]
+
+# CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9d,0xfc,0xd3,0x0f]
+
+# CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x02,0x0e]
+
+# CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xec,0x02,0x6e]
+
+# CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x06,0x6e]
+
+# CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x82,0x0e]
+
+# CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xec,0x82,0x6e]
+
+# CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x86,0x6e]
+
+# CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x02,0x0f]
+
+# CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x02,0x6f]
+
+# CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x06,0x6f]
+
+# CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x92,0x0e]
+
+# CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x92,0x6e]
+
+# CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x96,0x6e]
+
+# CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x12,0x0f]
+
+# CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x12,0x6f]
+
+# CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x16,0x6f]
+
+# CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x93,0x0e]
+
+# CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xec,0x17,0x6f]
+
+# CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x42,0x0f]
+
+# CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x42,0x6f]
+
+# CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x46,0x6f]
+
+# CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0x43,0x0f]
+
+# CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xec,0x43,0x0f]
+
+# CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0xd2,0x0f]
+
+# CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0xd2,0x6f]
+
+# CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0xd6,0x6f]
+
+# CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xec,0xd3,0x0f]
+
+# CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xec,0xd3,0x0f]
+
+# CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x00,0x1e]
+
+# CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x00,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb2,0xfd,0x00,0xfe]
+
+# CHECK: vldrw.u32 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9e,0xfd,0x00,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x01,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfd,0x01,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x7f,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfd,0x7f,0xfe]
+
+# CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x42,0xfe]
+
+# CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x00,0x1e]
+
+# CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x00,0xfe]
+
+# CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xfd,0x00,0xfe]
+
+# CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xfd,0x00,0xfe]
+
+# CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x01,0xfe]
+
+# CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfd,0x01,0xfe]
+
+# CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x7f,0xfe]
+
+# CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfd,0x7f,0xfe]
+
+# CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xfd,0x42,0xfe]
+
+# CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x00,0x1f]
+
+# CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x00,0xff]
+
+# CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb2,0xfd,0x00,0xff]
+
+# CHECK: vldrd.u64 q7, [q7] @ encoding: [0x9e,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9e,0xfd,0x00,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x01,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfd,0x01,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x7f,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xfd,0x7f,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x21,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x4e,0xff]
+
+# CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfd,0x21,0xff]
+
+# CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x00,0x1f]
+
+# CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x00,0xff]
+
+# CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xfd,0x00,0xff]
+
+# CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xfd,0x00,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x01,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xfd,0x01,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x7f,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfd,0x7f,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x21,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x4e,0xff]
+
+# CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x82,0xfd,0x21,0xff]
+
+# CHECK: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x00,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x24,0xf0,0x49,0xcd]
+
+# CHECK: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x3e,0xf0,0xe9,0xcd]
+
+# CHECK: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0xb7,0xc6]
+
+# CHECK: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x11,0xf0,0x13,0xc2]
+
+# CHECK: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0xe3,0xc7]
+
+# CHECK: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x01,0xf0,0x0d,0xc9]
+
+# CHECK: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xbf,0xc2]
+
+# CHECK: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xc1,0xc2]
+
+# CHECK: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0x9b,0xcc]
+
+# CHECK: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xfb,0xcf]
+
+# CHECK: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0b,0xf0,0xd1,0xca]
+
+# CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x15,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x32,0xf0,0x01,0xe0]
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xc8]
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x05,0xc0]
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0xff,0xcf]
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x4f,0xf0,0x01,0xe0]
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x43,0x1f]
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x4e,0x1f]
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x4a,0x3f]
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x47,0x2f]
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x4b,0x0f]
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x46,0x0f]
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x68,0x5f]
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x60,0x3f]
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x60,0x1f]
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x62,0x1f]
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x66,0x1f]
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x62,0x1f]
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x61,0x0f]
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x62,0x6f]
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x6b,0x0f]
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x68,0x0f]
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x69,0x0f]
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xfe,0x67,0x0f]
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x66,0x0f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x60,0x1f]
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x65,0x1f]
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x47,0x1f]
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x4a,0x3f]
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x4e,0x0f]
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x44,0x2f]
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x4e,0x1f]
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x46,0x1f]
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x47,0x3f]
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xfe,0x45,0x3f]
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x4a,0x1f]
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x4c,0x1f]
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x4a,0x0f]
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xfe,0x4e,0x0f]
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x42,0x2f]
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x4b,0x0f]
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0xe0,0x1e]
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0xe3,0x1e]
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0xee,0x1e]
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0xe0,0x1e]
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0xe2,0x1e]
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0xe3,0x1e]
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0xe0,0x1e]
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0xe1,0x3e]
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0xe3,0x1e]
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0xe1,0x1e]
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0xeb,0x1e]
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0xee,0x1e]
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x66,0x1e]
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x6e,0x1e]
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x64,0x1e]
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x60,0x1e]
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x6a,0x1e]
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x61,0x1e]
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x61,0x1e]
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x1e]
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x6a,0x3e]
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0x6c,0x1e]
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xfe,0x68,0x1e]
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x61,0x1e]
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x60,0x1e]
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x6c,0x1e]
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x67,0x1e]
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x6b,0x1e]
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x0e]
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x67,0x0e]
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x66,0x0e]
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x62,0x0e]
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x68,0x2e]
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xfe,0x66,0x0e]
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x62,0x0e]
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xfe,0x62,0x0e]
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4c,0x1e]
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x4e,0x1e]
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x46,0x1e]
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x49,0x1e]
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x46,0x1e]
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x4e,0x1e]
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x4c,0x1e]
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x4b,0x3e]
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x46,0x2e]
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x46,0xfe]
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x48,0x0e]
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xee,0x4a,0x2e]
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x41,0x2e]
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xfe,0x4a,0x0e]
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x47,0x0e]
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x4a,0x2e]
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xee,0x65,0x1e]
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x6e,0x1e]
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x63,0x1e]
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x62,0x1e]
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x62,0x3e]
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x60,0x3e]
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x63,0x0e]
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x69,0xae]
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xee,0x6b,0x0e]
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xfe,0x6e,0x0e]
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfe,0x6a,0x0e]
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x62,0x2e]
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4a,0x1e]
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x42,0x1e]
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x44,0x1e]
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x49,0x1e]
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x4c,0x1e]
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xfe,0x47,0x1e]
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x4a,0x0e]
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x42,0x0e]
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x41,0x0e]
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x42,0x0e]
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x60,0x0f]
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xe1,0x2f]
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0xe4,0xcf]
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0xeb,0x1f]
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x61,0x1f]
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xe7,0x1f]
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x6f,0x0f]
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0xee,0x0f]
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xee,0x6e,0x0f]
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0xee,0x1f]
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xee,0x1f]
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xef,0x5f]
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0e,0xf0,0x01,0xe8]
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x01,0xe8]
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x2a,0xf0,0x01,0xe8]
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x31,0xf0,0x01,0xe8]
+
+# CHECK: vcmp.f16 eq, q4, r12  @ encoding: [0x39,0xfe,0x4c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0x4c,0x0f]
+
+# CHECK: vcmp.f32 ne, q3, r0  @ encoding: [0x37,0xee,0xc0,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0xc0,0x0f]
+
+# CHECK: vcmp.i8 eq, q1, r0  @ encoding: [0x03,0xfe,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xfe,0x40,0x0f]
+
+# CHECK: vcmp.s8 le, q1, r0  @ encoding: [0x03,0xfe,0xe0,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xfe,0xe0,0x1f]
+
+# CHECK: vcmp.u8 cs, q1, r0  @ encoding: [0x03,0xfe,0x60,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xfe,0x60,0x0f]
+
+# CHECK: vcmp.i16 eq, q5, r10  @ encoding: [0x1b,0xfe,0x4a,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xfe,0x4a,0x0f]
+
+# CHECK: vcmp.i32 eq, q1, r4  @ encoding: [0x23,0xfe,0x44,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x44,0x0f]
+
+# CHECK: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x0f]
+
+# CHECK: vmov.8 q0[1], r8  @ encoding: [0x40,0xee,0x30,0x8b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x40,0xee,0x30,0x8b]
+
+# CHECK: vmov.16 q0[2], r5  @ encoding: [0x20,0xee,0x30,0x5b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x30,0x5b]
+
+# CHECK: vmov.32 q6[3], r11  @ encoding: [0x2d,0xee,0x10,0xbb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xee,0x10,0xbb]
+
+# CHECK: vmov.32 r0, q1[0]  @ encoding: [0x12,0xee,0x10,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xee,0x10,0x0b]
+
+# CHECK: vmov.s16 r1, q2[7]  @ encoding: [0x35,0xee,0x70,0x1b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x70,0x1b]
+
+# CHECK: vmov.s8 r0, q4[13]  @ encoding: [0x79,0xee,0x30,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x79,0xee,0x30,0x0b]
+
+# CHECK: vmov.u16 r0, q1[4]  @ encoding: [0x93,0xee,0x30,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x93,0xee,0x30,0x0b]
+
+# CHECK: vmov.u8 r0, q5[7]  @ encoding: [0xfa,0xee,0x70,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xfa,0xee,0x70,0x0b]
+
+# CHECK: vmov lr, r7, q4[2], q4[0]  @ encoding: [0x07,0xec,0x0e,0x8f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xec,0x0e,0x8f]
+
+# CHECK: vmov    q3[3], q3[1], r4, r1  @ encoding: [0x11,0xec,0x14,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xec,0x14,0x6f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x40,0xec,0x00,0x0f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x50,0xec,0x00,0x0f]
+
+# CHECK: vmov.i32 q0, #0x1bff  @ encoding: [0x81,0xef,0x5b,0x0c]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xef,0x5b,0x0c]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc0,0xef,0x50,0x00]
+
+# CHECK: vmov.i16 q0, #0x5c  @ encoding: [0x85,0xef,0x5c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x85,0xef,0x5c,0x08]
+
+# CHECK: vmov.i8 q0, #0x4c  @ encoding: [0x84,0xef,0x5c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x84,0xef,0x5c,0x0e]
+
+# CHECK: vmov.f32 q0, #-3.625000e+00  @ encoding: [0x80,0xff,0x5d,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x80,0xff,0x5d,0x0f]
+
+# CHECK: vmov.f32 q0, #1.000000e+00  @ encoding: [0x87,0xef,0x50,0x0f]
+0x87,0xef,0x50,0x0f
+
+# CHECK: vmov.f32 s16, s1  @ encoding: [0xb0,0xee,0x60,0x8a]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xee,0x60,0x8a]
+
+# CHECK: vmov.f64 d0, d1  @ encoding: [0xb0,0xee,0x41,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xee,0x41,0x0b]
+
+# CHECK: vmov.i64 q0, #0xff0000ffffffffff  @ encoding: [0x81,0xff,0x7f,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xff,0x7f,0x0e]
+
+# CHECK: vorr.i16 q0, #0x12  @ encoding: [0x81,0xef,0x52,0x09]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xef,0x52,0x09]
+
+# CHECK: vorr.i32 q0, #0x1200  @ encoding: [0x81,0xef,0x52,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x81,0xef,0x52,0x03]
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xdc,0xfe,0x0b,0xee]
+
+# CHECK: vmlsdav.s16 lr, q0, q3  @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vcvtb.f16.f32 q1, q4  @ encoding: [0x3f,0xee,0x09,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xee,0x09,0x2e]
+
+# CHECK: vcvtt.f32.f16 q0, q1  @ encoding: [0x3f,0xfe,0x03,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3f,0xfe,0x03,0x1e]
+
+# CHECK: vcvt.f16.s16 q0, q1  @ encoding: [0xb7,0xff,0x42,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb7,0xff,0x42,0x06]
+
+# CHECK: vcvt.f16.u16 q0, q4  @ encoding: [0xb7,0xff,0xc8,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb7,0xff,0xc8,0x06]
+
+# CHECK: vcvt.s16.f16 q0, q0  @ encoding: [0xb7,0xff,0x40,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb7,0xff,0x40,0x07]
+
+# CHECK: vcvt.u16.f16 q0, q0  @ encoding: [0xb7,0xff,0xc0,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb7,0xff,0xc0,0x07]
+
+# CHECK: vcvt.f32.s32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0x40,0x06]
+
+# CHECK: vcvt.f32.u32 q0, q0  @ encoding: [0xbb,0xff,0xc0,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0xc0,0x06]
+
+# CHECK: vcvt.s32.f32 q0, q0  @ encoding: [0xbb,0xff,0x40,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0x40,0x07]
+
+# CHECK: vcvt.u32.f32 q0, q2  @ encoding: [0xbb,0xff,0xc4,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xff,0xc4,0x07]
+
+# CHECK: vmov.f16 s7, r8 @ encoding: [0x03,0xee,0x90,0x89]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x90,0x89]
+
+# CHECK: vmov.f16 s10, r5 @ encoding: [0x05,0xee,0x10,0x59]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0x10,0x59]
+
+# CHECK: vmov.f16 s10, sp @ encoding: [0x05,0xee,0x10,0xd9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0x10,0xd9]
+
+# CHECK: vmov.f16 s31, r10 @ encoding: [0x0f,0xee,0x90,0xa9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x90,0xa9]
+
+# CHECK: vmov.f16 r8, s7 @ encoding: [0x13,0xee,0x90,0x89]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xee,0x90,0x89]
+
+# CHECK: vmov.f16 r5, s10 @ encoding: [0x15,0xee,0x10,0x59]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x10,0x59]
+
+# CHECK: vmov.f16 sp, s10 @ encoding: [0x15,0xee,0x10,0xd9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x10,0xd9]
+
+# CHECK: vmov.f16 r10, s31 @ encoding: [0x1f,0xee,0x90,0xa9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x90,0xa9]
+
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0x10,0xf9]
+
+# ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x90,0xf9]
+
+# CHECK: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xee,0x60,0x0a]
+
+# CHECK: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb6,0xee,0x41,0x0b]
+
+# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb2,0xee,0xc0,0x0b]
+
+# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf3,0xee,0xc2,0x0b]
+
+# CHECK: vcvt.f16.s16 q1, q7, #11 @ encoding: [0xb5,0xef,0x5e,0x2c]
+# CHECK: vcvt.s16.f16 q1, q1, #3 @ encoding: [0xbd,0xef,0x52,0x2d]
+# CHECK: vcvt.f16.u16 q2, q1, #10 @ encoding: [0xb6,0xff,0x52,0x4c]
+# CHECK: vcvt.u16.f16 q0, q0, #3 @ encoding: [0xbd,0xff,0x50,0x0d]
+# CHECK: vcvt.f32.s32 q1, q7, #6 @ encoding: [0xba,0xef,0x5e,0x2e]
+# CHECK: vcvt.s32.f32 q1, q0, #21 @ encoding: [0xab,0xef,0x50,0x2f]
+# CHECK: vcvt.f32.u32 q1, q4, #4 @ encoding: [0xbc,0xff,0x58,0x2e]
+# CHECK: vcvt.u32.f32 q1, q5, #8 @ encoding: [0xb8,0xff,0x5a,0x2f]
+[0xb5,0xef,0x5e,0x2c]
+[0xbd,0xef,0x52,0x2d]
+[0xb6,0xff,0x52,0x4c]
+[0xbd,0xff,0x50,0x0d]
+[0xba,0xef,0x5e,0x2e]
+[0xab,0xef,0x50,0x2f]
+[0xbc,0xff,0x58,0x2e]
+[0xb8,0xff,0x5a,0x2f]
+
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+[0x71,0xfe,0x4d,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstt @ encoding: [0x31,0xfe,0x4d,0x8f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+[0x31,0xfe,0x4d,0x8f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x8f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttt @ encoding: [0x31,0xfe,0x4d,0x4f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x4f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstte @ encoding: [0x31,0xfe,0x4d,0xcf]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xcf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xcf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstee @ encoding: [0x71,0xfe,0x4d,0x4f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x4f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstttt @ encoding: [0x31,0xfe,0x4d,0x2f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x2f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttte @ encoding: [0x31,0xfe,0x4d,0x6f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x6f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttet @ encoding: [0x31,0xfe,0x4d,0xef]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xef]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttee @ encoding: [0x31,0xfe,0x4d,0xaf]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xaf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpstett @ encoding: [0x71,0xfe,0x4d,0xaf]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xaf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpstete @ encoding: [0x71,0xfe,0x4d,0xef]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xef]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsteee @ encoding: [0x71,0xfe,0x4d,0x2f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x2f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOMVE: it eq @ encoding: [0x08,0xbf]
+[0x08,0xbf]
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+[0x0f,0xf0,0x01,0xe0]
+
+# CHECK: vmvn.i32 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x00]
+[0x83,0xef,0x75,0x00]
+
+# CHECK: vbic.i32 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x01]
+[0x83,0xef,0x75,0x01]
+
+# CHECK: vmvn.i32 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x02]
+[0x83,0xef,0x75,0x02]
+
+# CHECK: vbic.i32 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x03]
+[0x83,0xef,0x75,0x03]
+
+# CHECK: vmvn.i32 q0, #0x350000 @ encoding: [0x83,0xef,0x75,0x04]
+[0x83,0xef,0x75,0x04]
+
+# CHECK: vbic.i32 q0, #0x350000 @ encoding: [0x83,0xef,0x75,0x05]
+[0x83,0xef,0x75,0x05]
+
+# CHECK: vmvn.i32 q0, #0x35000000 @ encoding: [0x83,0xef,0x75,0x06]
+[0x83,0xef,0x75,0x06]
+
+# CHECK: vbic.i32 q0, #0x35000000 @ encoding: [0x83,0xef,0x75,0x07]
+[0x83,0xef,0x75,0x07]
+
+# CHECK: vmvn.i16 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x08]
+[0x83,0xef,0x75,0x08]
+
+# CHECK: vbic.i16 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x09]
+[0x83,0xef,0x75,0x09]
+
+# CHECK: vmvn.i16 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x0a]
+[0x83,0xef,0x75,0x0a]
+
+# CHECK: vbic.i16 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x0b]
+[0x83,0xef,0x75,0x0b]
+
+# CHECK: vmvn.i32 q0, #0x35ff @ encoding: [0x83,0xef,0x75,0x0c]
+[0x83,0xef,0x75,0x0c]
+
+# CHECK: vmvn.i32 q0, #0x35ffff @ encoding: [0x83,0xef,0x75,0x0d]
+[0x83,0xef,0x75,0x0d]
+
+# CHECK: vmov.i64 q0, #0xffff00ff00ff @ encoding: [0x83,0xef,0x75,0x0e]
+[0x83,0xef,0x75,0x0e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x83,0xef,0x75,0x0f]
+
+# CHECK: vldrb.u8 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3e]
+[0x92,0xed,0x00,0x3e]
+
+# CHECK: vldrb.u8 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3e]
+[0x12,0xed,0x00,0x3e]
+
+# CHECK: vldrb.u16 q1, [r2] @ encoding: [0x92,0xfd,0x80,0x2e]
+[0x92,0xfd,0x80,0x2e]
+
+# CHECK: vldrb.u16 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x80,0x2e]
+[0x12,0xfd,0x80,0x2e]
+
+# CHECK: vldrb.s16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x2e]
+[0x92,0xed,0x80,0x2e]
+
+# CHECK: vldrb.s16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x2e]
+[0x12,0xed,0x80,0x2e]
+
+# CHECK: vldrb.u32 q1, [r2] @ encoding: [0x92,0xfd,0x00,0x2f]
+[0x92,0xfd,0x00,0x2f]
+
+# CHECK: vldrb.u32 q1, [r2, #-0] @ encoding: [0x12,0xfd,0x00,0x2f]
+[0x12,0xfd,0x00,0x2f]
+
+# CHECK: vldrb.s32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x2f]
+[0x92,0xed,0x00,0x2f]
+
+# CHECK: vldrb.s32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x2f]
+[0x12,0xed,0x00,0x2f]
+
+# CHECK: vldrh.u16 q1, [r2] @ encoding: [0x92,0xed,0x80,0x3e]
+[0x92,0xed,0x80,0x3e]
+
+# CHECK: vldrh.u16 q1, [r2, #-0] @ encoding: [0x12,0xed,0x80,0x3e]
+[0x12,0xed,0x80,0x3e]
+
+# CHECK: vldrh.u32 q1, [r2] @ encoding: [0x9a,0xfd,0x00,0x2f]
+[0x9a,0xfd,0x00,0x2f]
+
+# CHECK: vldrh.u32 q1, [r2, #-0] @ encoding: [0x1a,0xfd,0x00,0x2f]
+[0x1a,0xfd,0x00,0x2f]
+
+# CHECK: vldrh.s32 q1, [r2] @ encoding: [0x9a,0xed,0x00,0x2f]
+[0x9a,0xed,0x00,0x2f]
+
+# CHECK: vldrh.s32 q1, [r2, #-0] @ encoding: [0x1a,0xed,0x00,0x2f]
+[0x1a,0xed,0x00,0x2f]
+
+# CHECK: vldrw.u32 q1, [r2] @ encoding: [0x92,0xed,0x00,0x3f]
+[0x92,0xed,0x00,0x3f]
+
+# CHECK: vldrw.u32 q1, [r2, #-0] @ encoding: [0x12,0xed,0x00,0x3f]
+[0x12,0xed,0x00,0x3f]
+
+# CHECK: vldrw.u32 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3e]
+[0x94,0xfd,0x00,0x3e]
+
+# CHECK: vldrw.u32 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3e]
+[0x14,0xfd,0x00,0x3e]
+
+# CHECK: vldrd.u64 q1, [q2] @ encoding: [0x94,0xfd,0x00,0x3f]
+[0x94,0xfd,0x00,0x3f]
+
+# CHECK: vldrd.u64 q1, [q2, #-0] @ encoding: [0x14,0xfd,0x00,0x3f]
+[0x14,0xfd,0x00,0x3f]
+
+# CHECK: vstrb.8 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3e]
+[0x82,0xed,0x00,0x3e]
+
+# CHECK: vstrb.8 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3e]
+[0x02,0xed,0x00,0x3e]
+
+# CHECK: vstrb.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x2e]
+[0x82,0xed,0x80,0x2e]
+
+# CHECK: vstrb.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x2e]
+[0x02,0xed,0x80,0x2e]
+
+# CHECK: vstrb.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x2f]
+[0x82,0xed,0x00,0x2f]
+
+# CHECK: vstrb.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x2f]
+[0x02,0xed,0x00,0x2f]
+
+# CHECK: vstrh.16 q1, [r2] @ encoding: [0x82,0xed,0x80,0x3e]
+[0x82,0xed,0x80,0x3e]
+
+# CHECK: vstrh.16 q1, [r2, #-0] @ encoding: [0x02,0xed,0x80,0x3e]
+[0x02,0xed,0x80,0x3e]
+
+# CHECK: vstrh.32 q1, [r2] @ encoding: [0x8a,0xed,0x00,0x2f]
+[0x8a,0xed,0x00,0x2f]
+
+# CHECK: vstrh.32 q1, [r2, #-0] @ encoding: [0x0a,0xed,0x00,0x2f]
+[0x0a,0xed,0x00,0x2f]
+
+# CHECK: vstrw.32 q1, [r2] @ encoding: [0x82,0xed,0x00,0x3f]
+[0x82,0xed,0x00,0x3f]
+
+# CHECK: vstrw.32 q1, [r2, #-0] @ encoding: [0x02,0xed,0x00,0x3f]
+[0x02,0xed,0x00,0x3f]
+
+# CHECK: vstrw.32 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3e]
+[0x84,0xfd,0x00,0x3e]
+
+# CHECK: vstrw.32 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3e]
+[0x04,0xfd,0x00,0x3e]
+
+# CHECK: vstrd.64 q1, [q2] @ encoding: [0x84,0xfd,0x00,0x3f]
+[0x84,0xfd,0x00,0x3f]
+
+# CHECK: vstrd.64 q1, [q2, #-0] @ encoding: [0x04,0xfd,0x00,0x3f]
+[0x04,0xfd,0x00,0x3f]
diff --git a/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt b/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt
--- a/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt
+++ b/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt
@@ -1,6 +1,9 @@
 # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
 # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
+# RUN: llvm-mc < %s -triple=thumbv8.1m.main-none-eabi -disassemble | FileCheck %s --check-prefix=RAS
+# RUN: not llvm-mc < %s -triple=thumbv8m-none-eabi -disassemble 2>&1 | FileCheck %s --check-prefix=FAIL
 
 [0xaf,0xf3,0x10,0x80]
 # RAS: esb
 # NO-RAS: hint.w #16
+# FAIL: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt b/llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt
@@ -0,0 +1,1158 @@
+# RUN: not llvm-mc -disassemble --show-encoding %s -triple=thumbv8.1m.main 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK:  bf #24, #46
+0x40 0xf6 0x17 0xe8
+0xb8 0xbf
+
+# CHECK:  bflt #18, #40
+0xc0 0xf4 0x15 0xe0
+
+# CHECK: bfcsel #14, #36, #16, ne
+0x84 0xf3 0x13 0xe0
+
+# CHECK:  bfx #10, r2
+0xe2 0xf2 0x01 0xe0
+
+# CHECK:  bflx #6, r3
+0xf3 0xf1 0x01 0xe0
+
+# CHECK:  bfl #2, #30402
+0x87 0xf0 0x61 0xcb
+
+# CHECK:  wls lr, r8, #36
+0x48 0xf0 0x13 0xc0
+
+# CHECK:  dls lr, r10
+0x4a 0xf0 0x01 0xe0
+
+# CHECK:  le #-24
+0x2f 0xf0 0x0d 0xc0
+
+# CHECK:  le lr, #-32
+0x0f 0xf0 0x11 0xc0
+
+# CHECK: bf      #10, #-56508  @ encoding: [0xd2,0xf2,0xa3,0xe1]
+0xd2 0xf2 0xa3 0xe1
+
+# CHECK: bf      #10, #3942  @ encoding: [0xc0,0xf2,0xb3,0xef]
+0xc0 0xf2 0xb3 0xef
+
+# CHECK: bf      #10, #50810  @ encoding: [0xcc,0xf2,0x3d,0xeb]
+0xcc 0xf2 0x3d 0xeb
+
+# CHECK: bf      #12, #-35896  @ encoding: [0x57,0xf3,0xe5,0xe1]
+0x57 0xf3 0xe5 0xe1
+
+# CHECK: bf      #12, #-62848  @ encoding: [0x50,0xf3,0x41,0xe5]
+0x50 0xf3 0x41 0xe5
+
+# CHECK: bf      #12, #25864  @ encoding: [0x46,0xf3,0x85,0xe2]
+0x46 0xf3 0x85 0xe2
+
+# CHECK: bf      #12, #30558  @ encoding: [0x47,0xf3,0xaf,0xeb]
+0x47 0xf3 0xaf 0xeb
+
+# CHECK: bf      #12, #33774  @ encoding: [0x48,0xf3,0xf7,0xe9]
+0x48 0xf3 0xf7 0xe9
+
+# CHECK: bf      #14, #-48062  @ encoding: [0xd4,0xf3,0x21,0xea]
+0xd4 0xf3 0x21 0xea
+
+# CHECK: bf      #16, #58260  @ encoding: [0x4e,0xf4,0xcb,0xe1]
+0x4e 0xf4 0xcb 0xe1
+
+# CHECK: bf      #2, #1814  @ encoding: [0xc0,0xf0,0x8b,0xeb]
+0xc0 0xf0 0x8b 0xeb
+
+# CHECK: bf      #2, #28648  @ encoding: [0xc6,0xf0,0xf5,0xe7]
+0xc6 0xf0 0xf5 0xe7
+
+# CHECK: bf      #2, #39722  @ encoding: [0xc9,0xf0,0x95,0xed]
+0xc9 0xf0 0x95 0xed
+
+# CHECK: bf      #2, #50996  @ encoding: [0xcc,0xf0,0x9b,0xe3]
+0xcc 0xf0 0x9b 0xe3
+
+# CHECK: bf      #20, #-31552  @ encoding: [0x58,0xf5,0x61,0xe2]
+0x58 0xf5 0x61 0xe2
+
+# CHECK: bf      #22, #40634  @ encoding: [0xc9,0xf5,0x5d,0xef]
+0xc9 0xf5 0x5d 0xef
+
+# CHECK: bf      #24, #-17436  @ encoding: [0x5b,0xf6,0xf3,0xe5]
+0x5b 0xf6 0xf3 0xe5
+
+# CHECK: bf      #24, #-29092  @ encoding: [0x58,0xf6,0x2f,0xe7]
+0x58 0xf6 0x2f 0xe7
+
+# CHECK: bf      #24, #-41178  @ encoding: [0x55,0xf6,0x93,0xef]
+0x55 0xf6 0x93 0xef
+
+# CHECK: bf      #24, #26858  @ encoding: [0x46,0xf6,0x75,0xec]
+0x46 0xf6 0x75 0xec
+
+# CHECK: bf      #24, #58116  @ encoding: [0x4e,0xf6,0x83,0xe1]
+0x4e 0xf6 0x83 0xe1
+
+# CHECK: bf      #26, #-46754  @ encoding: [0xd4,0xf6,0xaf,0xec]
+0xd4 0xf6 0xaf 0xec
+
+# CHECK: bf      #26, #-64786  @ encoding: [0xd0,0xf6,0x77,0xe9]
+0xd0 0xf6 0x77 0xe9
+
+# CHECK: bf      #26, #35362  @ encoding: [0xc8,0xf6,0x11,0xed]
+0xc8 0xf6 0x11 0xed
+
+# CHECK: bf      #28, #-13500  @ encoding: [0x5c,0xf7,0xa3,0xe5]
+0x5c 0xf7 0xa3 0xe5
+
+# CHECK: bf      #28, #-15996  @ encoding: [0x5c,0xf7,0xc3,0xe0]
+0x5c 0xf7 0xc3 0xe0
+
+# CHECK: bf      #28, #-19990  @ encoding: [0x5b,0xf7,0xf5,0xe8]
+0x5b 0xf7 0xf5 0xe8
+
+# CHECK: bf      #28, #-2302  @ encoding: [0x5f,0xf7,0x81,0xeb]
+0x5f 0xf7 0x81 0xeb
+
+# CHECK: bf      #28, #-46326  @ encoding: [0x54,0xf7,0x85,0xed]
+0x54 0xf7 0x85 0xed
+
+# CHECK: bf      #28, #24202  @ encoding: [0x45,0xf7,0x45,0xef]
+0x45 0xf7 0x45 0xef
+
+# CHECK: bf      #28, #28282  @ encoding: [0x46,0xf7,0x3d,0xef]
+0x46 0xf7 0x3d 0xef
+
+# CHECK: bf      #28, #57104  @ encoding: [0x4d,0xf7,0x89,0xe7]
+0x4d 0xf7 0x89 0xe7
+
+# CHECK: bf      #30, #-25942  @ encoding: [0xd9,0xf7,0x55,0xed]
+0xd9 0xf7 0x55 0xed
+
+# CHECK: bf      #30, #-32656  @ encoding: [0xd8,0xf7,0x39,0xe0]
+0xd8 0xf7 0x39 0xe0
+
+# CHECK: bf      #4, #-23408  @ encoding: [0x5a,0xf1,0x49,0xe2]
+0x5a 0xf1 0x49 0xe2
+
+# CHECK: bf      #4, #28878  @ encoding: [0x47,0xf1,0x67,0xe8]
+0x47 0xf1 0x67 0xe8
+
+# CHECK: bf      #4, #31362  @ encoding: [0x47,0xf1,0x41,0xed]
+0x47 0xf1 0x41 0xed
+
+# CHECK: bf      #6, #23604  @ encoding: [0xc5,0xf1,0x1b,0xe6]
+0xc5 0xf1 0x1b 0xe6
+
+# CHECK: bf      #6, #9258  @ encoding: [0xc2,0xf1,0x15,0xea]
+0xc2 0xf1 0x15 0xea
+
+# CHECK: bf      #8, #-10032  @ encoding: [0x5d,0xf2,0x69,0xe4]
+0x5d 0xf2 0x69 0xe4
+
+# CHECK: bf      #8, #-26268  @ encoding: [0x59,0xf2,0xb3,0xe4]
+0x59 0xf2 0xb3 0xe4
+
+# CHECK: bf      #8, #-60046  @ encoding: [0x51,0xf2,0xb9,0xea]
+0x51 0xf2 0xb9 0xea
+
+# CHECK: bf      #8, #19254  @ encoding: [0x44,0xf2,0x9b,0xed]
+0x44 0xf2 0x9b 0xed
+
+# CHECK: bf      #8, #38620  @ encoding: [0x49,0xf2,0x6f,0xe3]
+0x49 0xf2 0x6f 0xe3
+
+# CHECK: bfcsel  #10, #-672, #14, lt  @ encoding: [0xaf,0xf2,0xb1,0xe6]
+0xaf 0xf2 0xb1 0xe6
+
+# CHECK: bfcsel  #10, #2584, #12, pl  @ encoding: [0x94,0xf2,0x0d,0xe5]
+0x94 0xf2 0x0d 0xe5
+
+# CHECK: bfcsel  #12, #1358, #14, ls  @ encoding: [0x24,0xf3,0xa7,0xea]
+0x24 0xf3 0xa7 0xea
+
+# CHECK: bfcsel  #12, #2108, #14, mi  @ encoding: [0x10,0xf3,0x1f,0xe4]
+0x10 0xf3 0x1f 0xe4
+
+# CHECK: bfcsel  #12, #2794, #16, eq  @ encoding: [0x02,0xf3,0x75,0xed]
+0x02 0xf3 0x75 0xed
+
+# CHECK: bfcsel  #14, #-1174, #18, vc  @ encoding: [0x9f,0xf3,0xb5,0xed]
+0x9f 0xf3 0xb5 0xed
+
+# CHECK: bfcsel  #14, #1466, #18, ge  @ encoding: [0xaa,0xf3,0xdd,0xea]
+0xaa 0xf3 0xdd 0xea
+
+# CHECK: bfcsel  #14, #466, #16, lo  @ encoding: [0x8c,0xf3,0xe9,0xe8]
+0x8c 0xf3 0xe9 0xe8
+
+# CHECK: bfcsel  #16, #-2782, #20, vs  @ encoding: [0x1b,0xf4,0x91,0xea]
+0x1b 0xf4 0x91 0xea
+
+# CHECK: bfcsel  #16, #124, #18, ls  @ encoding: [0x24,0xf4,0x3f,0xe0]
+0x24 0xf4 0x3f 0xe0
+
+# CHECK: bfcsel  #16, #1320, #20, ne  @ encoding: [0x06,0xf4,0x95,0xe2]
+0x06 0xf4 0x95 0xe2
+
+# CHECK: bfcsel  #18, #-1914, #20, gt  @ encoding: [0xb1,0xf4,0x43,0xec]
+0xb1 0xf4 0x43 0xec
+
+# CHECK: bfcsel  #18, #-3102, #20, eq  @ encoding: [0x81,0xf4,0xf1,0xe9]
+0x81 0xf4 0xf1 0xe9
+
+# CHECK: bfcsel  #18, #3872, #20, eq  @ encoding: [0x80,0xf4,0x91,0xe7]
+0x80 0xf4 0x91 0xe7
+
+# CHECK: bfcsel  #2, #-1354, #4, vs  @ encoding: [0x99,0xf0,0x5b,0xed]
+0x99 0xf0 0x5b 0xed
+
+# CHECK: bfcsel  #2, #-144, #4, le  @ encoding: [0xb5,0xf0,0xb9,0xe7]
+0xb5 0xf0 0xb9 0xe7
+
+# CHECK: bfcsel  #2, #1552, #4, vc  @ encoding: [0x9c,0xf0,0x09,0xe3]
+0x9c 0xf0 0x09 0xe3
+
+# CHECK: bfcsel  #2, #3962, #4, ls  @ encoding: [0xa4,0xf0,0xbd,0xef]
+0xa4 0xf0 0xbd 0xef
+
+# CHECK: bfcsel  #20, #-1758, #22, gt  @ encoding: [0x31,0xf5,0x91,0xec]
+0x31 0xf5 0x91 0xec
+
+# CHECK: bfcsel  #20, #-2300, #22, mi  @ encoding: [0x11,0xf5,0x83,0xe3]
+0x11 0xf5 0x83 0xe3
+
+# CHECK: bfcsel  #20, #1146, #22, le  @ encoding: [0x34,0xf5,0x3d,0xea]
+0x34 0xf5 0x3d 0xea
+
+# CHECK: bfcsel  #20, #1526, #24, le  @ encoding: [0x36,0xf5,0xfb,0xea]
+0x36 0xf5 0xfb 0xea
+
+# CHECK: bfcsel  #20, #3826, #22, pl  @ encoding: [0x14,0xf5,0x79,0xef]
+0x14 0xf5 0x79 0xef
+
+# CHECK: bfcsel  #20, #4060, #22, eq  @ encoding: [0x00,0xf5,0xef,0xe7]
+0x00 0xf5 0xef 0xe7
+
+# CHECK: bfcsel  #22, #1438, #26, gt  @ encoding: [0xb2,0xf5,0xcf,0xea]
+0xb2 0xf5 0xcf 0xea
+
+# CHECK: bfcsel  #24, #-2782, #28, ne  @ encoding: [0x07,0xf6,0x91,0xea]
+0x07 0xf6 0x91 0xea
+
+# CHECK: bfcsel  #26, #-2112, #28, ge  @ encoding: [0xa9,0xf6,0xe1,0xe3]
+0xa9 0xf6 0xe1 0xe3
+
+# CHECK: bfcsel  #26, #3534, #30, lo  @ encoding: [0x8e,0xf6,0xe7,0xee]
+0x8e 0xf6 0xe7 0xee
+
+# CHECK: bfcsel  #28, #-3198, #32, lo  @ encoding: [0x0f,0xf7,0xc1,0xe9]
+0x0f 0xf7 0xc1 0xe9
+
+# CHECK: bfcsel  #28, #3924, #32, pl  @ encoding: [0x16,0xf7,0xab,0xe7]
+0x16 0xf7 0xab 0xe7
+
+# CHECK: bfcsel  #30, #-1958, #32, ge  @ encoding: [0xa9,0xf7,0x2d,0xec]
+0xa9 0xf7 0x2d 0xec
+
+# CHECK: bfcsel  #30, #2794, #34, vc  @ encoding: [0x9e,0xf7,0x75,0xed]
+0x9e 0xf7 0x75 0xed
+
+# CHECK: bfcsel  #30, #472, #32, ge  @ encoding: [0xa8,0xf7,0xed,0xe0]
+0xa8 0xf7 0xed 0xe0
+
+# CHECK: bfcsel  #4, #-2146, #6, lt  @ encoding: [0x2d,0xf1,0xcf,0xeb]
+0x2d 0xf1 0xcf 0xeb
+
+# CHECK: bfcsel  #4, #-3718, #8, lo  @ encoding: [0x0f,0xf1,0xbd,0xe8]
+0x0f 0xf1 0xbd 0xe8
+
+# CHECK: bfcsel  #4, #-454, #8, ls  @ encoding: [0x27,0xf1,0x1d,0xef]
+0x27 0xf1 0x1d 0xef
+
+# CHECK: bfcsel  #6, #3808, #8, gt  @ encoding: [0xb0,0xf1,0x71,0xe7]
+0xb0 0xf1 0x71 0xe7
+
+# CHECK: bfcsel  #8, #-1158, #12, ls  @ encoding: [0x27,0xf2,0xbd,0xed]
+0x27 0xf2 0xbd 0xed
+
+# CHECK: bfcsel  #8, #2558, #10, ne  @ encoding: [0x04,0xf2,0xff,0xec]
+0x04 0xf2 0xff 0xec
+
+# CHECK: bfcsel  #8, #906, #10, hi  @ encoding: [0x20,0xf2,0xc5,0xe9]
+0x20 0xf2 0xc5 0xe9
+
+# CHECK: bfl     #10, #-201030  @ encoding: [0xce,0xf2,0x5d,0xcf]
+0xce 0xf2 0x5d 0xcf
+
+# CHECK: bfl     #10, #-246952  @ encoding: [0xc3,0xf2,0xad,0xc5]
+0xc3 0xf2 0xad 0xc5
+
+# CHECK: bfl     #10, #173972  @ encoding: [0xaa,0xf2,0xcb,0xc3]
+0xaa 0xf2 0xcb 0xc3
+
+# CHECK: bfl     #10, #95564  @ encoding: [0x97,0xf2,0xa7,0xc2]
+0x97 0xf2 0xa7 0xc2
+
+# CHECK: bfl     #12, #-125840  @ encoding: [0x61,0xf3,0x39,0xc2]
+0x61 0xf3 0x39 0xc2
+
+# CHECK: bfl     #12, #-143570  @ encoding: [0x5c,0xf3,0x97,0xcf]
+0x5c 0xf3 0x97 0xcf
+
+# CHECK: bfl     #12, #128910  @ encoding: [0x1f,0xf3,0xc7,0xcb]
+0x1f 0xf3 0xc7 0xcb
+
+# CHECK: bfl     #12, #221064  @ encoding: [0x35,0xf3,0xc5,0xc7]
+0x35 0xf3 0xc5 0xc7
+
+# CHECK: bfl     #14, #136028  @ encoding: [0xa1,0xf3,0xaf,0xc1]
+0xa1 0xf3 0xaf 0xc1
+
+# CHECK: bfl     #14, #158274  @ encoding: [0xa6,0xf3,0x21,0xcd]
+0xa6 0xf3 0x21 0xcd
+
+# CHECK: bfl     #16, #-1934  @ encoding: [0x7f,0xf4,0x39,0xcc]
+0x7f 0xf4 0x39 0xcc
+
+# CHECK: bfl     #16, #231446  @ encoding: [0x38,0xf4,0x0b,0xcc]
+0x38 0xf4 0x0b 0xcc
+
+# CHECK: bfl     #18, #-15646  @ encoding: [0xfc,0xf4,0x71,0xc9]
+0xfc 0xf4 0x71 0xc9
+
+# CHECK: bfl     #18, #132222  @ encoding: [0xa0,0xf4,0x3f,0xca]
+0xa0 0xf4 0x3f 0xca
+
+# CHECK: bfl     #18, #158602  @ encoding: [0xa6,0xf4,0xc5,0xcd]
+0xa6 0xf4 0xc5 0xcd
+
+# CHECK: bfl     #18, #176344  @ encoding: [0xab,0xf4,0x6d,0xc0]
+0xab 0xf4 0x6d 0xc0
+
+# CHECK: bfl     #2, #-143878  @ encoding: [0xdc,0xf0,0xfd,0xce]
+0xdc 0xf0 0xfd 0xce
+
+# CHECK: bfl     #2, #-198298  @ encoding: [0xcf,0xf0,0xb3,0xcc]
+0xcf 0xf0 0xb3 0xcc
+
+# CHECK: bfl     #2, #229916  @ encoding: [0xb8,0xf0,0x0f,0xc1]
+0xb8 0xf0 0x0f 0xc1
+
+# CHECK: bfl     #2, #69548  @ encoding: [0x90,0xf0,0xd7,0xc7]
+0x90 0xf0 0xd7 0xc7
+
+# CHECK: bfl     #20, #-118408  @ encoding: [0x63,0xf5,0xbd,0xc0]
+0x63 0xf5 0xbd 0xc0
+
+# CHECK: bfl     #20, #-249792  @ encoding: [0x43,0xf5,0x21,0xc0]
+0x43 0xf5 0x21 0xc0
+
+# CHECK: bfl     #20, #207388  @ encoding: [0x32,0xf5,0x0f,0xc5]
+0x32 0xf5 0x0f 0xc5
+
+# CHECK: bfl     #20, #227830  @ encoding: [0x37,0xf5,0xfb,0xcc]
+0x37 0xf5 0xfb 0xcc
+
+# CHECK: bfl     #20, #33722  @ encoding: [0x08,0xf5,0xdd,0xc9]
+0x08 0xf5 0xdd 0xc9
+
+# CHECK: bfl     #22, #207354  @ encoding: [0xb2,0xf5,0xfd,0xcc]
+0xb2 0xf5 0xfd 0xcc
+
+# CHECK: bfl     #22, #232416  @ encoding: [0xb8,0xf5,0xf1,0xc5]
+0xb8 0xf5 0xf1 0xc5
+
+# CHECK: bfl     #24, #-138084  @ encoding: [0x5e,0xf6,0x4f,0xc2]
+0x5e 0xf6 0x4f 0xc2
+
+# CHECK: bfl     #24, #-258634  @ encoding: [0x40,0xf6,0xdb,0xce]
+0x40 0xf6 0xdb 0xce
+
+# CHECK: bfl     #24, #208602  @ encoding: [0x32,0xf6,0x6d,0xcf]
+0x32 0xf6 0x6d 0xcf
+
+# CHECK: bfl     #24, #44986  @ encoding: [0x0a,0xf6,0xdd,0xcf]
+0x0a 0xf6 0xdd 0xcf
+
+# CHECK: bfl     #26, #128586  @ encoding: [0x9f,0xf6,0x25,0xcb]
+0x9f 0xf6 0x25 0xcb
+
+# CHECK: bfl     #26, #2276  @ encoding: [0x80,0xf6,0x73,0xc4]
+0x80 0xf6 0x73 0xc4
+
+# CHECK: bfl     #28, #-194678  @ encoding: [0x50,0xf7,0xc5,0xcb]
+0x50 0xf7 0xc5 0xcb
+
+# CHECK: bfl     #28, #-245860  @ encoding: [0x43,0xf7,0xcf,0xc7]
+0x43 0xf7 0xcf 0xc7
+
+# CHECK: bfl     #30, #181956  @ encoding: [0xac,0xf7,0x63,0xc3]
+0xac 0xf7 0x63 0xc3
+
+# CHECK: bfl     #30, #227704  @ encoding: [0xb7,0xf7,0xbd,0xc4]
+0xb7 0xf7 0xbd 0xc4
+
+# CHECK: bfl     #30, #52348  @ encoding: [0x8c,0xf7,0x3f,0xc6]
+0x8c 0xf7 0x3f 0xc6
+
+# CHECK: bfl     #4, #-228328  @ encoding: [0x48,0xf1,0x0d,0xc2]
+0x48 0xf1 0x0d 0xc2
+
+# CHECK: bfl     #4, #-72122  @ encoding: [0x6e,0xf1,0x23,0xcb]
+0x6e 0xf1 0x23 0xcb
+
+# CHECK: bfl     #4, #129032  @ encoding: [0x1f,0xf1,0x05,0xc4]
+0x1f 0xf1 0x05 0xc4
+
+# CHECK: bfl     #4, #221134  @ encoding: [0x35,0xf1,0xe7,0xcf]
+0x35 0xf1 0xe7 0xcf
+
+# CHECK: bfl     #6, #-106948  @ encoding: [0xe5,0xf1,0x1f,0xc7]
+0xe5 0xf1 0x1f 0xc7
+
+# CHECK: bfl     #6, #-135484  @ encoding: [0xde,0xf1,0x63,0xc7]
+0xde 0xf1 0x63 0xc7
+
+# CHECK: bfl     #6, #-169018  @ encoding: [0xd6,0xf1,0xe3,0xcd]
+0xd6 0xf1 0xe3 0xcd
+
+# CHECK: bfl     #8, #-212316  @ encoding: [0x4c,0xf2,0x53,0xc1]
+0x4c 0xf2 0x53 0xc1
+
+# CHECK: bfl     #8, #148710  @ encoding: [0x24,0xf2,0x73,0xca]
+0x24 0xf2 0x73 0xca
+
+# CHECK: bfl     #8, #15868  @ encoding: [0x03,0xf2,0xff,0xc6]
+0x03 0xf2 0xff 0xc6
+
+# CHECK: bfl     #8, #215194  @ encoding: [0x34,0xf2,0x4d,0xcc]
+0x34 0xf2 0x4d 0xcc
+
+# CHECK: bflx    #10, lr  @ encoding: [0xfe,0xf2,0x01,0xe0]
+0xfe 0xf2 0x01 0xe0
+
+# CHECK: bflx    #10, r7  @ encoding: [0xf7,0xf2,0x01,0xe0]
+0xf7 0xf2 0x01 0xe0
+
+# CHECK: bflx    #12, r4  @ encoding: [0x74,0xf3,0x01,0xe0]
+0x74 0xf3 0x01 0xe0
+
+# CHECK: bflx    #16, r7  @ encoding: [0x77,0xf4,0x01,0xe0]
+0x77 0xf4 0x01 0xe0
+
+# CHECK: bflx    #18, r0  @ encoding: [0xf0,0xf4,0x01,0xe0]
+0xf0 0xf4 0x01 0xe0
+
+# CHECK: bflx    #18, r1  @ encoding: [0xf1,0xf4,0x01,0xe0]
+0xf1 0xf4 0x01 0xe0
+
+# CHECK: bflx    #18, r10  @ encoding: [0xfa,0xf4,0x01,0xe0]
+0xfa 0xf4 0x01 0xe0
+
+# CHECK: bflx    #18, r12  @ encoding: [0xfc,0xf4,0x01,0xe0]
+0xfc 0xf4 0x01 0xe0
+
+# CHECK: bflx    #18, r3  @ encoding: [0xf3,0xf4,0x01,0xe0]
+0xf3 0xf4 0x01 0xe0
+
+# CHECK: bflx    #2, r8  @ encoding: [0xf8,0xf0,0x01,0xe0]
+0xf8 0xf0 0x01 0xe0
+
+# CHECK: bflx    #20, r10  @ encoding: [0x7a,0xf5,0x01,0xe0]
+0x7a 0xf5 0x01 0xe0
+
+# CHECK: bflx    #20, r11  @ encoding: [0x7b,0xf5,0x01,0xe0]
+0x7b 0xf5 0x01 0xe0
+
+# CHECK: bflx    #20, r12  @ encoding: [0x7c,0xf5,0x01,0xe0]
+0x7c 0xf5 0x01 0xe0
+
+# CHECK: bflx    #20, r3  @ encoding: [0x73,0xf5,0x01,0xe0]
+0x73 0xf5 0x01 0xe0
+
+# CHECK: bflx    #20, r6  @ encoding: [0x76,0xf5,0x01,0xe0]
+0x76 0xf5 0x01 0xe0
+
+# CHECK: bflx    #20, r7  @ encoding: [0x77,0xf5,0x01,0xe0]
+0x77 0xf5 0x01 0xe0
+
+# CHECK: bflx    #22, r0  @ encoding: [0xf0,0xf5,0x01,0xe0]
+0xf0 0xf5 0x01 0xe0
+
+# CHECK: bflx    #22, r11  @ encoding: [0xfb,0xf5,0x01,0xe0]
+0xfb 0xf5 0x01 0xe0
+
+# CHECK: bflx    #24, r11  @ encoding: [0x7b,0xf6,0x01,0xe0]
+0x7b 0xf6 0x01 0xe0
+
+# CHECK: bflx    #24, r5  @ encoding: [0x75,0xf6,0x01,0xe0]
+0x75 0xf6 0x01 0xe0
+
+# CHECK: bflx    #26, lr  @ encoding: [0xfe,0xf6,0x01,0xe0]
+0xfe 0xf6 0x01 0xe0
+
+# CHECK: bflx    #26, r0  @ encoding: [0xf0,0xf6,0x01,0xe0]
+0xf0 0xf6 0x01 0xe0
+
+# CHECK: bflx    #26, r11  @ encoding: [0xfb,0xf6,0x01,0xe0]
+0xfb 0xf6 0x01 0xe0
+
+# CHECK: bflx    #26, r7  @ encoding: [0xf7,0xf6,0x01,0xe0]
+0xf7 0xf6 0x01 0xe0
+
+# CHECK: bflx    #26, r8  @ encoding: [0xf8,0xf6,0x01,0xe0]
+0xf8 0xf6 0x01 0xe0
+
+# CHECK: bflx    #28, r2  @ encoding: [0x72,0xf7,0x01,0xe0]
+0x72 0xf7 0x01 0xe0
+
+# CHECK: bflx    #28, r7  @ encoding: [0x77,0xf7,0x01,0xe0]
+0x77 0xf7 0x01 0xe0
+
+# CHECK: bflx    #30, r2  @ encoding: [0xf2,0xf7,0x01,0xe0]
+0xf2 0xf7 0x01 0xe0
+
+# CHECK: bflx    #30, r3  @ encoding: [0xf3,0xf7,0x01,0xe0]
+0xf3 0xf7 0x01 0xe0
+
+# CHECK: bflx    #30, r5  @ encoding: [0xf5,0xf7,0x01,0xe0]
+0xf5 0xf7 0x01 0xe0
+
+# CHECK: bflx    #30, r7  @ encoding: [0xf7,0xf7,0x01,0xe0]
+0xf7 0xf7 0x01 0xe0
+
+# CHECK: bflx    #4, r9  @ encoding: [0x79,0xf1,0x01,0xe0]
+0x79 0xf1 0x01 0xe0
+
+# CHECK: bflx    #6, r3  @ encoding: [0xf3,0xf1,0x01,0xe0]
+0xf3 0xf1 0x01 0xe0
+
+# CHECK: bflx    #6, r4  @ encoding: [0xf4,0xf1,0x01,0xe0]
+0xf4 0xf1 0x01 0xe0
+
+# CHECK: bflx    #6, r7  @ encoding: [0xf7,0xf1,0x01,0xe0]
+0xf7 0xf1 0x01 0xe0
+
+# CHECK: bflx    #8, r1  @ encoding: [0x71,0xf2,0x01,0xe0]
+0x71 0xf2 0x01 0xe0
+
+# CHECK: bflx    #8, r9  @ encoding: [0x79,0xf2,0x01,0xe0]
+0x79 0xf2 0x01 0xe0
+
+# CHECK: bfx     #10, r1  @ encoding: [0xe1,0xf2,0x01,0xe0]
+0xe1 0xf2 0x01 0xe0
+
+# CHECK: bfx     #10, r6  @ encoding: [0xe6,0xf2,0x01,0xe0]
+0xe6 0xf2 0x01 0xe0
+
+# CHECK: bfx     #10, r7  @ encoding: [0xe7,0xf2,0x01,0xe0]
+0xe7 0xf2 0x01 0xe0
+
+# CHECK: bfx     #12, r2  @ encoding: [0x62,0xf3,0x01,0xe0]
+0x62 0xf3 0x01 0xe0
+
+# CHECK: bfx     #12, r4  @ encoding: [0x64,0xf3,0x01,0xe0]
+0x64 0xf3 0x01 0xe0
+
+# CHECK: bfx     #12, r9  @ encoding: [0x69,0xf3,0x01,0xe0]
+0x69 0xf3 0x01 0xe0
+
+# CHECK: bfx     #14, r10  @ encoding: [0xea,0xf3,0x01,0xe0]
+0xea 0xf3 0x01 0xe0
+
+# CHECK: bfx     #14, r3  @ encoding: [0xe3,0xf3,0x01,0xe0]
+0xe3 0xf3 0x01 0xe0
+
+# CHECK: bfx     #14, r5  @ encoding: [0xe5,0xf3,0x01,0xe0]
+0xe5 0xf3 0x01 0xe0
+
+# CHECK: bfx     #14, r7  @ encoding: [0xe7,0xf3,0x01,0xe0]
+0xe7 0xf3 0x01 0xe0
+
+# CHECK: bfx     #16, r4  @ encoding: [0x64,0xf4,0x01,0xe0]
+0x64 0xf4 0x01 0xe0
+
+# CHECK: bfx     #16, r6  @ encoding: [0x66,0xf4,0x01,0xe0]
+0x66 0xf4 0x01 0xe0
+
+# CHECK: bfx     #2, r1  @ encoding: [0xe1,0xf0,0x01,0xe0]
+0xe1 0xf0 0x01 0xe0
+
+# CHECK: bfx     #2, r12  @ encoding: [0xec,0xf0,0x01,0xe0]
+0xec 0xf0 0x01 0xe0
+
+# CHECK: bfx     #2, r6  @ encoding: [0xe6,0xf0,0x01,0xe0]
+0xe6 0xf0 0x01 0xe0
+
+# CHECK: bfx     #20, r6  @ encoding: [0x66,0xf5,0x01,0xe0]
+0x66 0xf5 0x01 0xe0
+
+# CHECK: bfx     #20, r8  @ encoding: [0x68,0xf5,0x01,0xe0]
+0x68 0xf5 0x01 0xe0
+
+# CHECK: bfx     #22, r0  @ encoding: [0xe0,0xf5,0x01,0xe0]
+0xe0 0xf5 0x01 0xe0
+
+# CHECK: bfx     #22, r12  @ encoding: [0xec,0xf5,0x01,0xe0]
+0xec 0xf5 0x01 0xe0
+
+# CHECK: bfx     #22, r8  @ encoding: [0xe8,0xf5,0x01,0xe0]
+0xe8 0xf5 0x01 0xe0
+
+# CHECK: bfx     #24, r1  @ encoding: [0x61,0xf6,0x01,0xe0]
+0x61 0xf6 0x01 0xe0
+
+# CHECK: bfx     #26, lr  @ encoding: [0xee,0xf6,0x01,0xe0]
+0xee 0xf6 0x01 0xe0
+
+# CHECK: bfx     #26, r5  @ encoding: [0xe5,0xf6,0x01,0xe0]
+0xe5 0xf6 0x01 0xe0
+
+# CHECK: bfx     #26, r8  @ encoding: [0xe8,0xf6,0x01,0xe0]
+0xe8 0xf6 0x01 0xe0
+
+# CHECK: bfx     #28, r0  @ encoding: [0x60,0xf7,0x01,0xe0]
+0x60 0xf7 0x01 0xe0
+
+# CHECK: bfx     #28, r3  @ encoding: [0x63,0xf7,0x01,0xe0]
+0x63 0xf7 0x01 0xe0
+
+# CHECK: bfx     #28, r4  @ encoding: [0x64,0xf7,0x01,0xe0]
+0x64 0xf7 0x01 0xe0
+
+# CHECK: bfx     #28, r5  @ encoding: [0x65,0xf7,0x01,0xe0]
+0x65 0xf7 0x01 0xe0
+
+# CHECK: bfx     #30, r7  @ encoding: [0xe7,0xf7,0x01,0xe0]
+0xe7 0xf7 0x01 0xe0
+
+# CHECK: bfx     #4, r0  @ encoding: [0x60,0xf1,0x01,0xe0]
+0x60 0xf1 0x01 0xe0
+
+# CHECK: bfx     #4, r2  @ encoding: [0x62,0xf1,0x01,0xe0]
+0x62 0xf1 0x01 0xe0
+
+# CHECK: bfx     #4, r9  @ encoding: [0x69,0xf1,0x01,0xe0]
+0x69 0xf1 0x01 0xe0
+
+# CHECK: bfx     #6, lr  @ encoding: [0xee,0xf1,0x01,0xe0]
+0xee 0xf1 0x01 0xe0
+
+# CHECK: bfx     #6, r0  @ encoding: [0xe0,0xf1,0x01,0xe0]
+0xe0 0xf1 0x01 0xe0
+
+# CHECK: bfx     #6, r3  @ encoding: [0xe3,0xf1,0x01,0xe0]
+0xe3 0xf1 0x01 0xe0
+
+# CHECK: bfx     #8, r0  @ encoding: [0x60,0xf2,0x01,0xe0]
+0x60 0xf2 0x01 0xe0
+
+# CHECK: bfx     #8, r11  @ encoding: [0x6b,0xf2,0x01,0xe0]
+0x6b 0xf2 0x01 0xe0
+
+# CHECK: bfx     #8, r12  @ encoding: [0x6c,0xf2,0x01,0xe0]
+0x6c 0xf2 0x01 0xe0
+
+# CHECK: dls     lr, lr  @ encoding: [0x4e,0xf0,0x01,0xe0]
+0x4e 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r0  @ encoding: [0x40,0xf0,0x01,0xe0]
+0x40 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r1  @ encoding: [0x41,0xf0,0x01,0xe0]
+0x41 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r10  @ encoding: [0x4a,0xf0,0x01,0xe0]
+0x4a 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r11  @ encoding: [0x4b,0xf0,0x01,0xe0]
+0x4b 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r12  @ encoding: [0x4c,0xf0,0x01,0xe0]
+0x4c 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r2  @ encoding: [0x42,0xf0,0x01,0xe0]
+0x42 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r3  @ encoding: [0x43,0xf0,0x01,0xe0]
+0x43 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r5  @ encoding: [0x45,0xf0,0x01,0xe0]
+0x45 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r6  @ encoding: [0x46,0xf0,0x01,0xe0]
+0x46 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r7  @ encoding: [0x47,0xf0,0x01,0xe0]
+0x47 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r8  @ encoding: [0x48,0xf0,0x01,0xe0]
+0x48 0xf0 0x01 0xe0
+
+# CHECK: dls     lr, r9  @ encoding: [0x49,0xf0,0x01,0xe0]
+0x49 0xf0 0x01 0xe0
+
+# CHECK: le      #-106  @ encoding: [0x2f,0xf0,0x35,0xc8]
+0x2f 0xf0 0x35 0xc8
+
+# CHECK: le      #-1172  @ encoding: [0x2f,0xf0,0x4b,0xc2]
+0x2f 0xf0 0x4b 0xc2
+
+# CHECK: le      #-1210  @ encoding: [0x2f,0xf0,0x5d,0xca]
+0x2f 0xf0 0x5d 0xca
+
+# CHECK: le      #-1260  @ encoding: [0x2f,0xf0,0x77,0xc2]
+0x2f 0xf0 0x77 0xc2
+
+# CHECK: le      #-1262  @ encoding: [0x2f,0xf0,0x77,0xca]
+0x2f 0xf0 0x77 0xca
+
+# CHECK: le      #-1284  @ encoding: [0x2f,0xf0,0x83,0xc2]
+0x2f 0xf0 0x83 0xc2
+
+# CHECK: le      #-1286  @ encoding: [0x2f,0xf0,0x83,0xca]
+0x2f 0xf0 0x83 0xca
+
+# CHECK: le      #-1556  @ encoding: [0x2f,0xf0,0x0b,0xc3]
+0x2f 0xf0 0x0b 0xc3
+
+# CHECK: le      #-178  @ encoding: [0x2f,0xf0,0x59,0xc8]
+0x2f 0xf0 0x59 0xc8
+
+# CHECK: le      #-1882  @ encoding: [0x2f,0xf0,0xad,0xcb]
+0x2f 0xf0 0xad 0xcb
+
+# CHECK: le      #-1900  @ encoding: [0x2f,0xf0,0xb7,0xc3]
+0x2f 0xf0 0xb7 0xc3
+
+# CHECK: le      #-1910  @ encoding: [0x2f,0xf0,0xbb,0xcb]
+0x2f 0xf0 0xbb 0xcb
+
+# CHECK: le      #-2076  @ encoding: [0x2f,0xf0,0x0f,0xc4]
+0x2f 0xf0 0x0f 0xc4
+
+# CHECK: le      #-2266  @ encoding: [0x2f,0xf0,0x6d,0xcc]
+0x2f 0xf0 0x6d 0xcc
+
+# CHECK: le      #-2324  @ encoding: [0x2f,0xf0,0x8b,0xc4]
+0x2f 0xf0 0x8b 0xc4
+
+# CHECK: le      #-2328  @ encoding: [0x2f,0xf0,0x8d,0xc4]
+0x2f 0xf0 0x8d 0xc4
+
+# CHECK: le      #-2456  @ encoding: [0x2f,0xf0,0xcd,0xc4]
+0x2f 0xf0 0xcd 0xc4
+
+# CHECK: le      #-246  @ encoding: [0x2f,0xf0,0x7b,0xc8]
+0x2f 0xf0 0x7b 0xc8
+
+# CHECK: le      #-2476  @ encoding: [0x2f,0xf0,0xd7,0xc4]
+0x2f 0xf0 0xd7 0xc4
+
+# CHECK: le      #-2578  @ encoding: [0x2f,0xf0,0x09,0xcd]
+0x2f 0xf0 0x09 0xcd
+
+# CHECK: le      #-262  @ encoding: [0x2f,0xf0,0x83,0xc8]
+0x2f 0xf0 0x83 0xc8
+
+# CHECK: le      #-2660  @ encoding: [0x2f,0xf0,0x33,0xc5]
+0x2f 0xf0 0x33 0xc5
+
+# CHECK: le      #-2722  @ encoding: [0x2f,0xf0,0x51,0xcd]
+0x2f 0xf0 0x51 0xcd
+
+# CHECK: le      #-2868  @ encoding: [0x2f,0xf0,0x9b,0xc5]
+0x2f 0xf0 0x9b 0xc5
+
+# CHECK: le      #-2882  @ encoding: [0x2f,0xf0,0xa1,0xcd]
+0x2f 0xf0 0xa1 0xcd
+
+# CHECK: le      #-3154  @ encoding: [0x2f,0xf0,0x29,0xce]
+0x2f 0xf0 0x29 0xce
+
+# CHECK: le      #-3274  @ encoding: [0x2f,0xf0,0x65,0xce]
+0x2f 0xf0 0x65 0xce
+
+# CHECK: le      #-3352  @ encoding: [0x2f,0xf0,0x8d,0xc6]
+0x2f 0xf0 0x8d 0xc6
+
+# CHECK: le      #-338  @ encoding: [0x2f,0xf0,0xa9,0xc8]
+0x2f 0xf0 0xa9 0xc8
+
+# CHECK: le      #-3458  @ encoding: [0x2f,0xf0,0xc1,0xce]
+0x2f 0xf0 0xc1 0xce
+
+# CHECK: le      #-3480  @ encoding: [0x2f,0xf0,0xcd,0xc6]
+0x2f 0xf0 0xcd 0xc6
+
+# CHECK: le      #-3542  @ encoding: [0x2f,0xf0,0xeb,0xce]
+0x2f 0xf0 0xeb 0xce
+
+# CHECK: le      #-3644  @ encoding: [0x2f,0xf0,0x1f,0xc7]
+0x2f 0xf0 0x1f 0xc7
+
+# CHECK: le      #-3676  @ encoding: [0x2f,0xf0,0x2f,0xc7]
+0x2f 0xf0 0x2f 0xc7
+
+# CHECK: le      #-3692  @ encoding: [0x2f,0xf0,0x37,0xc7]
+0x2f 0xf0 0x37 0xc7
+
+# CHECK: le      #-3860  @ encoding: [0x2f,0xf0,0x8b,0xc7]
+0x2f 0xf0 0x8b 0xc7
+
+# CHECK: le      #-3986  @ encoding: [0x2f,0xf0,0xc9,0xcf]
+0x2f 0xf0 0xc9 0xcf
+
+# CHECK: le      #-4006  @ encoding: [0x2f,0xf0,0xd3,0xcf]
+0x2f 0xf0 0xd3 0xcf
+
+# CHECK: le      #-4034  @ encoding: [0x2f,0xf0,0xe1,0xcf]
+0x2f 0xf0 0xe1 0xcf
+
+# CHECK: le      #-4060  @ encoding: [0x2f,0xf0,0xef,0xc7]
+0x2f 0xf0 0xef 0xc7
+
+# CHECK: le      #-4068  @ encoding: [0x2f,0xf0,0xf3,0xc7]
+0x2f 0xf0 0xf3 0xc7
+
+# CHECK: le      #-478  @ encoding: [0x2f,0xf0,0xef,0xc8]
+0x2f 0xf0 0xef 0xc8
+
+# CHECK: le      #-544  @ encoding: [0x2f,0xf0,0x11,0xc1]
+0x2f 0xf0 0x11 0xc1
+
+# CHECK: le      #-586  @ encoding: [0x2f,0xf0,0x25,0xc9]
+0x2f 0xf0 0x25 0xc9
+
+# CHECK: le      #-606  @ encoding: [0x2f,0xf0,0x2f,0xc9]
+0x2f 0xf0 0x2f 0xc9
+
+# CHECK: le      #-656  @ encoding: [0x2f,0xf0,0x49,0xc1]
+0x2f 0xf0 0x49 0xc1
+
+# CHECK: le      #-740  @ encoding: [0x2f,0xf0,0x73,0xc1]
+0x2f 0xf0 0x73 0xc1
+
+# CHECK: le      #-762  @ encoding: [0x2f,0xf0,0x7d,0xc9]
+0x2f 0xf0 0x7d 0xc9
+
+# CHECK: le      #-862  @ encoding: [0x2f,0xf0,0xaf,0xc9]
+0x2f 0xf0 0xaf 0xc9
+
+# CHECK: le      #-870  @ encoding: [0x2f,0xf0,0xb3,0xc9]
+0x2f 0xf0 0xb3 0xc9
+
+# CHECK: le      lr, #-1080  @ encoding: [0x0f,0xf0,0x1d,0xc2]
+0x0f 0xf0 0x1d 0xc2
+
+# CHECK: le      lr, #-1104  @ encoding: [0x0f,0xf0,0x29,0xc2]
+0x0f 0xf0 0x29 0xc2
+
+# CHECK: le      lr, #-1152  @ encoding: [0x0f,0xf0,0x41,0xc2]
+0x0f 0xf0 0x41 0xc2
+
+# CHECK: le      lr, #-1462  @ encoding: [0x0f,0xf0,0xdb,0xca]
+0x0f 0xf0 0xdb 0xca
+
+# CHECK: le      lr, #-1470  @ encoding: [0x0f,0xf0,0xdf,0xca]
+0x0f 0xf0 0xdf 0xca
+
+# CHECK: le      lr, #-1612  @ encoding: [0x0f,0xf0,0x27,0xc3]
+0x0f 0xf0 0x27 0xc3
+
+# CHECK: le      lr, #-1632  @ encoding: [0x0f,0xf0,0x31,0xc3]
+0x0f 0xf0 0x31 0xc3
+
+# CHECK: le      lr, #-1694  @ encoding: [0x0f,0xf0,0x4f,0xcb]
+0x0f 0xf0 0x4f 0xcb
+
+# CHECK: le      lr, #-1714  @ encoding: [0x0f,0xf0,0x59,0xcb]
+0x0f 0xf0 0x59 0xcb
+
+# CHECK: le      lr, #-1850  @ encoding: [0x0f,0xf0,0x9d,0xcb]
+0x0f 0xf0 0x9d 0xcb
+
+# CHECK: le      lr, #-1878  @ encoding: [0x0f,0xf0,0xab,0xcb]
+0x0f 0xf0 0xab 0xcb
+
+# CHECK: le      lr, #-1896  @ encoding: [0x0f,0xf0,0xb5,0xc3]
+0x0f 0xf0 0xb5 0xc3
+
+# CHECK: le      lr, #-1922  @ encoding: [0x0f,0xf0,0xc1,0xcb]
+0x0f 0xf0 0xc1 0xcb
+
+# CHECK: le      lr, #-1926  @ encoding: [0x0f,0xf0,0xc3,0xcb]
+0x0f 0xf0 0xc3 0xcb
+
+# CHECK: le      lr, #-2  @ encoding: [0x0f,0xf0,0x01,0xc8]
+0x0f 0xf0 0x01 0xc8
+
+# CHECK: le      lr, #-2104  @ encoding: [0x0f,0xf0,0x1d,0xc4]
+0x0f 0xf0 0x1d 0xc4
+
+# CHECK: le      lr, #-2116  @ encoding: [0x0f,0xf0,0x23,0xc4]
+0x0f 0xf0 0x23 0xc4
+
+# CHECK: le      lr, #-2144  @ encoding: [0x0f,0xf0,0x31,0xc4]
+0x0f 0xf0 0x31 0xc4
+
+# CHECK: le      lr, #-2188  @ encoding: [0x0f,0xf0,0x47,0xc4]
+0x0f 0xf0 0x47 0xc4
+
+# CHECK: le      lr, #-2344  @ encoding: [0x0f,0xf0,0x95,0xc4]
+0x0f 0xf0 0x95 0xc4
+
+# CHECK: le      lr, #-2456  @ encoding: [0x0f,0xf0,0xcd,0xc4]
+0x0f 0xf0 0xcd 0xc4
+
+# CHECK: le      lr, #-2608  @ encoding: [0x0f,0xf0,0x19,0xc5]
+0x0f 0xf0 0x19 0xc5
+
+# CHECK: le      lr, #-2616  @ encoding: [0x0f,0xf0,0x1d,0xc5]
+0x0f 0xf0 0x1d 0xc5
+
+# CHECK: le      lr, #-2622  @ encoding: [0x0f,0xf0,0x1f,0xcd]
+0x0f 0xf0 0x1f 0xcd
+
+# CHECK: le      lr, #-2680  @ encoding: [0x0f,0xf0,0x3d,0xc5]
+0x0f 0xf0 0x3d 0xc5
+
+# CHECK: le      lr, #-2694  @ encoding: [0x0f,0xf0,0x43,0xcd]
+0x0f 0xf0 0x43 0xcd
+
+# CHECK: le      lr, #-2850  @ encoding: [0x0f,0xf0,0x91,0xcd]
+0x0f 0xf0 0x91 0xcd
+
+# CHECK: le      lr, #-2860  @ encoding: [0x0f,0xf0,0x97,0xc5]
+0x0f 0xf0 0x97 0xc5
+
+# CHECK: le      lr, #-3004  @ encoding: [0x0f,0xf0,0xdf,0xc5]
+0x0f 0xf0 0xdf 0xc5
+
+# CHECK: le      lr, #-3018  @ encoding: [0x0f,0xf0,0xe5,0xcd]
+0x0f 0xf0 0xe5 0xcd
+
+# CHECK: le      lr, #-304  @ encoding: [0x0f,0xf0,0x99,0xc0]
+0x0f 0xf0 0x99 0xc0
+
+# CHECK: le      lr, #-3098  @ encoding: [0x0f,0xf0,0x0d,0xce]
+0x0f 0xf0 0x0d 0xce
+
+# CHECK: le      lr, #-3228  @ encoding: [0x0f,0xf0,0x4f,0xc6]
+0x0f 0xf0 0x4f 0xc6
+
+# CHECK: le      lr, #-3316  @ encoding: [0x0f,0xf0,0x7b,0xc6]
+0x0f 0xf0 0x7b 0xc6
+
+# CHECK: le      lr, #-3332  @ encoding: [0x0f,0xf0,0x83,0xc6]
+0x0f 0xf0 0x83 0xc6
+
+# CHECK: le      lr, #-3354  @ encoding: [0x0f,0xf0,0x8d,0xce]
+0x0f 0xf0 0x8d 0xce
+
+# CHECK: le      lr, #-3962  @ encoding: [0x0f,0xf0,0xbd,0xcf]
+0x0f 0xf0 0xbd 0xcf
+
+# CHECK: le      lr, #-4042  @ encoding: [0x0f,0xf0,0xe5,0xcf]
+0x0f 0xf0 0xe5 0xcf
+
+# CHECK: le      lr, #-4052  @ encoding: [0x0f,0xf0,0xeb,0xc7]
+0x0f 0xf0 0xeb 0xc7
+
+# CHECK: le      lr, #-458  @ encoding: [0x0f,0xf0,0xe5,0xc8]
+0x0f 0xf0 0xe5 0xc8
+
+# CHECK: le      lr, #-56  @ encoding: [0x0f,0xf0,0x1d,0xc0]
+0x0f 0xf0 0x1d 0xc0
+
+# CHECK: le      lr, #-582  @ encoding: [0x0f,0xf0,0x23,0xc9]
+0x0f 0xf0 0x23 0xc9
+
+# CHECK: le      lr, #-676  @ encoding: [0x0f,0xf0,0x53,0xc1]
+0x0f 0xf0 0x53 0xc1
+
+# CHECK: le      lr, #-752  @ encoding: [0x0f,0xf0,0x79,0xc1]
+0x0f 0xf0 0x79 0xc1
+
+# CHECK: le      lr, #-76  @ encoding: [0x0f,0xf0,0x27,0xc0]
+0x0f 0xf0 0x27 0xc0
+
+# CHECK: le      lr, #-802  @ encoding: [0x0f,0xf0,0x91,0xc9]
+0x0f 0xf0 0x91 0xc9
+
+# CHECK: le      lr, #-862  @ encoding: [0x0f,0xf0,0xaf,0xc9]
+0x0f 0xf0 0xaf 0xc9
+
+# CHECK: le      lr, #-902  @ encoding: [0x0f,0xf0,0xc3,0xc9]
+0x0f 0xf0 0xc3 0xc9
+
+# CHECK: le      lr, #-968  @ encoding: [0x0f,0xf0,0xe5,0xc1]
+0x0f 0xf0 0xe5 0xc1
+
+# CHECK: wls     lr, lr, #1192  @ encoding: [0x4e,0xf0,0x55,0xc2]
+0x4e 0xf0 0x55 0xc2
+
+# CHECK: wls     lr, lr, #2134  @ encoding: [0x4e,0xf0,0x2b,0xcc]
+0x4e 0xf0 0x2b 0xcc
+
+# CHECK: wls     lr, lr, #962  @ encoding: [0x4e,0xf0,0xe1,0xc9]
+0x4e 0xf0 0xe1 0xc9
+
+# CHECK: wls     lr, r0, #1668  @ encoding: [0x40,0xf0,0x43,0xc3]
+0x40 0xf0 0x43 0xc3
+
+# CHECK: wls     lr, r0, #2706  @ encoding: [0x40,0xf0,0x49,0xcd]
+0x40 0xf0 0x49 0xcd
+
+# CHECK: wls     lr, r0, #3026  @ encoding: [0x40,0xf0,0xe9,0xcd]
+0x40 0xf0 0xe9 0xcd
+
+# CHECK: wls     lr, r0, #3436  @ encoding: [0x40,0xf0,0xb7,0xc6]
+0x40 0xf0 0xb7 0xc6
+
+# CHECK: wls     lr, r1, #1060  @ encoding: [0x41,0xf0,0x13,0xc2]
+0x41 0xf0 0x13 0xc2
+
+# CHECK: wls     lr, r1, #4036  @ encoding: [0x41,0xf0,0xe3,0xc7]
+0x41 0xf0 0xe3 0xc7
+
+# CHECK: wls     lr, r1, #538  @ encoding: [0x41,0xf0,0x0d,0xc9]
+0x41 0xf0 0x0d 0xc9
+
+# CHECK: wls     lr, r10, #1404  @ encoding: [0x4a,0xf0,0xbf,0xc2]
+0x4a 0xf0 0xbf 0xc2
+
+# CHECK: wls     lr, r10, #1408  @ encoding: [0x4a,0xf0,0xc1,0xc2]
+0x4a 0xf0 0xc1 0xc2
+
+# CHECK: wls     lr, r10, #2358  @ encoding: [0x4a,0xf0,0x9b,0xcc]
+0x4a 0xf0 0x9b 0xcc
+
+# CHECK: wls     lr, r10, #4086  @ encoding: [0x4a,0xf0,0xfb,0xcf]
+0x4a 0xf0 0xfb 0xcf
+
+# CHECK: wls     lr, r11, #1442  @ encoding: [0x4b,0xf0,0xd1,0xca]
+0x4b 0xf0 0xd1 0xca
+
+# CHECK: wls     lr, r11, #2678  @ encoding: [0x4b,0xf0,0x3b,0xcd]
+0x4b 0xf0 0x3b 0xcd
+
+# CHECK: wls     lr, r11, #3610  @ encoding: [0x4b,0xf0,0x0d,0xcf]
+0x4b 0xf0 0x0d 0xcf
+
+# CHECK: wls     lr, r12, #206  @ encoding: [0x4c,0xf0,0x67,0xc8]
+0x4c 0xf0 0x67 0xc8
+
+# CHECK: wls     lr, r12, #2896  @ encoding: [0x4c,0xf0,0xa9,0xc5]
+0x4c 0xf0 0xa9 0xc5
+
+# CHECK: wls     lr, r12, #3258  @ encoding: [0x4c,0xf0,0x5d,0xce]
+0x4c 0xf0 0x5d 0xce
+
+# CHECK: wls     lr, r2, #3242  @ encoding: [0x42,0xf0,0x55,0xce]
+0x42 0xf0 0x55 0xce
+
+# CHECK: wls     lr, r2, #3832  @ encoding: [0x42,0xf0,0x7d,0xc7]
+0x42 0xf0 0x7d 0xc7
+
+# CHECK: wls     lr, r2, #872  @ encoding: [0x42,0xf0,0xb5,0xc1]
+0x42 0xf0 0xb5 0xc1
+
+# CHECK: wls     lr, r3, #3514  @ encoding: [0x43,0xf0,0xdd,0xce]
+0x43 0xf0 0xdd 0xce
+
+# CHECK: wls     lr, r3, #3636  @ encoding: [0x43,0xf0,0x1b,0xc7]
+0x43 0xf0 0x1b 0xc7
+
+# CHECK: wls     lr, r3, #3942  @ encoding: [0x43,0xf0,0xb3,0xcf]
+0x43 0xf0 0xb3 0xcf
+
+# CHECK: wls     lr, r3, #712  @ encoding: [0x43,0xf0,0x65,0xc1]
+0x43 0xf0 0x65 0xc1
+
+# CHECK: wls     lr, r4, #2146  @ encoding: [0x44,0xf0,0x31,0xcc]
+0x44 0xf0 0x31 0xcc
+
+# CHECK: wls     lr, r4, #2486  @ encoding: [0x44,0xf0,0xdb,0xcc]
+0x44 0xf0 0xdb 0xcc
+
+# CHECK: wls     lr, r5, #1906  @ encoding: [0x45,0xf0,0xb9,0xcb]
+0x45 0xf0 0xb9 0xcb
+
+# CHECK: wls     lr, r5, #3396  @ encoding: [0x45,0xf0,0xa3,0xc6]
+0x45 0xf0 0xa3 0xc6
+
+# CHECK: wls     lr, r6, #3326  @ encoding: [0x46,0xf0,0x7f,0xce]
+0x46 0xf0 0x7f 0xce
+
+# CHECK: wls     lr, r6, #416  @ encoding: [0x46,0xf0,0xd1,0xc0]
+0x46 0xf0 0xd1 0xc0
+
+# CHECK: wls     lr, r6, #422  @ encoding: [0x46,0xf0,0xd3,0xc8]
+0x46 0xf0 0xd3 0xc8
+
+# CHECK: wls     lr, r7, #3474  @ encoding: [0x47,0xf0,0xc9,0xce]
+0x47 0xf0 0xc9 0xce
+
+# CHECK: wls     lr, r7, #3640  @ encoding: [0x47,0xf0,0x1d,0xc7]
+0x47 0xf0 0x1d 0xc7
+
+# CHECK: wls     lr, r8, #2700  @ encoding: [0x48,0xf0,0x47,0xc5]
+0x48 0xf0 0x47 0xc5
+
+# CHECK: wls     lr, r9, #1114  @ encoding: [0x49,0xf0,0x2d,0xca]
+0x49 0xf0 0x2d 0xca
+
+# CHECK: wls     lr, r9, #1984  @ encoding: [0x49,0xf0,0xe1,0xc3]
+0x49 0xf0 0xe1 0xc3
+
+# CHECK: wls     lr, r9, #3758  @ encoding: [0x49,0xf0,0x57,0xcf]
+0x49 0xf0 0x57 0xcf
+
+# CHECK: wls     lr, r9, #3796  @ encoding: [0x49,0xf0,0x6b,0xc7]
+0x49 0xf0 0x6b 0xc7
+
+# CHECK: cinc lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+0x52 0xea 0x22 0x9e
+
+# CHECK: cinc lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+0x57 0xea 0x47 0x9e
+
+# CHECK: cinv lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+0x5c 0xea 0x3c 0xae
+
+# CHECK: cneg lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+0x5a 0xea 0x3a 0xbe
+
+# CHECK: csel    r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+0x59 0xea 0x7b 0x89
+
+# CHECK: cset lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+0x5f 0xea 0x1f 0x9e
+
+# CHECK: csetm lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+0x5f 0xea 0x3f 0xae
+
+# CHECK: csinc   lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+0x5a 0xea 0xd7 0x9e
+
+# CHECK: csinv   lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+0x55 0xea 0x2f 0xae
+
+# CHECK: cinv lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+0x52 0xea 0x42 0xae
+
+# CHECK: csneg   lr, r1, r11, vc  @ encoding: [0x51,0xea,0x7b,0xbe]
+0x51 0xea 0x7b 0xbe
+
+# CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
+[0x50,0xea,0x01,0x80]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x50,0xea,0xe0,0x80]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x50,0xea,0xf0,0x80]
diff --git a/llvm/test/MC/Disassembler/ARM/thumbv8.1m-vmrs-vmsr.txt b/llvm/test/MC/Disassembler/ARM/thumbv8.1m-vmrs-vmsr.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/thumbv8.1m-vmrs-vmsr.txt
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve -show-encoding -disassemble < %s \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,+mve -show-encoding -disassemble < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
+# RUN:   FileCheck --check-prefix=ERROR-NOSEC < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,-mve,+vfp2 -show-encoding -disassemble < %s 2> %t \
+# RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
+# RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve,-vfp2 -show-encoding -disassemble < %s \
+# RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,-mve,-vfp2 -show-encoding -disassemble < %s 2> %t
+# RUN: FileCheck --check-prefix=ERROR-NONE < %t %s
+# RUN: not llvm-mc -triple=thumbv8m.main-none-eabi -mattr=+8msecext,+vfp2 -show-encoding -disassemble < %s 2> %t
+# RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+# CHECK-NOMVE: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+# CHECK-NOSEC: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+# CHECK: vmsr fpscr_nzcvqc, r0              @ encoding: [0xe2,0xee,0x10,0x0a]
+[0xe2,0xee,0x10,0x0a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+# CHECK-NOMVE: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+# CHECK-NOSEC: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+# CHECK: vmrs r10, fpscr_nzcvqc              @ encoding: [0xf2,0xee,0x10,0xaa]
+[0xf2,0xee,0x10,0xaa]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+# CHECK-NOMVE: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+# ERROR-NOSEC: invalid instruction encoding
+# CHECK: vmrs r0, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x0a]
+[0xfe,0xee,0x10,0x0a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+# CHECK-NOMVE: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+# ERROR-NOSEC: invalid instruction encoding
+# CHECK: vmsr fpcxtns, r10              @ encoding: [0xee,0xee,0x10,0xaa]
+[0xee,0xee,0x10,0xaa]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+# CHECK-NOMVE: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+# ERROR-NOSEC: invalid instruction encoding
+# CHECK: vmsr fpcxts, r5              @ encoding: [0xef,0xee,0x10,0x5a]
+[0xef,0xee,0x10,0x5a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+# CHECK-NOMVE: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+# ERROR-NOSEC: invalid instruction encoding
+# CHECK: vmrs  r3, fpcxtns              @ encoding: [0xfe,0xee,0x10,0x3a]
+[0xfe,0xee,0x10,0x3a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOVFP: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+# CHECK-NOMVE: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+# ERROR-NOSEC: invalid instruction encoding
+# CHECK: vmrs  r0, fpcxts              @ encoding: [0xff,0xee,0x10,0x0a]
+[0xff,0xee,0x10,0x0a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
+# CHECK-NOSEC: vmrs r0, vpr              @ encoding: [0xfc,0xee,0x10,0x0a]
+# CHECK: vmrs r0, vpr              @ encoding: [0xfc,0xee,0x10,0x0a]
+[0xfc,0xee,0x10,0x0a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
+# CHECK-NOSEC: vmrs r4, p0              @ encoding: [0xfd,0xee,0x10,0x4a]
+# CHECK: vmrs r4, p0              @ encoding: [0xfd,0xee,0x10,0x4a]
+[0xfd,0xee,0x10,0x4a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
+# CHECK-NOSEC: vmsr vpr, r0              @ encoding: [0xec,0xee,0x10,0x0a]
+# CHECK: vmsr vpr, r0              @ encoding: [0xec,0xee,0x10,0x0a]
+[0xec,0xee,0x10,0x0a]
+
+# ERROR-V8M: invalid instruction encoding
+# ERROR-NONE: invalid instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
+# CHECK-NOSEC: vmsr p0, r4              @ encoding: [0xed,0xee,0x10,0x4a]
+# CHECK: vmsr p0, r4              @ encoding: [0xed,0xee,0x10,0x4a]
+[0xed,0xee,0x10,0x4a]
diff --git a/llvm/test/MC/Disassembler/ARM/thumbv8.1m.s b/llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
@@ -0,0 +1,104 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+
+[0x52 0xea 0x22 0x9e]
+# CHECK: cinc lr, r2, lo  @ encoding: [0x52,0xea,0x22,0x9e]
+
+[0x57 0xea 0x47 0x9e]
+# CHECK: cinc lr, r7, pl  @ encoding: [0x57,0xea,0x47,0x9e]
+
+[0x5c 0xea 0x3c 0xae]
+# CHECK: cinv lr, r12, hs  @ encoding: [0x5c,0xea,0x3c,0xae]
+
+[0x5a 0xea 0x3a 0xbe]
+# CHECK: cneg lr, r10, hs  @ encoding: [0x5a,0xea,0x3a,0xbe]
+
+[0x59 0xea 0x7b 0x89]
+# CHECK: csel r9, r9, r11, vc  @ encoding: [0x59,0xea,0x7b,0x89]
+
+[0x5f 0xea 0x1f 0x9e]
+# CHECK: cset lr, eq  @ encoding: [0x5f,0xea,0x1f,0x9e]
+
+[0x5f 0xea 0x3f 0xae]
+# CHECK: csetm lr, hs  @ encoding: [0x5f,0xea,0x3f,0xae]
+
+[0x5a 0xea 0xd7 0x9e]
+# CHECK: csinc lr, r10, r7, le  @ encoding: [0x5a,0xea,0xd7,0x9e]
+
+[0x55 0xea 0x2f 0xae]
+# CHECK: csinv lr, r5, zr, hs  @ encoding: [0x55,0xea,0x2f,0xae]
+
+[0x52 0xea 0x42 0xae]
+# CHECK: cinv lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
+
+[0x51 0xea 0x7b 0xbe]
+# CHECK: csneg lr, r1, r11, vc  @ encoding: [0x51,0xea,0x7b,0xbe]
+
+[0x50,0xea,0x01,0x80]
+# CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
+
+[0x5d 0xea 0x22 0x9e]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x47 0x9e]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x3c 0xae]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x3a 0xbe]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x7b 0x89]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x1f 0x9e]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x3f 0xae]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0xd7 0x9e]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x2f 0xae]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x42 0xae]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5d 0xea 0x7b 0xbe]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x52 0xea 0x22 0x9d]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x57 0xea 0x47 0x9d]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5c 0xea 0x3c 0xad]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5a 0xea 0x3a 0xbd]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x59 0xea 0x7b 0x8d]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0x1f 0x9d]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0x3f 0xad]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x5a 0xea 0xd7 0x9d]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x55 0xea 0x2f 0xad]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x52 0xea 0x42 0xad]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+
+[0x51 0xea 0x7b 0xbd]
+# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
diff --git a/llvm/test/MC/Disassembler/ARM/vscclrm.txt b/llvm/test/MC/Disassembler/ARM/vscclrm.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/vscclrm.txt
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding %s 2>1 | FileCheck %s
+
+
+[0x9f 0xec 0x04 0x0a]
+# CHECK: vscclrm {s0, s1, s2, s3, vpr}
+
+[0xdf,0xec,0x06,0x1a]
+# CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
+
+[0x9f 0xec 0x0c 0x9a]
+# CHECK: vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
+
+[0xdf 0xec 0x01 0xfa]
+# CHECK: vscclrm {s31, vpr}
+
+[0x9f,0xec,0x04,0x0b]
+# CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
+
+[0x9f,0xec,0x06,0x5b]
+# CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
+
+[0x88 0xbf]
+# CHECK: it    hi
+
+[0xdf 0xec 0x1d 0x1a]
+# CHECK: vscclrmhi    {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
diff --git a/llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt b/llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt
@@ -0,0 +1,328 @@
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,+mve,+8msecext -show-encoding -disassemble < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN:   FileCheck --check-prefix=ERROR < %t %s
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-vfp2,+mve,+8msecext -show-encoding -disassemble < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
+# RUN:   FileCheck --check-prefix=ERROR-NOVFP < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,-mve,+8msecext -show-encoding -disassemble < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
+# RUN:   FileCheck --check-prefix=ERROR-NOMVE < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+vfp2,+mve,-8msecext -show-encoding -disassemble < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
+# RUN:   FileCheck --check-prefix=ERROR-NOSEC < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-vfp2,-mve,-8msecext -show-encoding -disassemble < %s 2>%t
+# RUN:   FileCheck --check-prefix=ERROR-NONE < %t %s
+
+# ERROR-NONE: invalid instruction encoding
+# CHECK-NOSEC: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK-NOMVE: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK-NOVFP: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+[0x80,0xed,0x80,0x2f]
+
+# CHECK-NOSEC: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+# CHECK-NOMVE: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+# CHECK-NOVFP: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+# CHECK: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
+[0x09,0xed,0x86,0x4f]
+
+# CHECK-NOSEC: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+# CHECK-NOMVE: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+# CHECK-NOVFP: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+# CHECK: vstr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x29,0xed,0x86,0x4f]
+[0x29,0xed,0x86,0x4f]
+
+# CHECK-NOSEC: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+# CHECK-NOMVE: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+# CHECK-NOVFP: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+# CHECK: vstr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x29,0xec,0x86,0x4f]
+[0x29,0xec,0x86,0x4f]
+
+# CHECK-NOSEC: it hi @ encoding: [0x88,0xbf]
+# CHECK-NOMVE: it hi @ encoding: [0x88,0xbf]
+# CHECK-NOVFP: it hi @ encoding: [0x88,0xbf]
+# CHECK: it hi @ encoding: [0x88,0xbf]
+[0x88,0xbf]
+
+# CHECK-NOSEC: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK-NOMVE: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK-NOVFP: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+# CHECK: vstrhi fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
+[0x80,0xed,0x80,0x2f]
+
+# CHECK-NOSEC: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK-NOMVE: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK-NOVFP: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+[0x90,0xed,0x80,0x2f]
+
+# CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+# CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+# CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+# CHECK: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
+[0x19,0xed,0x86,0x4f]
+
+# CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+# CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+# CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+# CHECK: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
+[0x39,0xed,0x86,0x4f]
+
+# CHECK-NOSEC: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+# CHECK-NOMVE: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+# CHECK-NOVFP: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+# CHECK: vldr fpscr_nzcvqc, [r9], #-24 @ encoding: [0x39,0xec,0x86,0x4f]
+[0x39,0xec,0x86,0x4f]
+
+# CHECK-NOSEC: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+# CHECK-NOMVE: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+# CHECK-NOVFP: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+# CHECK: vldr fpscr_nzcvqc, [sp], #-52 @ encoding: [0x3d,0xec,0x8d,0x4f]
+[0x3d,0xec,0x8d,0x4f]
+
+# CHECK-NOSEC: it hi @ encoding: [0x88,0xbf]
+# CHECK-NOMVE: it hi @ encoding: [0x88,0xbf]
+# CHECK-NOVFP: it hi @ encoding: [0x88,0xbf]
+# CHECK: it hi @ encoding: [0x88,0xbf]
+[0x88,0xbf]
+
+# CHECK-NOSEC: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK-NOMVE: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK-NOVFP: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+# CHECK: vldrhi fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
+[0x90,0xed,0x80,0x2f]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+# CHECK-NOVFP: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+# CHECK: vstr fpcxts, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xef]
+[0xcc,0xed,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+# CHECK-NOVFP: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+# CHECK: vstr fpcxts, [r12, #508]! @ encoding: [0xec,0xed,0xff,0xef]
+[0xec,0xed,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+# CHECK-NOVFP: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+# CHECK: vstr fpcxts, [r12], #508 @ encoding: [0xec,0xec,0xff,0xef]
+[0xec,0xec,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+# CHECK-NOVFP: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+# CHECK: vstr fpcxts, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xef]
+[0x6d,0xec,0x86,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+# CHECK-NOVFP: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+# CHECK: vldr fpcxts, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xef]
+[0xdc,0xed,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+# CHECK-NOVFP: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+# CHECK: vldr fpcxts, [r12, #508]! @ encoding: [0xfc,0xed,0xff,0xef]
+[0xfc,0xed,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+# CHECK-NOVFP: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+# CHECK: vldr fpcxts, [r12], #508 @ encoding: [0xfc,0xec,0xff,0xef]
+[0xfc,0xec,0xff,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+# CHECK-NOVFP: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+# CHECK: vldr fpcxts, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xef]
+[0x7d,0xec,0x86,0xef]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+# CHECK: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
+[0xc0,0xed,0x80,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+# CHECK: vstr fpcxtns, [r9, #-24] @ encoding: [0x49,0xed,0x86,0xcf]
+[0x49,0xed,0x86,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+# CHECK: vstr fpcxtns, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0xcf]
+[0xc6,0xed,0xfd,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+# CHECK: vstr fpcxtns, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xcf]
+[0x4e,0xed,0xff,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+# CHECK: vstr fpcxtns, [r12, #508] @ encoding: [0xcc,0xed,0xff,0xcf]
+[0xcc,0xed,0xff,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+# CHECK-NOVFP: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+# CHECK: vstr fpcxtns, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xcf]
+[0x6d,0xec,0x86,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+# CHECK: vldr fpcxtns, [r0] @ encoding: [0xd0,0xed,0x80,0xcf]
+[0xd0,0xed,0x80,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+# CHECK: vldr fpcxtns, [r9, #-24] @ encoding: [0x59,0xed,0x86,0xcf]
+[0x59,0xed,0x86,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+# CHECK: vldr fpcxtns, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0xcf]
+[0xd6,0xed,0xfd,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+# CHECK: vldr fpcxtns, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xcf]
+[0x5e,0xed,0xff,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+# CHECK: vldr fpcxtns, [r12, #508] @ encoding: [0xdc,0xed,0xff,0xcf]
+[0xdc,0xed,0xff,0xcf]
+
+# ERROR-NOSEC invalid instruction encoding
+# CHECK-NOMVE: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+# CHECK-NOVFP: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+# CHECK: vldr fpcxtns, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xcf]
+[0x7d,0xec,0x86,0xcf]
+
+# CHECK-NOSEC: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+# CHECK: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
+[0xc6,0xed,0xfd,0x8f]
+
+# CHECK-NOSEC: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+# CHECK: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
+[0x4e,0xed,0xff,0xaf]
+
+# CHECK-NOSEC: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+# CHECK: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
+[0xe6,0xed,0xfd,0x8f]
+
+# CHECK-NOSEC: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+# CHECK: vstr p0, [lr, #-508]! @ encoding: [0x6e,0xed,0xff,0xaf]
+[0x6e,0xed,0xff,0xaf]
+
+# CHECK-NOSEC: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+# CHECK: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
+[0xe6,0xec,0xfd,0x8f]
+
+# CHECK-NOSEC: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+# CHECK: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
+[0x6e,0xec,0xff,0xaf]
+
+# CHECK-NOSEC: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+# CHECK: vstr p0, [sp], #-24 @ encoding: [0x6d,0xec,0x86,0xaf]
+[0x6d,0xec,0x86,0xaf]
+
+# CHECK-NOSEC: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+# CHECK: vldr vpr, [r6, #500] @ encoding: [0xd6,0xed,0xfd,0x8f]
+[0xd6,0xed,0xfd,0x8f]
+
+# CHECK-NOSEC: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+# CHECK: vldr p0, [lr, #-508] @ encoding: [0x5e,0xed,0xff,0xaf]
+[0x5e,0xed,0xff,0xaf]
+
+# CHECK-NOSEC: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+# CHECK: vldr vpr, [r6, #500]! @ encoding: [0xf6,0xed,0xfd,0x8f]
+[0xf6,0xed,0xfd,0x8f]
+
+# CHECK-NOSEC: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+# CHECK: vldr p0, [lr, #-508]! @ encoding: [0x7e,0xed,0xff,0xaf]
+[0x7e,0xed,0xff,0xaf]
+
+# CHECK-NOSEC: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+# CHECK: vldr vpr, [r6], #500 @ encoding: [0xf6,0xec,0xfd,0x8f]
+[0xf6,0xec,0xfd,0x8f]
+
+# CHECK-NOSEC: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+# CHECK: vldr p0, [lr], #-508 @ encoding: [0x7e,0xec,0xff,0xaf]
+[0x7e,0xec,0xff,0xaf]
+
+# CHECK-NOSEC: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+# ERROR-NOMVE invalid instruction encoding
+# CHECK-NOVFP: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+# CHECK: vldr p0, [sp], #-24 @ encoding: [0x7d,0xec,0x86,0xaf]
+[0x7d,0xec,0x86,0xaf]
+
+# ERROR-NOSEC: invalid instruction encoding
+# ERROR-NOMVE: potentially undefined instruction encoding
+# ERROR-NOVFP: potentially undefined instruction encoding
+# ERROR: potentially undefined instruction encoding
+[0x7f,0xec,0x86,0xcf]
+
+# ERROR-NOSEC: invalid instruction encoding
+# ERROR-NOMVE: potentially undefined instruction encoding
+# ERROR-NOVFP: potentially undefined instruction encoding
+# ERROR: potentially undefined instruction encoding
+[0x7f,0xec,0x86,0xcf]
+
+# ERROR-NOSEC: potentially undefined instruction encoding
+# ERROR-NOMVE: invalid instruction encoding
+# ERROR-NOVFP: potentially undefined instruction encoding
+# ERROR: potentially undefined instruction encoding
+[0xff,0xec,0x81,0xaf]
+
+# ERROR-NOSEC: potentially undefined instruction encoding
+# ERROR-NOMVE: potentially undefined instruction encoding
+# ERROR-NOVFP: potentially undefined instruction encoding
+# ERROR: potentially undefined instruction encoding
+[0xbf,0xed,0x81,0x2f]
+
+# ERROR-NOSEC: potentially undefined instruction encoding
+# ERROR-NOMVE: potentially undefined instruction encoding
+# ERROR-NOVFP: potentially undefined instruction encoding
+# ERROR: potentially undefined instruction encoding
+[0x3f,0xec,0x8d,0x4f]
+