Index: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td @@ -5537,22 +5537,22 @@ // VMAXNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { - def VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f32", - v2f32, v2f32, fmaxnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f32", - v4f32, v4f32, fmaxnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f16", - v4f16, v4f16, fmaxnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; - def VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f16", - v8f16, v8f16, fmaxnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f32", + v2f32, v2f32, fmaxnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f32", + v4f32, v4f32, fmaxnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f16", + v4f16, v4f16, fmaxnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f16", + v8f16, v8f16, fmaxnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; } // VMIN : Vector Minimum @@ -5579,22 +5579,22 @@ // VMINNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { - def VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vminnm", "f32", - v2f32, v2f32, fminnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vminnm", "f32", - v4f32, v4f32, fminnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vminnm", "f16", - v4f16, v4f16, fminnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; - def VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vminnm", "f16", - v8f16, v8f16, fminnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vminnm", "f32", + v2f32, v2f32, fminnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vminnm", "f32", + v4f32, v4f32, fminnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vminnm", "f16", + v4f16, v4f16, fminnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vminnm", "f16", + v8f16, v8f16, fminnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; } // Vector Pairwise Operations. Index: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td @@ -533,8 +533,8 @@ } } -defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; -defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; +defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; +defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; // Match reassociated forms only if not sign dependent rounding. def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), Index: llvm/trunk/lib/Target/ARM/ARMScheduleA57.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA57.td +++ llvm/trunk/lib/Target/ARM/ARMScheduleA57.td @@ -1174,7 +1174,8 @@ // ASIMD FP max/min def : InstRW<[A57Write_5cyc_1V], (instregex - "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "VMAXNM", "VMINNM")>; + "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "(NEON|VFP)_VMAXNM", + "(NEON|VFP)_VMINNM")>; // ASIMD FP multiply def A57WriteVMUL_VecFP : SchedWriteRes<[A57UnitV]> { let Latency = 5; }