Index: include/llvm/ADT/Triple.h =================================================================== --- include/llvm/ADT/Triple.h +++ include/llvm/ADT/Triple.h @@ -109,6 +109,7 @@ ARMSubArch_v8r, ARMSubArch_v8m_baseline, ARMSubArch_v8m_mainline, + ARMSubArch_v8_1m_mainline, ARMSubArch_v7, ARMSubArch_v7em, ARMSubArch_v7m, Index: include/llvm/Support/ARMAttributeParser.h =================================================================== --- include/llvm/Support/ARMAttributeParser.h +++ include/llvm/Support/ARMAttributeParser.h @@ -53,6 +53,8 @@ uint32_t &Offset); void Advanced_SIMD_arch(ARMBuildAttrs::AttrType Tag, const uint8_t *Data, uint32_t &Offset); + void MVE_arch(ARMBuildAttrs::AttrType Tag, const uint8_t *Data, + uint32_t &Offset); void PCS_config(ARMBuildAttrs::AttrType Tag, const uint8_t *Data, uint32_t &Offset); void ABI_PCS_R9_use(ARMBuildAttrs::AttrType Tag, const uint8_t *Data, Index: include/llvm/Support/ARMBuildAttributes.h =================================================================== --- include/llvm/Support/ARMBuildAttributes.h +++ include/llvm/Support/ARMBuildAttributes.h @@ -67,6 +67,7 @@ MPextension_use = 42, // recoded from 70 (ABI r2.08) DIV_use = 44, DSP_extension = 46, + MVE_arch = 48, also_compatible_with = 65, conformance = 67, Virtualization_use = 68, @@ -110,6 +111,7 @@ v8_R = 15, // e.g. Cortex R52 v8_M_Base= 16, // v8_M_Base AArch32 v8_M_Main= 17, // v8_M_Main AArch32 + v8_1_M_Main=21, // v8_1_M_Main AArch32 }; enum CPUArchProfile { // (=7), uleb128 @@ -151,6 +153,10 @@ AllowNeonARMv8 = 3, // ARM v8-A SIMD was permitted AllowNeonARMv8_1a = 4,// ARM v8.1-A SIMD was permitted (RDMA) + // Tag_MVE_arch, (=48), uleb128 + AllowMVEInteger = 1, // integer-only MVE was permitted + AllowMVEIntegerAndFloat = 2, // both integer and floating point MVE were permitted + // Tag_ABI_PCS_R9_use, (=14), uleb128 R9IsGPR = 0, // R9 used as v6 (just another callee-saved register) R9IsSB = 1, // R9 used as a global static base rgister Index: include/llvm/Support/ARMTargetParser.h =================================================================== --- include/llvm/Support/ARMTargetParser.h +++ include/llvm/Support/ARMTargetParser.h @@ -50,6 +50,7 @@ AEK_SVE2SM4 = 1 << 21, AEK_SVE2SHA3 = 1 << 22, AEK_BITPERM = 1 << 23, + AEK_FP_DP = 1 << 24, // Unsupported extensions. AEK_OS = 0x8000000, AEK_IWMMXT = 0x10000000, @@ -131,7 +132,8 @@ VFPV3, VFPV3_FP16, VFPV4, - VFPV5 + VFPV5, + VFPV5_FULLFP16, }; // An FPU name restricts the FPU in one of three ways: Index: include/llvm/Support/ARMTargetParser.def =================================================================== --- include/llvm/Support/ARMTargetParser.def +++ include/llvm/Support/ARMTargetParser.def @@ -31,6 +31,8 @@ ARM_FPU("fpv5-d16", FK_FPV5_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::D16) ARM_FPU("fpv5-sp-d16", FK_FPV5_SP_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::SP_D16) ARM_FPU("fp-armv8", FK_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::None) +ARM_FPU("fp-armv8-fullfp16-d16", FK_FP_ARMV8_FULLFP16_D16, FPUVersion::VFPV5_FULLFP16, NeonSupportLevel::None, FPURestriction::D16) +ARM_FPU("fp-armv8-fullfp16-sp-d16", FK_FP_ARMV8_FULLFP16_SP_D16, FPUVersion::VFPV5_FULLFP16, NeonSupportLevel::None, FPURestriction::SP_D16) ARM_FPU("neon", FK_NEON, FPUVersion::VFPV3, NeonSupportLevel::Neon, FPURestriction::None) ARM_FPU("neon-fp16", FK_NEON_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::Neon, FPURestriction::None) ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FPUVersion::VFPV4, NeonSupportLevel::Neon, FPURestriction::None) @@ -118,6 +120,8 @@ ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB) ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "v8m.main", ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB) +ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "v8.1m.main", + ARMBuildAttrs::CPUArch::v8_1_M_Main, FK_FP_ARMV8_FULLFP16_SP_D16, ARM::AEK_HWDIVTHUMB | ARM::AEK_RAS) // Non-standard Arch names. ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, ARM::AEK_NONE) @@ -144,6 +148,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod","-dotprod") ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp") ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr) +ARM_ARCH_EXT_NAME("mve", ARM::AEK_SIMD, "+mve", "-mve") +ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_SIMD | ARM::AEK_FP), "+mve.fp", "-mve.fp") ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr) ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr) ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr) Index: lib/Object/ELFObjectFile.cpp =================================================================== --- lib/Object/ELFObjectFile.cpp +++ lib/Object/ELFObjectFile.cpp @@ -230,6 +230,24 @@ } } + if (Attributes.hasAttribute(ARMBuildAttrs::MVE_arch)) { + switch(Attributes.getAttributeValue(ARMBuildAttrs::MVE_arch)) { + default: + break; + case ARMBuildAttrs::Not_Allowed: + Features.AddFeature("mve", false); + Features.AddFeature("mve.fp", false); + break; + case ARMBuildAttrs::AllowMVEInteger: + Features.AddFeature("mve.fp", false); + Features.AddFeature("mve"); + break; + case ARMBuildAttrs::AllowMVEIntegerAndFloat: + Features.AddFeature("mve.fp"); + break; + } + } + if (Attributes.hasAttribute(ARMBuildAttrs::DIV_use)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::DIV_use)) { default: Index: lib/Support/ARMAttributeParser.cpp =================================================================== --- lib/Support/ARMAttributeParser.cpp +++ lib/Support/ARMAttributeParser.cpp @@ -37,6 +37,7 @@ ATTRIBUTE_HANDLER(FP_arch), ATTRIBUTE_HANDLER(WMMX_arch), ATTRIBUTE_HANDLER(Advanced_SIMD_arch), + ATTRIBUTE_HANDLER(MVE_arch), ATTRIBUTE_HANDLER(PCS_config), ATTRIBUTE_HANDLER(ABI_PCS_R9_use), ATTRIBUTE_HANDLER(ABI_PCS_RW_data), @@ -132,7 +133,9 @@ static const char *const Strings[] = { "Pre-v4", "ARM v4", "ARM v4T", "ARM v5T", "ARM v5TE", "ARM v5TEJ", "ARM v6", "ARM v6KZ", "ARM v6T2", "ARM v6K", "ARM v7", "ARM v6-M", "ARM v6S-M", - "ARM v7E-M", "ARM v8" + "ARM v7E-M", "ARM v8", nullptr, + "ARM v8-M Baseline", "ARM v8-M Mainline", nullptr, nullptr, nullptr, + "ARM v8.1-M Mainline" }; uint64_t Value = ParseInteger(Data, Offset); @@ -213,6 +216,18 @@ PrintAttribute(Tag, Value, ValueDesc); } +void ARMAttributeParser::MVE_arch(AttrType Tag, const uint8_t *Data, + uint32_t &Offset) { + static const char *const Strings[] = { + "Not Permitted", "MVE integer", "MVE integer and float" + }; + + uint64_t Value = ParseInteger(Data, Offset); + StringRef ValueDesc = + (Value < array_lengthof(Strings)) ? Strings[Value] : nullptr; + PrintAttribute(Tag, Value, ValueDesc); +} + void ARMAttributeParser::PCS_config(AttrType Tag, const uint8_t *Data, uint32_t &Offset) { static const char *const Strings[] = { Index: lib/Support/ARMBuildAttrs.cpp =================================================================== --- lib/Support/ARMBuildAttrs.cpp +++ lib/Support/ARMBuildAttrs.cpp @@ -28,6 +28,7 @@ { ARMBuildAttrs::FP_arch, "Tag_FP_arch" }, { ARMBuildAttrs::WMMX_arch, "Tag_WMMX_arch" }, { ARMBuildAttrs::Advanced_SIMD_arch, "Tag_Advanced_SIMD_arch" }, + { ARMBuildAttrs::MVE_arch, "Tag_MVE_arch" }, { ARMBuildAttrs::PCS_config, "Tag_PCS_config" }, { ARMBuildAttrs::ABI_PCS_R9_use, "Tag_ABI_PCS_R9_use" }, { ARMBuildAttrs::ABI_PCS_RW_data, "Tag_ABI_PCS_RW_data" }, Index: lib/Support/ARMTargetParser.cpp =================================================================== --- lib/Support/ARMTargetParser.cpp +++ lib/Support/ARMTargetParser.cpp @@ -77,6 +77,7 @@ case ArchKind::ARMV8R: case ArchKind::ARMV8MBaseline: case ArchKind::ARMV8MMainline: + case ArchKind::ARMV8_1MMainline: return 8; case ArchKind::INVALID: return 0; @@ -93,6 +94,7 @@ case ArchKind::ARMV7EM: case ArchKind::ARMV8MMainline: case ArchKind::ARMV8MBaseline: + case ArchKind::ARMV8_1MMainline: return ProfileKind::M; case ArchKind::ARMV7R: case ArchKind::ARMV8R: @@ -151,6 +153,7 @@ .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") + .Case("v8.1m.main", "v8.1-m.main") .Default(Arch); } @@ -164,6 +167,10 @@ // higher. We also have to make sure to disable fp16 when vfp4 is disabled, // as +vfp4 implies +fp16 but -vfp4 does not imply -fp16. switch (FPUNames[FPUKind].FPUVer) { + case FPUVersion::VFPV5_FULLFP16: + Features.push_back("+fp-armv8"); + Features.push_back("+fullfp16"); + break; case FPUVersion::VFPV5: Features.push_back("+fp-armv8"); break; Index: lib/Support/Triple.cpp =================================================================== --- lib/Support/Triple.cpp +++ lib/Support/Triple.cpp @@ -625,6 +625,8 @@ return Triple::ARMSubArch_v8m_baseline; case ARM::ArchKind::ARMV8MMainline: return Triple::ARMSubArch_v8m_mainline; + case ARM::ArchKind::ARMV8_1MMainline: + return Triple::ARMSubArch_v8_1m_mainline; default: return Triple::NoSubArch; } Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -498,6 +498,19 @@ "Support ARM v8.5a instructions", [HasV8_4aOps, FeatureSB]>; +def HasV8_1MMainlineOps : SubtargetFeature< + "v8.1m.main", "HasV8_1MMainlineOps", "true", + "Support ARM v8-1M Mainline instructions", + [HasV8MMainlineOps]>; +def HasMVEIntegerOps : SubtargetFeature< + "mve", "HasMVEIntegerOps", "true", + "Support M-Class Vector Extension with integer ops", + [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; +def HasMVEFloatOps : SubtargetFeature< + "mve.fp", "HasMVEFloatOps", "true", + "Support M-Class Vector Extension with integer and floating ops", + [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; + //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -783,6 +796,17 @@ FeatureAcquireRelease, FeatureMClass]>; +def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", + [HasV8_1MMainlineOps, + FeatureNoARM, + ModeThumb, + FeatureDB, + FeatureHWDivThumb, + Feature8MSecExt, + FeatureAcquireRelease, + FeatureMClass, + FeatureRAS]>; + // Aliases def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; Index: lib/Target/ARM/ARMPredicates.td =================================================================== --- lib/Target/ARM/ARMPredicates.td +++ lib/Target/ARM/ARMPredicates.td @@ -26,6 +26,15 @@ def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, AssemblerPredicate<"HasV8MMainlineOps", "armv8m.main">; +def HasV8_1MMainline : Predicate<"Subtarget->hasV8_1MMainlineOps()">, + AssemblerPredicate<"HasV8_1MMainlineOps", + "armv8.1m.main">; +def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">, + AssemblerPredicate<"HasMVEIntegerOps", + "mve">; +def HasMVEFloat : Predicate<"Subtarget->hasMVEFloatOps()">, + AssemblerPredicate<"HasMVEFloatOps", + "mve.fp">; def HasFPRegs : Predicate<"Subtarget->hasFPRegs()">, AssemblerPredicate<"FeatureFPRegs", "fp registers">; @@ -35,6 +44,9 @@ def HasFPRegs64 : Predicate<"Subtarget->hasFPRegs64()">, AssemblerPredicate<"FeatureFPRegs64", "64-bit fp registers">; +def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">, + AssemblerPredicate<"FeatureFPRegs,HasV8_1MMainlineOps", + "armv8.1m.main with FP or MVE">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate<"HasV6T2Ops", "armv6t2">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -110,7 +110,8 @@ ARMv8a, ARMv8mBaseline, ARMv8mMainline, - ARMv8r + ARMv8r, + ARMv81mMainline, }; public: @@ -157,6 +158,9 @@ bool HasV8_5aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; + bool HasV8_1MMainlineOps = false; + bool HasMVEIntegerOps = false; + bool HasMVEFloatOps = false; /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what /// floating point ISAs are supported. @@ -569,6 +573,9 @@ bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } + bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; } + bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } + bool hasMVEFloatOps() const { return HasMVEFloatOps; } bool hasFPRegs() const { return HasFPRegs; } bool hasFPRegs16() const { return HasFPRegs16; } bool hasFPRegs64() const { return HasFPRegs64; } Index: lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp +++ lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp @@ -124,7 +124,9 @@ if (STI.hasFeature(ARM::FeatureRClass)) return ARMBuildAttrs::v8_R; return ARMBuildAttrs::v8_A; - } else if (STI.hasFeature(ARM::HasV8MMainlineOps)) + } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) + return ARMBuildAttrs::v8_1_M_Main; + else if (STI.hasFeature(ARM::HasV8MMainlineOps)) return ARMBuildAttrs::v8_M_Main; else if (STI.hasFeature(ARM::HasV7Ops)) { if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) @@ -262,6 +264,11 @@ if (STI.hasFeature(ARM::FeatureMP)) emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP); + if (STI.hasFeature(ARM::HasMVEFloatOps)) + emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEIntegerAndFloat); + else if (STI.hasFeature(ARM::HasMVEIntegerOps)) + emitAttribute(ARMBuildAttrs::MVE_arch, ARMBuildAttrs::AllowMVEInteger); + // Hardware divide in ARM mode is part of base arch, starting from ARMv8. // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M). // It is not possible to produce DisallowDIV: if hwdiv is present in the base Index: test/CodeGen/ARM/build-attributes.ll =================================================================== --- test/CodeGen/ARM/build-attributes.ll +++ test/CodeGen/ARM/build-attributes.ll @@ -240,6 +240,9 @@ ; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m33 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m35p | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m35p -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi | FileCheck %s --check-prefix=ARMv81M-MAIN +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve | FileCheck %s --check-prefix=ARMv81M-MAIN-MVEINT +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=ARMv81M-MAIN-MVEFP ; CPU-SUPPORTED-NOT: is not a recognized processor for this target @@ -1769,6 +1772,12 @@ ; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format ; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use +; ARMv81M-MAIN: .eabi_attribute 6, 21 @ Tag_CPU_arch +; ARMv81M-MAIN-NOT: .eabi_attribute 48 +; ARMv81M-MAIN-MVEINT: .eabi_attribute 6, 21 @ Tag_CPU_arch +; ARMv81M-MAIN-MVEINT: .eabi_attribute 48, 1 @ Tag_MVE_arch +; ARMv81M-MAIN-MVEFP: .eabi_attribute 6, 21 @ Tag_CPU_arch +; ARMv81M-MAIN-MVEFP: .eabi_attribute 48, 2 @ Tag_MVE_arch define i32 @f(i64 %z) { ret i32 0 } Index: unittests/Support/ARMAttributeParser.cpp =================================================================== --- unittests/Support/ARMAttributeParser.cpp +++ unittests/Support/ARMAttributeParser.cpp @@ -75,6 +75,16 @@ ARMBuildAttrs::v6S_M)); EXPECT_TRUE(testBuildAttr(6, 13, ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7E_M)); + EXPECT_TRUE(testBuildAttr(6, 14, ARMBuildAttrs::CPU_arch, + ARMBuildAttrs::v8_A)); + EXPECT_TRUE(testBuildAttr(6, 15, ARMBuildAttrs::CPU_arch, + ARMBuildAttrs::v8_R)); + EXPECT_TRUE(testBuildAttr(6, 16, ARMBuildAttrs::CPU_arch, + ARMBuildAttrs::v8_M_Base)); + EXPECT_TRUE(testBuildAttr(6, 17, ARMBuildAttrs::CPU_arch, + ARMBuildAttrs::v8_M_Main)); + EXPECT_TRUE(testBuildAttr(6, 21, ARMBuildAttrs::CPU_arch, + ARMBuildAttrs::v8_1_M_Main)); } TEST(CPUArchProfileBuildAttr, testBuildAttr) { @@ -159,6 +169,16 @@ ARMBuildAttrs::AllowHPFP)); } +TEST(MVEBuildAttr, testBuildAttr) { + EXPECT_TRUE(testTagString(48, "Tag_MVE_arch")); + EXPECT_TRUE(testBuildAttr(48, 0, ARMBuildAttrs::MVE_arch, + ARMBuildAttrs::Not_Allowed)); + EXPECT_TRUE(testBuildAttr(48, 1, ARMBuildAttrs::MVE_arch, + ARMBuildAttrs::AllowMVEInteger)); + EXPECT_TRUE(testBuildAttr(48, 2, ARMBuildAttrs::MVE_arch, + ARMBuildAttrs::AllowMVEIntegerAndFloat)); +} + TEST(CPUAlignBuildAttr, testBuildAttr) { EXPECT_TRUE(testTagString(34, "Tag_CPU_unaligned_access")); EXPECT_TRUE(testBuildAttr(34, 0, ARMBuildAttrs::CPU_unaligned_access, Index: unittests/Support/TargetParserTest.cpp =================================================================== --- unittests/Support/TargetParserTest.cpp +++ unittests/Support/TargetParserTest.cpp @@ -27,7 +27,8 @@ "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8.3-a", "armv8.3a", "armv8.4-a", "armv8.4a", "armv8.5-a", "armv8.5a", "armv8-r", "armv8r", "armv8-m.base", "armv8m.base", - "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2", "xscale" + "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2", "xscale", + "armv8.1-m.main", }; bool testARMCPU(StringRef CPUName, StringRef ExpectedArch, @@ -418,6 +419,9 @@ testARMArch("armv8-m.main", "generic", "v8m.main", ARMBuildAttrs::CPUArch::v8_M_Main)); EXPECT_TRUE( + testARMArch("armv8.1-m.main", "generic", "v8.1m.main", + ARMBuildAttrs::CPUArch::v8_1_M_Main)); + EXPECT_TRUE( testARMArch("iwmmxt", "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE)); EXPECT_TRUE( @@ -569,7 +573,7 @@ unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS | ARM::AEK_FP16 | - ARM::AEK_FP16FML; + ARM::AEK_FP16FML | ARM::AEK_FP_DP; for (unsigned i = 0; i <= Extensions; i++) EXPECT_TRUE(i == 0 ? !ARM::getExtensionFeatures(i, Features) @@ -605,7 +609,9 @@ {"iwmmxt2", "noiwmmxt2", nullptr, nullptr}, {"maverick", "maverick", nullptr, nullptr}, {"xscale", "noxscale", nullptr, nullptr}, - {"sb", "nosb", "+sb", "-sb"}}; + {"sb", "nosb", "+sb", "-sb"}, + {"mve", "nomve", "+mve", "-mve"}, + {"mve.fp", "nomve.fp", "+mve.fp", "-mve.fp"}}; for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0])); @@ -628,7 +634,7 @@ "v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", "v8l", "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.4-a", - "v8.4a", "v8.5-a","v8.5a", "v8-r" + "v8.4a", "v8.5-a","v8.5a", "v8-r", "v8m.base", "v8m.main", "v8.1m.main" }; for (unsigned i = 0; i < array_lengthof(Arch); i++) { @@ -677,6 +683,7 @@ case ARM::ArchKind::ARMV7EM: case ARM::ArchKind::ARMV8MMainline: case ARM::ArchKind::ARMV8MBaseline: + case ARM::ArchKind::ARMV8_1MMainline: EXPECT_EQ(ARM::ProfileKind::M, ARM::parseArchProfile(ARMArch[i])); break; case ARM::ArchKind::ARMV7R: