diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7529,7 +7529,8 @@
 }
 
 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
-  if (VT.getVectorNumElements() == 4 &&
+  unsigned NumElts = VT.getVectorNumElements();
+  if (NumElts == 4 &&
       (VT.is128BitVector() || VT.is64BitVector())) {
     unsigned PFIndexes[4];
     for (unsigned i = 0; i != 4; ++i) {
@@ -7549,6 +7550,9 @@
       return true;
   }
 
+  if (NumElts > 1 && NumElts % 2 != 0)
+    return false;
+
   bool DummyBool;
   int DummyInt;
   unsigned DummyUnsigned;
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll b/llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-unknown-linux -o - | FileCheck %s
+
+define void @test(i32* %p1, i32* %p2) {
+; CHECK-LABEL: test:
+; CHECK-NEXT:    mov w8, #3
+; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    str w8, [x0]
+; CHECK-NEXT:    str w9, [x1]
+; CHECK-NEXT:    ret
+  %tmp = shufflevector <1 x i32> <i32 1>, <1 x i32> undef, <3 x i32> <i32 0, i32 undef, i32 undef>
+  %tmp2 = shufflevector <3 x i32> <i32 2, i32 3, i32 4>, <3 x i32> %tmp, <3 x i32> <i32 0, i32 1, i32 3>
+  %tmp3 = shufflevector <3 x i32> %tmp2, <3 x i32> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef>
+  %tmp4 = shufflevector <6 x i32> undef, <6 x i32> %tmp3, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+  %tmp6 = extractelement <9 x i32> %tmp4, i32 7
+  %tmp8 = extractelement <9 x i32> %tmp4, i32 8
+  store i32 %tmp6, i32* %p1, align 4
+  store i32 %tmp8, i32* %p2, align 4
+  ret void
+}