Index: lib/Target/AArch64/AArch64AsmPrinter.cpp =================================================================== --- lib/Target/AArch64/AArch64AsmPrinter.cpp +++ lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -17,8 +17,8 @@ #include "AArch64RegisterInfo.h" #include "AArch64Subtarget.h" #include "AArch64TargetObjectFile.h" -#include "InstPrinter/AArch64InstPrinter.h" #include "MCTargetDesc/AArch64AddressingModes.h" +#include "MCTargetDesc/AArch64InstPrinter.h" #include "MCTargetDesc/AArch64MCExpr.h" #include "MCTargetDesc/AArch64MCTargetDesc.h" #include "MCTargetDesc/AArch64TargetStreamer.h" Index: lib/Target/AArch64/CMakeLists.txt =================================================================== --- lib/Target/AArch64/CMakeLists.txt +++ lib/Target/AArch64/CMakeLists.txt @@ -68,7 +68,6 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(Utils) Index: lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h =================================================================== --- lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h +++ lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h @@ -1,222 +0,0 @@ -//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an AArch64 MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H -#define LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H - -#include "MCTargetDesc/AArch64MCTargetDesc.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCInstPrinter.h" -#include "../Utils/AArch64BaseInfo.h" - -namespace llvm { - -class AArch64InstPrinter : public MCInstPrinter { -public: - AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - - // Autogenerated by tblgen. - virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - const MCSubtargetInfo &STI, - raw_ostream &O); - - virtual StringRef getRegName(unsigned RegNo) const { - return getRegisterName(RegNo); - } - - static const char *getRegisterName(unsigned RegNo, - unsigned AltIdx = AArch64::NoRegAltName); - -protected: - bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - // Operand printers - void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - template void printImmSVE(T Value, raw_ostream &O); - void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, - raw_ostream &O); - template - void printPostIncOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printPostIncOperand(MI, OpNo, Amount, O); - } - - void printVRegOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSysCROperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddSubImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printLogicalImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printShifter(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printShiftedRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExtendedRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printArithExtend(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, - char SrcRegKind, unsigned Width); - template - void printMemExtend(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - printMemExtend(MI, OpNum, O, SrcRegKind, Width); - } - template - void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printCondCode(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printInverseCondCode(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAlignedLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, - raw_ostream &O); - void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, - raw_ostream &O); - - template - void printUImm12Offset(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - printUImm12Offset(MI, OpNum, Scale, O); - } - - template - void printAMIndexedWB(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - printAMIndexedWB(MI, OpNum, BitWidth / 8, O); - } - - void printAMNoIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - template - void printImmScale(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - template - void printPrefetchOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printPSBHintOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printBTIHintOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printFPImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printVectorList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O, - StringRef LayoutSuffix); - - /// Print a list of vector registers where the type suffix is implicit - /// (i.e. attached to the instruction rather than the registers). - void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - - template - void printTypedVectorList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printVectorIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAdrpLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printBarrierOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSystemPStateField(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printComplexRotationOp(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - template - void printImm8OptLsl(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printSVELogicalImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSVEPattern(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printSVERegOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printGPR64as32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printZPRasFPR(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printExactFPImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); -}; - -class AArch64AppleInstPrinter : public AArch64InstPrinter { -public: - AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - - void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O) override; - bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O) override; - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - const MCSubtargetInfo &STI, - raw_ostream &O) override; - - StringRef getRegName(unsigned RegNo) const override { - return getRegisterName(RegNo); - } - - static const char *getRegisterName(unsigned RegNo, - unsigned AltIdx = AArch64::NoRegAltName); -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H Index: lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp =================================================================== --- lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -1,1587 +0,0 @@ -//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an AArch64 MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "AArch64InstPrinter.h" -#include "MCTargetDesc/AArch64AddressingModes.h" -#include "Utils/AArch64BaseInfo.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/Format.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/raw_ostream.h" -#include -#include -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#define GET_INSTRUCTION_NAME -#define PRINT_ALIAS_INSTR -#include "AArch64GenAsmWriter.inc" -#define GET_INSTRUCTION_NAME -#define PRINT_ALIAS_INSTR -#include "AArch64GenAsmWriter1.inc" - -AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - -AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : AArch64InstPrinter(MAI, MII, MRI) {} - -void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - // This is for .cfi directives. - OS << getRegisterName(RegNo); -} - -void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, - const MCSubtargetInfo &STI) { - // Check for special encodings and print the canonical alias instead. - - unsigned Opcode = MI->getOpcode(); - - if (Opcode == AArch64::SYSxt) - if (printSysAlias(MI, STI, O)) { - printAnnotation(O, Annot); - return; - } - - // SBFM/UBFM should print to a nicer aliased form if possible. - if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || - Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { - const MCOperand &Op0 = MI->getOperand(0); - const MCOperand &Op1 = MI->getOperand(1); - const MCOperand &Op2 = MI->getOperand(2); - const MCOperand &Op3 = MI->getOperand(3); - - bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); - bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); - if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { - const char *AsmMnemonic = nullptr; - - switch (Op3.getImm()) { - default: - break; - case 7: - if (IsSigned) - AsmMnemonic = "sxtb"; - else if (!Is64Bit) - AsmMnemonic = "uxtb"; - break; - case 15: - if (IsSigned) - AsmMnemonic = "sxth"; - else if (!Is64Bit) - AsmMnemonic = "uxth"; - break; - case 31: - // *xtw is only valid for signed 64-bit operations. - if (Is64Bit && IsSigned) - AsmMnemonic = "sxtw"; - break; - } - - if (AsmMnemonic) { - O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) - << ", " << getRegisterName(getWRegFromXReg(Op1.getReg())); - printAnnotation(O, Annot); - return; - } - } - - // All immediate shifts are aliases, implemented using the Bitfield - // instruction. In all cases the immediate shift amount shift must be in - // the range 0 to (reg.size -1). - if (Op2.isImm() && Op3.isImm()) { - const char *AsmMnemonic = nullptr; - int shift = 0; - int64_t immr = Op2.getImm(); - int64_t imms = Op3.getImm(); - if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { - AsmMnemonic = "lsl"; - shift = 31 - imms; - } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && - ((imms + 1 == immr))) { - AsmMnemonic = "lsl"; - shift = 63 - imms; - } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { - AsmMnemonic = "lsr"; - shift = immr; - } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { - AsmMnemonic = "lsr"; - shift = immr; - } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { - AsmMnemonic = "asr"; - shift = immr; - } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { - AsmMnemonic = "asr"; - shift = immr; - } - if (AsmMnemonic) { - O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) - << ", " << getRegisterName(Op1.getReg()) << ", #" << shift; - printAnnotation(O, Annot); - return; - } - } - - // SBFIZ/UBFIZ aliases - if (Op2.getImm() > Op3.getImm()) { - O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t' - << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) - << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; - printAnnotation(O, Annot); - return; - } - - // Otherwise SBFX/UBFX is the preferred form - O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t' - << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) - << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; - printAnnotation(O, Annot); - return; - } - - if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) { - const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 - const MCOperand &Op2 = MI->getOperand(2); - int ImmR = MI->getOperand(3).getImm(); - int ImmS = MI->getOperand(4).getImm(); - - if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && - (ImmR == 0 || ImmS < ImmR)) { - // BFC takes precedence over its entire range, sligtly differently to BFI. - int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; - int LSB = (BitWidth - ImmR) % BitWidth; - int Width = ImmS + 1; - - O << "\tbfc\t" << getRegisterName(Op0.getReg()) - << ", #" << LSB << ", #" << Width; - printAnnotation(O, Annot); - return; - } else if (ImmS < ImmR) { - // BFI alias - int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; - int LSB = (BitWidth - ImmR) % BitWidth; - int Width = ImmS + 1; - - O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " - << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; - printAnnotation(O, Annot); - return; - } - - int LSB = ImmR; - int Width = ImmS - ImmR + 1; - // Otherwise BFXIL the preferred form - O << "\tbfxil\t" - << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()) - << ", #" << LSB << ", #" << Width; - printAnnotation(O, Annot); - return; - } - - // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift - // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be - // printed. - if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi || - Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && - MI->getOperand(1).isExpr()) { - if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) - O << "\tmovz\t"; - else - O << "\tmovn\t"; - - O << getRegisterName(MI->getOperand(0).getReg()) << ", #"; - MI->getOperand(1).getExpr()->print(O, &MAI); - return; - } - - if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) && - MI->getOperand(2).isExpr()) { - O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"; - MI->getOperand(2).getExpr()->print(O, &MAI); - return; - } - - // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their - // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > - // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction - // that can represent the move is the MOV alias, and the rest get printed - // normally. - if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) && - MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) { - int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; - int Shift = MI->getOperand(2).getImm(); - uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift; - - if (AArch64_AM::isMOVZMovAlias(Value, Shift, - Opcode == AArch64::MOVZXi ? 64 : 32)) { - O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #" - << formatImm(SignExtend64(Value, RegWidth)); - return; - } - } - - if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && - MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) { - int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; - int Shift = MI->getOperand(2).getImm(); - uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift); - if (RegWidth == 32) - Value = Value & 0xffffffff; - - if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { - O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #" - << formatImm(SignExtend64(Value, RegWidth)); - return; - } - } - - if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) && - (MI->getOperand(1).getReg() == AArch64::XZR || - MI->getOperand(1).getReg() == AArch64::WZR) && - MI->getOperand(2).isImm()) { - int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; - uint64_t Value = AArch64_AM::decodeLogicalImmediate( - MI->getOperand(2).getImm(), RegWidth); - if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { - O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #" - << formatImm(SignExtend64(Value, RegWidth)); - return; - } - } - - if (Opcode == AArch64::CompilerBarrier) { - O << '\t' << MAI.getCommentString() << " COMPILER BARRIER"; - printAnnotation(O, Annot); - return; - } - - // Instruction TSB is specified as a one operand instruction, but 'csync' is - // not encoded, so for printing it is treated as a special case here: - if (Opcode == AArch64::TSB) { - O << "\ttsb\tcsync"; - return; - } - - if (!printAliasInstr(MI, STI, O)) - printInstruction(MI, STI, O); - - printAnnotation(O, Annot); - - if (atomicBarrierDroppedOnZero(Opcode) && - (MI->getOperand(0).getReg() == AArch64::XZR || - MI->getOperand(0).getReg() == AArch64::WZR)) { - printAnnotation(O, "acquire semantics dropped since destination is zero"); - } -} - -static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, - bool &IsTbx) { - switch (Opcode) { - case AArch64::TBXv8i8One: - case AArch64::TBXv8i8Two: - case AArch64::TBXv8i8Three: - case AArch64::TBXv8i8Four: - IsTbx = true; - Layout = ".8b"; - return true; - case AArch64::TBLv8i8One: - case AArch64::TBLv8i8Two: - case AArch64::TBLv8i8Three: - case AArch64::TBLv8i8Four: - IsTbx = false; - Layout = ".8b"; - return true; - case AArch64::TBXv16i8One: - case AArch64::TBXv16i8Two: - case AArch64::TBXv16i8Three: - case AArch64::TBXv16i8Four: - IsTbx = true; - Layout = ".16b"; - return true; - case AArch64::TBLv16i8One: - case AArch64::TBLv16i8Two: - case AArch64::TBLv16i8Three: - case AArch64::TBLv16i8Four: - IsTbx = false; - Layout = ".16b"; - return true; - default: - return false; - } -} - -struct LdStNInstrDesc { - unsigned Opcode; - const char *Mnemonic; - const char *Layout; - int ListOperand; - bool HasLane; - int NaturalOffset; -}; - -static const LdStNInstrDesc LdStNInstInfo[] = { - { AArch64::LD1i8, "ld1", ".b", 1, true, 0 }, - { AArch64::LD1i16, "ld1", ".h", 1, true, 0 }, - { AArch64::LD1i32, "ld1", ".s", 1, true, 0 }, - { AArch64::LD1i64, "ld1", ".d", 1, true, 0 }, - { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 }, - { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 }, - { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 }, - { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 }, - { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 }, - { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 }, - { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 }, - { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 }, - { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 }, - { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 }, - { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 }, - { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 }, - { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 }, - { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 }, - { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 }, - { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 }, - { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 }, - { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 }, - { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 }, - { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 }, - { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 }, - { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 }, - { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 }, - { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 }, - { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 }, - { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 }, - { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 }, - { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 }, - { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 }, - { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 }, - { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 }, - { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 }, - { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 }, - { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 }, - { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 }, - { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 }, - { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 }, - { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 }, - { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 }, - { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 }, - { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 }, - { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 }, - { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 }, - { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 }, - { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 }, - { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 }, - { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 }, - { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 }, - { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 }, - { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 }, - { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 }, - { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 }, - { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 }, - { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 }, - { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 }, - { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 }, - { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 }, - { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 }, - { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 }, - { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 }, - { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 }, - { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 }, - { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 }, - { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 }, - { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 }, - { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 }, - { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 }, - { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 }, - { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 }, - { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 }, - { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 }, - { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 }, - { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 }, - { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 }, - { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 }, - { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 }, - { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 }, - { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 }, - { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 }, - { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 }, - { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 }, - { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 }, - { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 }, - { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 }, - { AArch64::LD2i8, "ld2", ".b", 1, true, 0 }, - { AArch64::LD2i16, "ld2", ".h", 1, true, 0 }, - { AArch64::LD2i32, "ld2", ".s", 1, true, 0 }, - { AArch64::LD2i64, "ld2", ".d", 1, true, 0 }, - { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 }, - { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 }, - { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 }, - { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 }, - { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 }, - { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 }, - { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 }, - { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 }, - { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 }, - { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 }, - { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 }, - { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 }, - { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 }, - { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 }, - { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 }, - { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 }, - { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 }, - { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 }, - { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 }, - { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 }, - { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 }, - { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 }, - { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 }, - { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 }, - { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 }, - { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 }, - { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 }, - { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 }, - { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 }, - { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 }, - { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 }, - { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 }, - { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 }, - { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 }, - { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, - { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, - { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, - { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, - { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, - { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, - { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, - { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, - { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 }, - { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 }, - { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 }, - { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 }, - { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 }, - { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 }, - { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 }, - { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 }, - { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 }, - { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 }, - { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 }, - { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 }, - { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 }, - { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 }, - { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 }, - { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 }, - { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, - { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, - { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 }, - { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 }, - { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 }, - { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 }, - { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 }, - { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 }, - { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 }, - { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 }, - { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 }, - { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 }, - { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 }, - { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 }, - { AArch64::LD4i8, "ld4", ".b", 1, true, 0 }, - { AArch64::LD4i16, "ld4", ".h", 1, true, 0 }, - { AArch64::LD4i32, "ld4", ".s", 1, true, 0 }, - { AArch64::LD4i64, "ld4", ".d", 1, true, 0 }, - { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 }, - { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 }, - { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 }, - { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 }, - { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 }, - { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 }, - { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 }, - { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 }, - { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 }, - { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 }, - { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 }, - { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 }, - { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 }, - { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }, - { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 }, - { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 }, - { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 }, - { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 }, - { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 }, - { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 }, - { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 }, - { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 }, - { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 }, - { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 }, - { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 }, - { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 }, - { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 }, - { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 }, - { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 }, - { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 }, - { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 }, - { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 }, - { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 }, - { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 }, - { AArch64::ST1i8, "st1", ".b", 0, true, 0 }, - { AArch64::ST1i16, "st1", ".h", 0, true, 0 }, - { AArch64::ST1i32, "st1", ".s", 0, true, 0 }, - { AArch64::ST1i64, "st1", ".d", 0, true, 0 }, - { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 }, - { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 }, - { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 }, - { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 }, - { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 }, - { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 }, - { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 }, - { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 }, - { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 }, - { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 }, - { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 }, - { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 }, - { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 }, - { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 }, - { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 }, - { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 }, - { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 }, - { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 }, - { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 }, - { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 }, - { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 }, - { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 }, - { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 }, - { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 }, - { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 }, - { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 }, - { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 }, - { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 }, - { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 }, - { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 }, - { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 }, - { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 }, - { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 }, - { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 }, - { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 }, - { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 }, - { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 }, - { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 }, - { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 }, - { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 }, - { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 }, - { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 }, - { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 }, - { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 }, - { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 }, - { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 }, - { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 }, - { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 }, - { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 }, - { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 }, - { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 }, - { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 }, - { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 }, - { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 }, - { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 }, - { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 }, - { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 }, - { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 }, - { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 }, - { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 }, - { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 }, - { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 }, - { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 }, - { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 }, - { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 }, - { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 }, - { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 }, - { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 }, - { AArch64::ST2i8, "st2", ".b", 0, true, 0 }, - { AArch64::ST2i16, "st2", ".h", 0, true, 0 }, - { AArch64::ST2i32, "st2", ".s", 0, true, 0 }, - { AArch64::ST2i64, "st2", ".d", 0, true, 0 }, - { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 }, - { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 }, - { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 }, - { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 }, - { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 }, - { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 }, - { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 }, - { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 }, - { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 }, - { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 }, - { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 }, - { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 }, - { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 }, - { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 }, - { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 }, - { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 }, - { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 }, - { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 }, - { AArch64::ST3i8, "st3", ".b", 0, true, 0 }, - { AArch64::ST3i16, "st3", ".h", 0, true, 0 }, - { AArch64::ST3i32, "st3", ".s", 0, true, 0 }, - { AArch64::ST3i64, "st3", ".d", 0, true, 0 }, - { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 }, - { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 }, - { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 }, - { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 }, - { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 }, - { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 }, - { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 }, - { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 }, - { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 }, - { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 }, - { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 }, - { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 }, - { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 }, - { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 }, - { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 }, - { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 }, - { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 }, - { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 }, - { AArch64::ST4i8, "st4", ".b", 0, true, 0 }, - { AArch64::ST4i16, "st4", ".h", 0, true, 0 }, - { AArch64::ST4i32, "st4", ".s", 0, true, 0 }, - { AArch64::ST4i64, "st4", ".d", 0, true, 0 }, - { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 }, - { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 }, - { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 }, - { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 }, - { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 }, - { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 }, - { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 }, - { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 }, - { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 }, - { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 }, - { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 }, - { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 }, - { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 }, - { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 }, - { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 }, - { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 }, - { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 }, - { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 }, -}; - -static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) { - unsigned Idx; - for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx) - if (LdStNInstInfo[Idx].Opcode == Opcode) - return &LdStNInstInfo[Idx]; - - return nullptr; -} - -void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, - const MCSubtargetInfo &STI) { - unsigned Opcode = MI->getOpcode(); - StringRef Layout; - - bool IsTbx; - if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) { - O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t' - << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", "; - - unsigned ListOpNum = IsTbx ? 2 : 1; - printVectorList(MI, ListOpNum, STI, O, ""); - - O << ", " - << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); - printAnnotation(O, Annot); - return; - } - - if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) { - O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t'; - - // Now onto the operands: first a vector list with possible lane - // specifier. E.g. { v0 }[2] - int OpNum = LdStDesc->ListOperand; - printVectorList(MI, OpNum++, STI, O, ""); - - if (LdStDesc->HasLane) - O << '[' << MI->getOperand(OpNum++).getImm() << ']'; - - // Next the address: [xN] - unsigned AddrReg = MI->getOperand(OpNum++).getReg(); - O << ", [" << getRegisterName(AddrReg) << ']'; - - // Finally, there might be a post-indexed offset. - if (LdStDesc->NaturalOffset != 0) { - unsigned Reg = MI->getOperand(OpNum++).getReg(); - if (Reg != AArch64::XZR) - O << ", " << getRegisterName(Reg); - else { - assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?"); - O << ", #" << LdStDesc->NaturalOffset; - } - } - - printAnnotation(O, Annot); - return; - } - - AArch64InstPrinter::printInst(MI, O, Annot, STI); -} - -bool AArch64InstPrinter::printSysAlias(const MCInst *MI, - const MCSubtargetInfo &STI, - raw_ostream &O) { -#ifndef NDEBUG - unsigned Opcode = MI->getOpcode(); - assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); -#endif - - const MCOperand &Op1 = MI->getOperand(0); - const MCOperand &Cn = MI->getOperand(1); - const MCOperand &Cm = MI->getOperand(2); - const MCOperand &Op2 = MI->getOperand(3); - - unsigned Op1Val = Op1.getImm(); - unsigned CnVal = Cn.getImm(); - unsigned CmVal = Cm.getImm(); - unsigned Op2Val = Op2.getImm(); - - uint16_t Encoding = Op2Val; - Encoding |= CmVal << 3; - Encoding |= CnVal << 7; - Encoding |= Op1Val << 11; - - bool NeedsReg; - std::string Ins; - std::string Name; - - if (CnVal == 7) { - switch (CmVal) { - default: return false; - // Maybe IC, maybe Prediction Restriction - case 1: - switch (Op1Val) { - default: return false; - case 0: goto Search_IC; - case 3: goto Search_PRCTX; - } - // Prediction Restriction aliases - case 3: { - Search_PRCTX: - const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByEncoding(Encoding >> 3); - if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits())) - return false; - - NeedsReg = PRCTX->NeedsReg; - switch (Op2Val) { - default: return false; - case 4: Ins = "cfp\t"; break; - case 5: Ins = "dvp\t"; break; - case 7: Ins = "cpp\t"; break; - } - Name = std::string(PRCTX->Name); - } - break; - // IC aliases - case 5: { - Search_IC: - const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding); - if (!IC || !IC->haveFeatures(STI.getFeatureBits())) - return false; - - NeedsReg = IC->NeedsReg; - Ins = "ic\t"; - Name = std::string(IC->Name); - } - break; - // DC aliases - case 4: case 6: case 10: case 11: case 12: case 13: case 14: - { - const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding); - if (!DC || !DC->haveFeatures(STI.getFeatureBits())) - return false; - - NeedsReg = true; - Ins = "dc\t"; - Name = std::string(DC->Name); - } - break; - // AT aliases - case 8: case 9: { - const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding); - if (!AT || !AT->haveFeatures(STI.getFeatureBits())) - return false; - - NeedsReg = true; - Ins = "at\t"; - Name = std::string(AT->Name); - } - break; - } - } else if (CnVal == 8) { - // TLBI aliases - const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding); - if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) - return false; - - NeedsReg = TLBI->NeedsReg; - Ins = "tlbi\t"; - Name = std::string(TLBI->Name); - } - else - return false; - - std::string Str = Ins + Name; - std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower); - - O << '\t' << Str; - if (NeedsReg) - O << ", " << getRegisterName(MI->getOperand(4).getReg()); - - return true; -} - -void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned Reg = Op.getReg(); - O << getRegisterName(Reg); - } else if (Op.isImm()) { - printImm(MI, OpNo, STI, O); - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - Op.getExpr()->print(O, &MAI); - } -} - -void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - O << "#" << formatImm(Op.getImm()); -} - -void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - O << format("#%#llx", Op.getImm()); -} - -void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, - unsigned Imm, raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned Reg = Op.getReg(); - if (Reg == AArch64::XZR) - O << "#" << Imm; - else - O << getRegisterName(Reg); - } else - llvm_unreachable("unknown operand kind in printPostIncOperand64"); -} - -void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - assert(Op.isReg() && "Non-register vreg operand!"); - unsigned Reg = Op.getReg(); - O << getRegisterName(Reg, AArch64::vreg); -} - -void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); - O << "c" << Op.getImm(); -} - -void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - if (MO.isImm()) { - unsigned Val = (MO.getImm() & 0xfff); - assert(Val == MO.getImm() && "Add/sub immediate out of range!"); - unsigned Shift = - AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); - O << '#' << formatImm(Val); - if (Shift != 0) - printShifter(MI, OpNum + 1, STI, O); - - if (CommentStream) - *CommentStream << '=' << formatImm(Val << Shift) << '\n'; - } else { - assert(MO.isExpr() && "Unexpected operand type!"); - MO.getExpr()->print(O, &MAI); - printShifter(MI, OpNum + 1, STI, O); - } -} - -template -void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint64_t Val = MI->getOperand(OpNum).getImm(); - O << "#0x"; - O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T))); -} - -void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNum).getImm(); - // LSL #0 should not be printed. - if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && - AArch64_AM::getShiftValue(Val) == 0) - return; - O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) - << " #" << AArch64_AM::getShiftValue(Val); -} - -void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << getRegisterName(MI->getOperand(OpNum).getReg()); - printShifter(MI, OpNum + 1, STI, O); -} - -void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << getRegisterName(MI->getOperand(OpNum).getReg()); - printArithExtend(MI, OpNum + 1, STI, O); -} - -void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNum).getImm(); - AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); - unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); - - // If the destination or first source register operand is [W]SP, print - // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at - // all. - if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { - unsigned Dest = MI->getOperand(0).getReg(); - unsigned Src1 = MI->getOperand(1).getReg(); - if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && - ExtType == AArch64_AM::UXTX) || - ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && - ExtType == AArch64_AM::UXTW) ) { - if (ShiftVal != 0) - O << ", lsl #" << ShiftVal; - return; - } - } - O << ", " << AArch64_AM::getShiftExtendName(ExtType); - if (ShiftVal != 0) - O << " #" << ShiftVal; -} - -static void printMemExtendImpl(bool SignExtend, bool DoShift, - unsigned Width, char SrcRegKind, - raw_ostream &O) { - // sxtw, sxtx, uxtw or lsl (== uxtx) - bool IsLSL = !SignExtend && SrcRegKind == 'x'; - if (IsLSL) - O << "lsl"; - else - O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind; - - if (DoShift || IsLSL) - O << " #" << Log2_32(Width / 8); -} - -void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum, - raw_ostream &O, char SrcRegKind, - unsigned Width) { - bool SignExtend = MI->getOperand(OpNum).getImm(); - bool DoShift = MI->getOperand(OpNum + 1).getImm(); - printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O); -} - -template -void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printOperand(MI, OpNum, STI, O); - if (Suffix == 's' || Suffix == 'd') - O << '.' << Suffix; - else - assert(Suffix == 0 && "Unsupported suffix size"); - - bool DoShift = ExtWidth != 8; - if (SignExtend || DoShift || SrcRegKind == 'w') { - O << ", "; - printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O); - } -} - -void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); - O << AArch64CC::getCondCodeName(CC); -} - -void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); - O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC)); -} - -void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']'; -} - -template -void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm()); -} - -void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum, - unsigned Scale, raw_ostream &O) { - const MCOperand MO = MI->getOperand(OpNum); - if (MO.isImm()) { - O << "#" << formatImm(MO.getImm() * Scale); - } else { - assert(MO.isExpr() && "Unexpected operand type!"); - MO.getExpr()->print(O, &MAI); - } -} - -void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, - unsigned Scale, raw_ostream &O) { - const MCOperand MO1 = MI->getOperand(OpNum + 1); - O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()); - if (MO1.isImm()) { - O << ", #" << formatImm(MO1.getImm() * Scale); - } else { - assert(MO1.isExpr() && "Unexpected operand type!"); - O << ", "; - MO1.getExpr()->print(O, &MAI); - } - O << ']'; -} - -template -void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned prfop = MI->getOperand(OpNum).getImm(); - if (IsSVEPrefetch) { - if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) { - O << PRFM->Name; - return; - } - } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) { - O << PRFM->Name; - return; - } - - O << '#' << formatImm(prfop); -} - -void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned psbhintop = MI->getOperand(OpNum).getImm(); - auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop); - if (PSB) - O << PSB->Name; - else - O << '#' << formatImm(psbhintop); -} - -void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned btihintop = (MI->getOperand(OpNum).getImm() ^ 32) >> 1; - auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop); - if (BTI) - O << BTI->Name; - else - O << '#' << formatImm(btihintop); -} - -void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - float FPImm = - MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm()); - - // 8 decimal places are enough to perfectly represent permitted floats. - O << format("#%.8f", FPImm); -} - -static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { - while (Stride--) { - switch (Reg) { - default: - llvm_unreachable("Vector register expected!"); - case AArch64::Q0: Reg = AArch64::Q1; break; - case AArch64::Q1: Reg = AArch64::Q2; break; - case AArch64::Q2: Reg = AArch64::Q3; break; - case AArch64::Q3: Reg = AArch64::Q4; break; - case AArch64::Q4: Reg = AArch64::Q5; break; - case AArch64::Q5: Reg = AArch64::Q6; break; - case AArch64::Q6: Reg = AArch64::Q7; break; - case AArch64::Q7: Reg = AArch64::Q8; break; - case AArch64::Q8: Reg = AArch64::Q9; break; - case AArch64::Q9: Reg = AArch64::Q10; break; - case AArch64::Q10: Reg = AArch64::Q11; break; - case AArch64::Q11: Reg = AArch64::Q12; break; - case AArch64::Q12: Reg = AArch64::Q13; break; - case AArch64::Q13: Reg = AArch64::Q14; break; - case AArch64::Q14: Reg = AArch64::Q15; break; - case AArch64::Q15: Reg = AArch64::Q16; break; - case AArch64::Q16: Reg = AArch64::Q17; break; - case AArch64::Q17: Reg = AArch64::Q18; break; - case AArch64::Q18: Reg = AArch64::Q19; break; - case AArch64::Q19: Reg = AArch64::Q20; break; - case AArch64::Q20: Reg = AArch64::Q21; break; - case AArch64::Q21: Reg = AArch64::Q22; break; - case AArch64::Q22: Reg = AArch64::Q23; break; - case AArch64::Q23: Reg = AArch64::Q24; break; - case AArch64::Q24: Reg = AArch64::Q25; break; - case AArch64::Q25: Reg = AArch64::Q26; break; - case AArch64::Q26: Reg = AArch64::Q27; break; - case AArch64::Q27: Reg = AArch64::Q28; break; - case AArch64::Q28: Reg = AArch64::Q29; break; - case AArch64::Q29: Reg = AArch64::Q30; break; - case AArch64::Q30: Reg = AArch64::Q31; break; - // Vector lists can wrap around. - case AArch64::Q31: - Reg = AArch64::Q0; - break; - case AArch64::Z0: Reg = AArch64::Z1; break; - case AArch64::Z1: Reg = AArch64::Z2; break; - case AArch64::Z2: Reg = AArch64::Z3; break; - case AArch64::Z3: Reg = AArch64::Z4; break; - case AArch64::Z4: Reg = AArch64::Z5; break; - case AArch64::Z5: Reg = AArch64::Z6; break; - case AArch64::Z6: Reg = AArch64::Z7; break; - case AArch64::Z7: Reg = AArch64::Z8; break; - case AArch64::Z8: Reg = AArch64::Z9; break; - case AArch64::Z9: Reg = AArch64::Z10; break; - case AArch64::Z10: Reg = AArch64::Z11; break; - case AArch64::Z11: Reg = AArch64::Z12; break; - case AArch64::Z12: Reg = AArch64::Z13; break; - case AArch64::Z13: Reg = AArch64::Z14; break; - case AArch64::Z14: Reg = AArch64::Z15; break; - case AArch64::Z15: Reg = AArch64::Z16; break; - case AArch64::Z16: Reg = AArch64::Z17; break; - case AArch64::Z17: Reg = AArch64::Z18; break; - case AArch64::Z18: Reg = AArch64::Z19; break; - case AArch64::Z19: Reg = AArch64::Z20; break; - case AArch64::Z20: Reg = AArch64::Z21; break; - case AArch64::Z21: Reg = AArch64::Z22; break; - case AArch64::Z22: Reg = AArch64::Z23; break; - case AArch64::Z23: Reg = AArch64::Z24; break; - case AArch64::Z24: Reg = AArch64::Z25; break; - case AArch64::Z25: Reg = AArch64::Z26; break; - case AArch64::Z26: Reg = AArch64::Z27; break; - case AArch64::Z27: Reg = AArch64::Z28; break; - case AArch64::Z28: Reg = AArch64::Z29; break; - case AArch64::Z29: Reg = AArch64::Z30; break; - case AArch64::Z30: Reg = AArch64::Z31; break; - // Vector lists can wrap around. - case AArch64::Z31: - Reg = AArch64::Z0; - break; - } - } - return Reg; -} - -template -void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - static_assert(size == 64 || size == 32, - "Template parameter must be either 32 or 64"); - unsigned Reg = MI->getOperand(OpNum).getReg(); - - unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; - unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; - - unsigned Even = MRI.getSubReg(Reg, Sube); - unsigned Odd = MRI.getSubReg(Reg, Subo); - O << getRegisterName(Even) << ", " << getRegisterName(Odd); -} - -void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O, - StringRef LayoutSuffix) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - - O << "{ "; - - // Work out how many registers there are in the list (if there is an actual - // list). - unsigned NumRegs = 1; - if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) - NumRegs = 2; - else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) - NumRegs = 3; - else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) - NumRegs = 4; - - // Now forget about the list and find out what the first register is. - if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) - Reg = FirstReg; - else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) - Reg = FirstReg; - else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) - Reg = FirstReg; - - // If it's a D-reg, we need to promote it to the equivalent Q-reg before - // printing (otherwise getRegisterName fails). - if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { - const MCRegisterClass &FPR128RC = - MRI.getRegClass(AArch64::FPR128RegClassID); - Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); - } - - for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { - if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg)) - O << getRegisterName(Reg) << LayoutSuffix; - else - O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix; - - if (i + 1 != NumRegs) - O << ", "; - } - - O << " }"; -} - -void -AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printVectorList(MI, OpNum, STI, O, ""); -} - -template -void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - std::string Suffix("."); - if (NumLanes) - Suffix += itostr(NumLanes) + LaneKind; - else - Suffix += LaneKind; - - printVectorList(MI, OpNum, STI, O, Suffix); -} - -void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "[" << MI->getOperand(OpNum).getImm() << "]"; -} - -void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - - // If the label has already been resolved to an immediate offset (say, when - // we're running the disassembler), just print the immediate. - if (Op.isImm()) { - O << "#" << formatImm(Op.getImm() * 4); - return; - } - - // If the branch target is simply an address then print it in hex. - const MCConstantExpr *BranchTarget = - dyn_cast(MI->getOperand(OpNum).getExpr()); - int64_t Address; - if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { - O << "0x"; - O.write_hex(Address); - } else { - // Otherwise, just print the expression. - MI->getOperand(OpNum).getExpr()->print(O, &MAI); - } -} - -void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - - // If the label has already been resolved to an immediate offset (say, when - // we're running the disassembler), just print the immediate. - if (Op.isImm()) { - O << "#" << formatImm(Op.getImm() * (1 << 12)); - return; - } - - // Otherwise, just print the expression. - MI->getOperand(OpNum).getExpr()->print(O, &MAI); -} - -void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - unsigned Opcode = MI->getOpcode(); - - StringRef Name; - if (Opcode == AArch64::ISB) { - auto ISB = AArch64ISB::lookupISBByEncoding(Val); - Name = ISB ? ISB->Name : ""; - } else if (Opcode == AArch64::TSB) { - auto TSB = AArch64TSB::lookupTSBByEncoding(Val); - Name = TSB ? TSB->Name : ""; - } else { - auto DB = AArch64DB::lookupDBByEncoding(Val); - Name = DB ? DB->Name : ""; - } - if (!Name.empty()) - O << Name; - else - O << "#" << Val; -} - -void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - - // Horrible hack for the one register that has identical encodings but - // different names in MSR and MRS. Because of this, one of MRS and MSR is - // going to get the wrong entry - if (Val == AArch64SysReg::DBGDTRRX_EL0) { - O << "DBGDTRRX_EL0"; - return; - } - - const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); - if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) - O << Reg->Name; - else - O << AArch64SysReg::genericRegisterString(Val); -} - -void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - - // Horrible hack for the one register that has identical encodings but - // different names in MSR and MRS. Because of this, one of MRS and MSR is - // going to get the wrong entry - if (Val == AArch64SysReg::DBGDTRTX_EL0) { - O << "DBGDTRTX_EL0"; - return; - } - - const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); - if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) - O << Reg->Name; - else - O << AArch64SysReg::genericRegisterString(Val); -} - -void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - - auto PState = AArch64PState::lookupPStateByEncoding(Val); - if (PState && PState->haveFeatures(STI.getFeatureBits())) - O << PState->Name; - else - O << "#" << formatImm(Val); -} - -void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned RawVal = MI->getOperand(OpNo).getImm(); - uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal); - O << format("#%#016llx", Val); -} - -template -void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - O << "#" << (Val * Angle) + Remainder; -} - -void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNum).getImm(); - if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val)) - O << Pat->Name; - else - O << '#' << formatImm(Val); -} - -template -void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - switch (suffix) { - case 0: - case 'b': - case 'h': - case 's': - case 'd': - case 'q': - break; - default: llvm_unreachable("Invalid kind specifier."); - } - - unsigned Reg = MI->getOperand(OpNum).getReg(); - O << getRegisterName(Reg); - if (suffix != 0) - O << '.' << suffix; -} - -template -void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) { - typename std::make_unsigned::type HexValue = Value; - - if (getPrintImmHex()) - O << '#' << formatHex((uint64_t)HexValue); - else - O << '#' << formatDec(Value); - - if (CommentStream) { - // Do the opposite to that used for instruction operands. - if (getPrintImmHex()) - *CommentStream << '=' << formatDec(HexValue) << '\n'; - else - *CommentStream << '=' << formatHex((uint64_t)Value) << '\n'; - } -} - -template -void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned UnscaledVal = MI->getOperand(OpNum).getImm(); - unsigned Shift = MI->getOperand(OpNum + 1).getImm(); - assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && - "Unexepected shift type!"); - - // #0 lsl #8 is never pretty printed - if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) { - O << '#' << formatImm(UnscaledVal); - printShifter(MI, OpNum + 1, STI, O); - return; - } - - T Val; - if (std::is_signed()) - Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); - else - Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); - - printImmSVE(Val, O); -} - -template -void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - typedef typename std::make_signed::type SignedT; - typedef typename std::make_unsigned::type UnsignedT; - - uint64_t Val = MI->getOperand(OpNum).getImm(); - UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64); - - // Prefer the default format for 16bit values, hex otherwise. - if ((int16_t)PrintVal == (SignedT)PrintVal) - printImmSVE((T)PrintVal, O); - else if ((uint16_t)PrintVal == PrintVal) - printImmSVE(PrintVal, O); - else - O << '#' << formatHex((uint64_t)PrintVal); -} - -template -void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Base; - switch (Width) { - case 8: Base = AArch64::B0; break; - case 16: Base = AArch64::H0; break; - case 32: Base = AArch64::S0; break; - case 64: Base = AArch64::D0; break; - case 128: Base = AArch64::Q0; break; - default: - llvm_unreachable("Unsupported width"); - } - unsigned Reg = MI->getOperand(OpNum).getReg(); - O << getRegisterName(Reg - AArch64::Z0 + Base); -} - -template -void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0); - auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1); - unsigned Val = MI->getOperand(OpNum).getImm(); - O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr); -} - -void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - O << getRegisterName(getWRegFromXReg(Reg)); -} Index: lib/Target/AArch64/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/AArch64/InstPrinter/CMakeLists.txt +++ lib/Target/AArch64/InstPrinter/CMakeLists.txt @@ -1,7 +0,0 @@ -include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) - -add_llvm_library(LLVMAArch64AsmPrinter - AArch64InstPrinter.cpp - ) - -add_dependencies(LLVMAArch64AsmPrinter AArch64CommonTableGen) Index: lib/Target/AArch64/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/AArch64/InstPrinter/LLVMBuild.txt +++ lib/Target/AArch64/InstPrinter/LLVMBuild.txt @@ -1,23 +0,0 @@ -;===- ./lib/Target/AArch64/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = AArch64AsmPrinter -parent = AArch64 -required_libraries = AArch64Utils MC Support -add_to_library_groups = AArch64 - Index: lib/Target/AArch64/LLVMBuild.txt =================================================================== --- lib/Target/AArch64/LLVMBuild.txt +++ lib/Target/AArch64/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo Utils [component_0] type = TargetGroup @@ -30,5 +30,5 @@ type = Library name = AArch64CodeGen parent = AArch64 -required_libraries = AArch64AsmPrinter AArch64Desc AArch64Info AArch64Utils Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel +required_libraries = AArch64Desc AArch64Info AArch64Utils Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel add_to_library_groups = AArch64 Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -14,8 +14,8 @@ #include "AArch64ELFStreamer.h" #include "AArch64MCAsmInfo.h" #include "AArch64WinCOFFStreamer.h" -#include "InstPrinter/AArch64InstPrinter.h" #include "MCTargetDesc/AArch64AddressingModes.h" +#include "MCTargetDesc/AArch64InstPrinter.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInstrAnalysis.h" Index: lib/Target/AArch64/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/AArch64/MCTargetDesc/CMakeLists.txt +++ lib/Target/AArch64/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ AArch64AsmBackend.cpp AArch64ELFObjectWriter.cpp AArch64ELFStreamer.cpp + AArch64InstPrinter.cpp AArch64MCAsmInfo.cpp AArch64MCCodeEmitter.cpp AArch64MCExpr.cpp Index: lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt +++ lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt @@ -18,6 +18,6 @@ type = Library name = AArch64Desc parent = AArch64 -required_libraries = AArch64AsmPrinter AArch64Info MC Support +required_libraries = AArch64Info AArch64Utils MC Support add_to_library_groups = AArch64 Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -19,7 +19,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" -#include "InstPrinter/AMDGPUInstPrinter.h" +#include "MCTargetDesc/AMDGPUInstPrinter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUTargetStreamer.h" #include "R600AsmPrinter.h" Index: lib/Target/AMDGPU/AMDGPUMCInstLower.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -15,7 +15,7 @@ #include "AMDGPUAsmPrinter.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" -#include "InstPrinter/AMDGPUInstPrinter.h" +#include "MCTargetDesc/AMDGPUInstPrinter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "R600AsmPrinter.h" #include "SIInstrInfo.h" Index: lib/Target/AMDGPU/CMakeLists.txt =================================================================== --- lib/Target/AMDGPU/CMakeLists.txt +++ lib/Target/AMDGPU/CMakeLists.txt @@ -122,7 +122,6 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(Utils) Index: lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h =================================================================== --- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h +++ lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h @@ -1,251 +0,0 @@ -//===-- AMDGPUInstPrinter.h - AMDGPU MC Inst -> ASM interface ---*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -/// \file -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_AMDGPU_INSTPRINTER_AMDGPUINSTPRINTER_H -#define LLVM_LIB_TARGET_AMDGPU_INSTPRINTER_AMDGPUINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class AMDGPUInstPrinter : public MCInstPrinter { -public: - AMDGPUInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - //Autogenerated by tblgen - void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - static void printRegOperand(unsigned RegNo, raw_ostream &O, - const MCRegisterInfo &MRI); - -private: - void printU4ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU16ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printS13ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU32ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O, - StringRef BitName); - void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOffsetS13(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - - void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printSMRDOffset8(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSMRDOffset20(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printGLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printSLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printUNorm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printLWE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printD16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpCompr(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpVM(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFORMAT(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printRegOperand(unsigned RegNo, raw_ostream &O); - void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printVINTRPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImmediate16(uint32_t Imm, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImmediateV216(uint32_t Imm, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI, - raw_ostream &O); - void printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printRowMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printBoundCtrl(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printSDWADstSel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSDWADstUnused(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod, - raw_ostream &O); - void printOpSel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printOpSelHi(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printNegLo(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printNegHi(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printInterpSlot(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printInterpAttr(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printInterpAttrChan(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printVGPRIndexMode(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printMemOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - - - template - void printExpSrcN(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpSrc0(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpSrc1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpSrc2(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpSrc3(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printExpTgt(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - -public: - static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, - StringRef Asm, StringRef Default = ""); - static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, - char Asm); -protected: - void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printLiteral(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printLast(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printNeg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOMOD(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printUpdateExecMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printUpdatePred(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printWrite(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printBankSwizzle(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printRSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printCT(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printKCache(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printWaitFlag(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); -}; - -class R600InstPrinter : public MCInstPrinter { -public: - R600InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O); -}; - -} // End namespace llvm - -#endif Index: lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp =================================================================== --- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -1,1445 +0,0 @@ -//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// \file -//===----------------------------------------------------------------------===// - -#include "AMDGPUInstPrinter.h" -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" -#include "SIDefines.h" -#include "Utils/AMDGPUAsmUtils.h" -#include "Utils/AMDGPUBaseInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/raw_ostream.h" -#include - -using namespace llvm; -using namespace llvm::AMDGPU; - -void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annot, const MCSubtargetInfo &STI) { - OS.flush(); - printInstruction(MI, STI, OS); - printAnnotation(OS, Annot); -} - -void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); -} - -void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); -} - -void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // It's possible to end up with a 32-bit literal used with a 16-bit operand - // with ignored high bits. Print as 32-bit anyway in that case. - int64_t Imm = MI->getOperand(OpNo).getImm(); - if (isInt<16>(Imm) || isUInt<16>(Imm)) - O << formatHex(static_cast(Imm & 0xffff)); - else - printU32ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); -} - -void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); -} - -void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); -} - -void AMDGPUInstPrinter::printS13ImmDecOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm())); -} - -void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); -} - -void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, - raw_ostream &O, StringRef BitName) { - if (MI->getOperand(OpNo).getImm()) { - O << ' ' << BitName; - } -} - -void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "offen"); -} - -void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "idxen"); -} - -void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printNamedBit(MI, OpNo, O, "addr64"); -} - -void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) { - O << " offset:"; - printU16ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint16_t Imm = MI->getOperand(OpNo).getImm(); - if (Imm != 0) { - O << ((OpNo == 0)? "offset:" : " offset:"); - printU16ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint16_t Imm = MI->getOperand(OpNo).getImm(); - if (Imm != 0) { - O << ((OpNo == 0)? "offset:" : " offset:"); - printS13ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) { - O << " offset0:"; - printU8ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) { - O << " offset1:"; - printU8ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printU32ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printSMRDOffset20(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printU32ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printU32ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "gds"); -} - -void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "glc"); -} - -void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "slc"); -} - -void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "tfe"); -} - -void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) { - O << " dmask:"; - printU16ImmOperand(MI, OpNo, STI, O); - } -} - -void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "unorm"); -} - -void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "da"); -} - -void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - if (STI.hasFeature(AMDGPU::FeatureR128A16)) - printNamedBit(MI, OpNo, O, "a16"); - else - printNamedBit(MI, OpNo, O, "r128"); -} - -void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "lwe"); -} - -void AMDGPUInstPrinter::printD16(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - printNamedBit(MI, OpNo, O, "d16"); -} - -void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) - O << " compr"; -} - -void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) - O << " vm"; -} - -void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (unsigned Val = MI->getOperand(OpNo).getImm()) { - O << " dfmt:" << (Val & 15); - O << ", nfmt:" << (Val >> 4); - } -} - -void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, - const MCRegisterInfo &MRI) { - switch (RegNo) { - case AMDGPU::VCC: - O << "vcc"; - return; - case AMDGPU::SCC: - O << "scc"; - return; - case AMDGPU::EXEC: - O << "exec"; - return; - case AMDGPU::M0: - O << "m0"; - return; - case AMDGPU::FLAT_SCR: - O << "flat_scratch"; - return; - case AMDGPU::XNACK_MASK: - O << "xnack_mask"; - return; - case AMDGPU::SRC_SHARED_BASE: - O << "src_shared_base"; - return; - case AMDGPU::SRC_SHARED_LIMIT: - O << "src_shared_limit"; - return; - case AMDGPU::SRC_PRIVATE_BASE: - O << "src_private_base"; - return; - case AMDGPU::SRC_PRIVATE_LIMIT: - O << "src_private_limit"; - return; - case AMDGPU::SRC_POPS_EXITING_WAVE_ID: - O << "src_pops_exiting_wave_id"; - return; - case AMDGPU::LDS_DIRECT: - O << "src_lds_direct"; - return; - case AMDGPU::VCC_LO: - O << "vcc_lo"; - return; - case AMDGPU::VCC_HI: - O << "vcc_hi"; - return; - case AMDGPU::TBA_LO: - O << "tba_lo"; - return; - case AMDGPU::TBA_HI: - O << "tba_hi"; - return; - case AMDGPU::TMA_LO: - O << "tma_lo"; - return; - case AMDGPU::TMA_HI: - O << "tma_hi"; - return; - case AMDGPU::EXEC_LO: - O << "exec_lo"; - return; - case AMDGPU::EXEC_HI: - O << "exec_hi"; - return; - case AMDGPU::FLAT_SCR_LO: - O << "flat_scratch_lo"; - return; - case AMDGPU::FLAT_SCR_HI: - O << "flat_scratch_hi"; - return; - case AMDGPU::XNACK_MASK_LO: - O << "xnack_mask_lo"; - return; - case AMDGPU::XNACK_MASK_HI: - O << "xnack_mask_hi"; - return; - case AMDGPU::FP_REG: - case AMDGPU::SP_REG: - case AMDGPU::SCRATCH_WAVE_OFFSET_REG: - case AMDGPU::PRIVATE_RSRC_REG: - llvm_unreachable("pseudo-register should not ever be emitted"); - default: - break; - } - - // The low 8 bits of the encoding value is the register index, for both VGPRs - // and SGPRs. - unsigned RegIdx = MRI.getEncodingValue(RegNo) & ((1 << 8) - 1); - - unsigned NumRegs; - if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 1; - } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)) { - O << 's'; - NumRegs = 1; - } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)) { - O <<'v'; - NumRegs = 2; - } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)) { - O << 's'; - NumRegs = 2; - } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 4; - } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo)) { - O << 's'; - NumRegs = 4; - } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 3; - } else if (MRI.getRegClass(AMDGPU::VReg_160RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 5; - } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 8; - } else if (MRI.getRegClass(AMDGPU::SGPR_256RegClassID).contains(RegNo)) { - O << 's'; - NumRegs = 8; - } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)) { - O << 'v'; - NumRegs = 16; - } else if (MRI.getRegClass(AMDGPU::SGPR_512RegClassID).contains(RegNo)) { - O << 's'; - NumRegs = 16; - } else { - O << getRegisterName(RegNo); - return; - } - - if (NumRegs == 1) { - O << RegIdx; - return; - } - - O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; -} - -void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) - O << "_e64 "; - else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP) - O << "_dpp "; - else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA) - O << "_sdwa "; - else - O << "_e32 "; - - printOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) - O << " "; - else - O << "_e32 "; - - printOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int16_t SImm = static_cast(Imm); - if (SImm >= -16 && SImm <= 64) { - O << SImm; - return; - } - - if (Imm == 0x3C00) - O<< "1.0"; - else if (Imm == 0xBC00) - O<< "-1.0"; - else if (Imm == 0x3800) - O<< "0.5"; - else if (Imm == 0xB800) - O<< "-0.5"; - else if (Imm == 0x4000) - O<< "2.0"; - else if (Imm == 0xC000) - O<< "-2.0"; - else if (Imm == 0x4400) - O<< "4.0"; - else if (Imm == 0xC400) - O<< "-4.0"; - else if (Imm == 0x3118) { - assert(STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]); - O << "0.15915494"; - } else - O << formatHex(static_cast(Imm)); -} - -void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint16_t Lo16 = static_cast(Imm); - printImmediate16(Lo16, STI, O); -} - -void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int32_t SImm = static_cast(Imm); - if (SImm >= -16 && SImm <= 64) { - O << SImm; - return; - } - - if (Imm == FloatToBits(0.0f)) - O << "0.0"; - else if (Imm == FloatToBits(1.0f)) - O << "1.0"; - else if (Imm == FloatToBits(-1.0f)) - O << "-1.0"; - else if (Imm == FloatToBits(0.5f)) - O << "0.5"; - else if (Imm == FloatToBits(-0.5f)) - O << "-0.5"; - else if (Imm == FloatToBits(2.0f)) - O << "2.0"; - else if (Imm == FloatToBits(-2.0f)) - O << "-2.0"; - else if (Imm == FloatToBits(4.0f)) - O << "4.0"; - else if (Imm == FloatToBits(-4.0f)) - O << "-4.0"; - else if (Imm == 0x3e22f983 && - STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) - O << "0.15915494"; - else - O << formatHex(static_cast(Imm)); -} - -void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int64_t SImm = static_cast(Imm); - if (SImm >= -16 && SImm <= 64) { - O << SImm; - return; - } - - if (Imm == DoubleToBits(0.0)) - O << "0.0"; - else if (Imm == DoubleToBits(1.0)) - O << "1.0"; - else if (Imm == DoubleToBits(-1.0)) - O << "-1.0"; - else if (Imm == DoubleToBits(0.5)) - O << "0.5"; - else if (Imm == DoubleToBits(-0.5)) - O << "-0.5"; - else if (Imm == DoubleToBits(2.0)) - O << "2.0"; - else if (Imm == DoubleToBits(-2.0)) - O << "-2.0"; - else if (Imm == DoubleToBits(4.0)) - O << "4.0"; - else if (Imm == DoubleToBits(-4.0)) - O << "-4.0"; - else if (Imm == 0x3fc45f306dc9c882 && - STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) - O << "0.15915494309189532"; - else { - assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882); - - // In rare situations, we will have a 32-bit literal in a 64-bit - // operand. This is technically allowed for the encoding of s_mov_b64. - O << formatHex(static_cast(Imm)); - } -} - -void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (OpNo >= MI->getNumOperands()) { - O << "/*Missing OP" << OpNo << "*/"; - return; - } - - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - printRegOperand(Op.getReg(), O, MRI); - } else if (Op.isImm()) { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - switch (Desc.OpInfo[OpNo].OperandType) { - case AMDGPU::OPERAND_REG_IMM_INT32: - case AMDGPU::OPERAND_REG_IMM_FP32: - case AMDGPU::OPERAND_REG_INLINE_C_INT32: - case AMDGPU::OPERAND_REG_INLINE_C_FP32: - case MCOI::OPERAND_IMMEDIATE: - printImmediate32(Op.getImm(), STI, O); - break; - case AMDGPU::OPERAND_REG_IMM_INT64: - case AMDGPU::OPERAND_REG_IMM_FP64: - case AMDGPU::OPERAND_REG_INLINE_C_INT64: - case AMDGPU::OPERAND_REG_INLINE_C_FP64: - printImmediate64(Op.getImm(), STI, O); - break; - case AMDGPU::OPERAND_REG_INLINE_C_INT16: - case AMDGPU::OPERAND_REG_INLINE_C_FP16: - case AMDGPU::OPERAND_REG_IMM_INT16: - case AMDGPU::OPERAND_REG_IMM_FP16: - printImmediate16(Op.getImm(), STI, O); - break; - case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: - case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: - printImmediateV216(Op.getImm(), STI, O); - break; - case MCOI::OPERAND_UNKNOWN: - case MCOI::OPERAND_PCREL: - O << formatDec(Op.getImm()); - break; - case MCOI::OPERAND_REGISTER: - // FIXME: This should be removed and handled somewhere else. Seems to come - // from a disassembler bug. - O << "/*invalid immediate*/"; - break; - default: - // We hit this for the immediate instruction bits that don't yet have a - // custom printer. - llvm_unreachable("unexpected immediate operand type"); - } - } else if (Op.isFPImm()) { - // We special case 0.0 because otherwise it will be printed as an integer. - if (Op.getFPImm() == 0.0) - O << "0.0"; - else { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - int RCID = Desc.OpInfo[OpNo].RegClass; - unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); - if (RCBits == 32) - printImmediate32(FloatToBits(Op.getFPImm()), STI, O); - else if (RCBits == 64) - printImmediate64(DoubleToBits(Op.getFPImm()), STI, O); - else - llvm_unreachable("Invalid register class size"); - } - } else if (Op.isExpr()) { - const MCExpr *Exp = Op.getExpr(); - Exp->print(O, &MAI); - } else { - O << "/*INV_OP*/"; - } -} - -void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI, - unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned InputModifiers = MI->getOperand(OpNo).getImm(); - - // Use 'neg(...)' instead of '-' to avoid ambiguity. - // This is important for integer literals because - // -1 is not the same value as neg(1). - bool NegMnemo = false; - - if (InputModifiers & SISrcMods::NEG) { - if (OpNo + 1 < MI->getNumOperands() && - (InputModifiers & SISrcMods::ABS) == 0) { - const MCOperand &Op = MI->getOperand(OpNo + 1); - NegMnemo = Op.isImm() || Op.isFPImm(); - } - if (NegMnemo) { - O << "neg("; - } else { - O << '-'; - } - } - - if (InputModifiers & SISrcMods::ABS) - O << '|'; - printOperand(MI, OpNo + 1, STI, O); - if (InputModifiers & SISrcMods::ABS) - O << '|'; - - if (NegMnemo) { - O << ')'; - } -} - -void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, - unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned InputModifiers = MI->getOperand(OpNo).getImm(); - if (InputModifiers & SISrcMods::SEXT) - O << "sext("; - printOperand(MI, OpNo + 1, STI, O); - if (InputModifiers & SISrcMods::SEXT) - O << ')'; -} - -void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - using namespace AMDGPU::DPP; - - unsigned Imm = MI->getOperand(OpNo).getImm(); - if (Imm <= DppCtrl::QUAD_PERM_LAST) { - O << " quad_perm:["; - O << formatDec(Imm & 0x3) << ','; - O << formatDec((Imm & 0xc) >> 2) << ','; - O << formatDec((Imm & 0x30) >> 4) << ','; - O << formatDec((Imm & 0xc0) >> 6) << ']'; - } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && - (Imm <= DppCtrl::ROW_SHL_LAST)) { - O << " row_shl:"; - printU4ImmDecOperand(MI, OpNo, O); - } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && - (Imm <= DppCtrl::ROW_SHR_LAST)) { - O << " row_shr:"; - printU4ImmDecOperand(MI, OpNo, O); - } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && - (Imm <= DppCtrl::ROW_ROR_LAST)) { - O << " row_ror:"; - printU4ImmDecOperand(MI, OpNo, O); - } else if (Imm == DppCtrl::WAVE_SHL1) { - O << " wave_shl:1"; - } else if (Imm == DppCtrl::WAVE_ROL1) { - O << " wave_rol:1"; - } else if (Imm == DppCtrl::WAVE_SHR1) { - O << " wave_shr:1"; - } else if (Imm == DppCtrl::WAVE_ROR1) { - O << " wave_ror:1"; - } else if (Imm == DppCtrl::ROW_MIRROR) { - O << " row_mirror"; - } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { - O << " row_half_mirror"; - } else if (Imm == DppCtrl::BCAST15) { - O << " row_bcast:15"; - } else if (Imm == DppCtrl::BCAST31) { - O << " row_bcast:31"; - } else { - O << " /* Invalid dpp_ctrl value */"; - } -} - -void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " row_mask:"; - printU4ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " bank_mask:"; - printU4ImmOperand(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNo).getImm(); - if (Imm) { - O << " bound_ctrl:0"; // XXX - this syntax is used in sp3 - } -} - -void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - using namespace llvm::AMDGPU::SDWA; - - unsigned Imm = MI->getOperand(OpNo).getImm(); - switch (Imm) { - case SdwaSel::BYTE_0: O << "BYTE_0"; break; - case SdwaSel::BYTE_1: O << "BYTE_1"; break; - case SdwaSel::BYTE_2: O << "BYTE_2"; break; - case SdwaSel::BYTE_3: O << "BYTE_3"; break; - case SdwaSel::WORD_0: O << "WORD_0"; break; - case SdwaSel::WORD_1: O << "WORD_1"; break; - case SdwaSel::DWORD: O << "DWORD"; break; - default: llvm_unreachable("Invalid SDWA data select operand"); - } -} - -void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "dst_sel:"; - printSDWASel(MI, OpNo, O); -} - -void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "src0_sel:"; - printSDWASel(MI, OpNo, O); -} - -void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "src1_sel:"; - printSDWASel(MI, OpNo, O); -} - -void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - using namespace llvm::AMDGPU::SDWA; - - O << "dst_unused:"; - unsigned Imm = MI->getOperand(OpNo).getImm(); - switch (Imm) { - case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break; - case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break; - case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break; - default: llvm_unreachable("Invalid SDWA dest_unused operand"); - } -} - -template -void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Opc = MI->getOpcode(); - int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); - unsigned En = MI->getOperand(EnIdx).getImm(); - - int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); - - // If compr is set, print as src0, src0, src1, src1 - if (MI->getOperand(ComprIdx).getImm()) { - if (N == 1 || N == 2) - --OpNo; - else if (N == 3) - OpNo -= 2; - } - - if (En & (1 << N)) - printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); - else - O << "off"; -} - -void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printExpSrcN<0>(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printExpSrcN<1>(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printExpSrcN<2>(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printExpSrcN<3>(MI, OpNo, STI, O); -} - -void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // This is really a 6 bit field. - uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); - - if (Tgt <= 7) - O << " mrt" << Tgt; - else if (Tgt == 8) - O << " mrtz"; - else if (Tgt == 9) - O << " null"; - else if (Tgt >= 12 && Tgt <= 15) - O << " pos" << Tgt - 12; - else if (Tgt >= 32 && Tgt <= 63) - O << " param" << Tgt - 32; - else { - // Reserved values 10, 11 - O << " invalid_target_" << Tgt; - } -} - -static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod, - bool IsPacked, bool HasDstSel) { - int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1); - - for (int I = 0; I < NumOps; ++I) { - if (!!(Ops[I] & Mod) != DefaultValue) - return false; - } - - if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0) - return false; - - return true; -} - -void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, - StringRef Name, - unsigned Mod, - raw_ostream &O) { - unsigned Opc = MI->getOpcode(); - int NumOps = 0; - int Ops[3]; - - for (int OpName : { AMDGPU::OpName::src0_modifiers, - AMDGPU::OpName::src1_modifiers, - AMDGPU::OpName::src2_modifiers }) { - int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); - if (Idx == -1) - break; - - Ops[NumOps++] = MI->getOperand(Idx).getImm(); - } - - const bool HasDstSel = - NumOps > 0 && - Mod == SISrcMods::OP_SEL_0 && - MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL; - - const bool IsPacked = - MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked; - - if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel)) - return; - - O << Name; - for (int I = 0; I < NumOps; ++I) { - if (I != 0) - O << ','; - - O << !!(Ops[I] & Mod); - } - - if (HasDstSel) { - O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL); - } - - O << ']'; -} - -void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O); -} - -void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O); -} - -void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O); -} - -void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O); -} - -void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - switch (Imm) { - case 0: - O << "p10"; - break; - case 1: - O << "p20"; - break; - case 2: - O << "p0"; - break; - default: - O << "invalid_param_" << Imm; - } -} - -void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Attr = MI->getOperand(OpNum).getImm(); - O << "attr" << Attr; -} - -void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Chan = MI->getOperand(OpNum).getImm(); - O << '.' << "xyzw"[Chan & 0x3]; -} - -void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - using namespace llvm::AMDGPU::VGPRIndexMode; - unsigned Val = MI->getOperand(OpNo).getImm(); - - if ((Val & ~ENABLE_MASK) != 0) { - O << " " << formatHex(static_cast(Val)); - } else { - O << " gpr_idx("; - bool NeedComma = false; - for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) { - if (Val & (1 << ModeId)) { - if (NeedComma) - O << ','; - O << IdSymbolic[ModeId]; - NeedComma = true; - } - } - O << ')'; - } -} - -void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printOperand(MI, OpNo, STI, O); - O << ", "; - printOperand(MI, OpNo + 1, STI, O); -} - -void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, - raw_ostream &O, StringRef Asm, - StringRef Default) { - const MCOperand &Op = MI->getOperand(OpNo); - assert(Op.isImm()); - if (Op.getImm() == 1) { - O << Asm; - } else { - O << Default; - } -} - -void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, - raw_ostream &O, char Asm) { - const MCOperand &Op = MI->getOperand(OpNo); - assert(Op.isImm()); - if (Op.getImm() == 1) - O << Asm; -} - -void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) - O << " high"; -} - -void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) - O << " clamp"; -} - -void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int Imm = MI->getOperand(OpNo).getImm(); - if (Imm == SIOutMods::MUL2) - O << " mul:2"; - else if (Imm == SIOutMods::MUL4) - O << " mul:4"; - else if (Imm == SIOutMods::DIV2) - O << " div:2"; -} - -void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - using namespace llvm::AMDGPU::SendMsg; - - const unsigned SImm16 = MI->getOperand(OpNo).getImm(); - const unsigned Id = SImm16 & ID_MASK_; - do { - if (Id == ID_INTERRUPT) { - if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0. - break; - O << "sendmsg(" << IdSymbolic[Id] << ')'; - return; - } - if (Id == ID_GS || Id == ID_GS_DONE) { - if ((SImm16 & ~(ID_MASK_|OP_GS_MASK_|STREAM_ID_MASK_)) != 0) // Unused/unknown bits must be 0. - break; - const unsigned OpGs = (SImm16 & OP_GS_MASK_) >> OP_SHIFT_; - const unsigned StreamId = (SImm16 & STREAM_ID_MASK_) >> STREAM_ID_SHIFT_; - if (OpGs == OP_GS_NOP && Id != ID_GS_DONE) // NOP to be used for GS_DONE only. - break; - if (OpGs == OP_GS_NOP && StreamId != 0) // NOP does not use/define stream id bits. - break; - O << "sendmsg(" << IdSymbolic[Id] << ", " << OpGsSymbolic[OpGs]; - if (OpGs != OP_GS_NOP) { O << ", " << StreamId; } - O << ')'; - return; - } - if (Id == ID_SYSMSG) { - if ((SImm16 & ~(ID_MASK_|OP_SYS_MASK_)) != 0) // Unused/unknown bits must be 0. - break; - const unsigned OpSys = (SImm16 & OP_SYS_MASK_) >> OP_SHIFT_; - if (! (OP_SYS_FIRST_ <= OpSys && OpSys < OP_SYS_LAST_)) // Unused/unknown. - break; - O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')'; - return; - } - } while (false); - O << SImm16; // Unknown simm16 code. -} - -static void printSwizzleBitmask(const uint16_t AndMask, - const uint16_t OrMask, - const uint16_t XorMask, - raw_ostream &O) { - using namespace llvm::AMDGPU::Swizzle; - - uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; - uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; - - O << "\""; - - for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) { - uint16_t p0 = Probe0 & Mask; - uint16_t p1 = Probe1 & Mask; - - if (p0 == p1) { - if (p0 == 0) { - O << "0"; - } else { - O << "1"; - } - } else { - if (p0 == 0) { - O << "p"; - } else { - O << "i"; - } - } - } - - O << "\""; -} - -void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - using namespace llvm::AMDGPU::Swizzle; - - uint16_t Imm = MI->getOperand(OpNo).getImm(); - if (Imm == 0) { - return; - } - - O << " offset:"; - - if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) { - - O << "swizzle(" << IdSymbolic[ID_QUAD_PERM]; - for (unsigned I = 0; I < LANE_NUM; ++I) { - O << ","; - O << formatDec(Imm & LANE_MASK); - Imm >>= LANE_SHIFT; - } - O << ")"; - - } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) { - - uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; - uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK; - uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK; - - if (AndMask == BITMASK_MAX && - OrMask == 0 && - countPopulation(XorMask) == 1) { - - O << "swizzle(" << IdSymbolic[ID_SWAP]; - O << ","; - O << formatDec(XorMask); - O << ")"; - - } else if (AndMask == BITMASK_MAX && - OrMask == 0 && XorMask > 0 && - isPowerOf2_64(XorMask + 1)) { - - O << "swizzle(" << IdSymbolic[ID_REVERSE]; - O << ","; - O << formatDec(XorMask + 1); - O << ")"; - - } else { - - uint16_t GroupSize = BITMASK_MAX - AndMask + 1; - if (GroupSize > 1 && - isPowerOf2_64(GroupSize) && - OrMask < GroupSize && - XorMask == 0) { - - O << "swizzle(" << IdSymbolic[ID_BROADCAST]; - O << ","; - O << formatDec(GroupSize); - O << ","; - O << formatDec(OrMask); - O << ")"; - - } else { - O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM]; - O << ","; - printSwizzleBitmask(AndMask, OrMask, XorMask, O); - O << ")"; - } - } - } else { - printU16ImmDecOperand(MI, OpNo, O); - } -} - -void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); - - unsigned SImm16 = MI->getOperand(OpNo).getImm(); - unsigned Vmcnt, Expcnt, Lgkmcnt; - decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt); - - bool NeedSpace = false; - - if (Vmcnt != getVmcntBitMask(ISA)) { - O << "vmcnt(" << Vmcnt << ')'; - NeedSpace = true; - } - - if (Expcnt != getExpcntBitMask(ISA)) { - if (NeedSpace) - O << ' '; - O << "expcnt(" << Expcnt << ')'; - NeedSpace = true; - } - - if (Lgkmcnt != getLgkmcntBitMask(ISA)) { - if (NeedSpace) - O << ' '; - O << "lgkmcnt(" << Lgkmcnt << ')'; - } -} - -void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - using namespace llvm::AMDGPU::Hwreg; - - unsigned SImm16 = MI->getOperand(OpNo).getImm(); - const unsigned Id = (SImm16 & ID_MASK_) >> ID_SHIFT_; - const unsigned Offset = (SImm16 & OFFSET_MASK_) >> OFFSET_SHIFT_; - const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1; - - O << "hwreg("; - unsigned Last = ID_SYMBOLIC_LAST_; - if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI) || AMDGPU::isVI(STI)) - Last = ID_SYMBOLIC_FIRST_GFX9_; - if (ID_SYMBOLIC_FIRST_ <= Id && Id < Last && IdSymbolic[Id]) { - O << IdSymbolic[Id]; - } else { - O << Id; - } - if (Width != WIDTH_M1_DEFAULT_ + 1 || Offset != OFFSET_DEFAULT_) { - O << ", " << Offset << ", " << Width; - } - O << ')'; -} - -void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint16_t Imm = MI->getOperand(OpNo).getImm(); - if (Imm == 0) { - return; - } - - O << formatDec(Imm); -} - -#include "AMDGPUGenAsmWriter.inc" - -void R600InstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - O.flush(); - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|'); -} - -void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - int BankSwizzle = MI->getOperand(OpNo).getImm(); - switch (BankSwizzle) { - case 1: - O << "BS:VEC_021/SCL_122"; - break; - case 2: - O << "BS:VEC_120/SCL_212"; - break; - case 3: - O << "BS:VEC_102/SCL_221"; - break; - case 4: - O << "BS:VEC_201"; - break; - case 5: - O << "BS:VEC_210"; - break; - default: - break; - } -} - -void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT"); -} - -void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned CT = MI->getOperand(OpNo).getImm(); - switch (CT) { - case 0: - O << 'U'; - break; - case 1: - O << 'N'; - break; - default: - break; - } -} - -void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - int KCacheMode = MI->getOperand(OpNo).getImm(); - if (KCacheMode > 0) { - int KCacheBank = MI->getOperand(OpNo - 2).getImm(); - O << "CB" << KCacheBank << ':'; - int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); - int LineSize = (KCacheMode == 1) ? 16 : 32; - O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize; - } -} - -void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " "); -} - -void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - assert(Op.isImm() || Op.isExpr()); - if (Op.isImm()) { - int64_t Imm = Op.getImm(); - O << Imm << '(' << BitsToFloat(Imm) << ')'; - } - if (Op.isExpr()) { - Op.getExpr()->print(O << '@', &MAI); - } -} - -void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-'); -} - -void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - switch (MI->getOperand(OpNo).getImm()) { - default: break; - case 1: - O << " * 2.0"; - break; - case 2: - O << " * 4.0"; - break; - case 3: - O << " / 2.0"; - break; - } -} - -void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printOperand(MI, OpNo, O); - O << ", "; - printOperand(MI, OpNo + 1, O); -} - -void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (OpNo >= MI->getNumOperands()) { - O << "/*Missing OP" << OpNo << "*/"; - return; - } - - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - switch (Op.getReg()) { - // This is the default predicate state, so we don't need to print it. - case R600::PRED_SEL_OFF: - break; - - default: - O << getRegisterName(Op.getReg()); - break; - } - } else if (Op.isImm()) { - O << Op.getImm(); - } else if (Op.isFPImm()) { - // We special case 0.0 because otherwise it will be printed as an integer. - if (Op.getFPImm() == 0.0) - O << "0.0"; - else { - O << Op.getFPImm(); - } - } else if (Op.isExpr()) { - const MCExpr *Exp = Op.getExpr(); - Exp->print(O, &MAI); - } else { - O << "/*INV_OP*/"; - } -} - -void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+'); -} - -void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned Sel = MI->getOperand(OpNo).getImm(); - switch (Sel) { - case 0: - O << 'X'; - break; - case 1: - O << 'Y'; - break; - case 2: - O << 'Z'; - break; - case 3: - O << 'W'; - break; - case 4: - O << '0'; - break; - case 5: - O << '1'; - break; - case 7: - O << '_'; - break; - default: - break; - } -} - -void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,"); -} - -void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,"); -} - -void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.getImm() == 0) { - O << " (MASKED)"; - } -} - -#include "R600GenAsmWriter.inc" Index: lib/Target/AMDGPU/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/AMDGPU/InstPrinter/CMakeLists.txt +++ lib/Target/AMDGPU/InstPrinter/CMakeLists.txt @@ -1,5 +0,0 @@ -add_llvm_library(LLVMAMDGPUAsmPrinter - AMDGPUInstPrinter.cpp - ) - -add_dependencies(LLVMAMDGPUAsmPrinter LLVMAMDGPUUtils) Index: lib/Target/AMDGPU/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/AMDGPU/InstPrinter/LLVMBuild.txt +++ lib/Target/AMDGPU/InstPrinter/LLVMBuild.txt @@ -1,23 +0,0 @@ -;===- ./lib/Target/AMDGPU/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = AMDGPUAsmPrinter -parent = AMDGPU -required_libraries = MC Support AMDGPUUtils -add_to_library_groups = AMDGPU - Index: lib/Target/AMDGPU/LLVMBuild.txt =================================================================== --- lib/Target/AMDGPU/LLVMBuild.txt +++ lib/Target/AMDGPU/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo Utils [component_0] type = TargetGroup @@ -29,5 +29,5 @@ type = Library name = AMDGPUCodeGen parent = AMDGPU -required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat MIRParser +required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils Vectorize GlobalISel BinaryFormat MIRParser add_to_library_groups = AMDGPU Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -13,9 +13,9 @@ #include "AMDGPUMCTargetDesc.h" #include "AMDGPUELFStreamer.h" +#include "AMDGPUInstPrinter.h" #include "AMDGPUMCAsmInfo.h" #include "AMDGPUTargetStreamer.h" -#include "InstPrinter/AMDGPUInstPrinter.h" #include "SIDefines.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCCodeEmitter.h" Index: lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt +++ lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ AMDGPUAsmBackend.cpp AMDGPUELFObjectWriter.cpp AMDGPUELFStreamer.cpp + AMDGPUInstPrinter.cpp AMDGPUMCAsmInfo.cpp AMDGPUMCCodeEmitter.cpp AMDGPUMCTargetDesc.cpp Index: lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt +++ lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = AMDGPUDesc parent = AMDGPU -required_libraries = Core MC AMDGPUAsmPrinter AMDGPUInfo AMDGPUUtils Support BinaryFormat +required_libraries = Core MC AMDGPUInfo AMDGPUUtils Support BinaryFormat add_to_library_groups = AMDGPU Index: lib/Target/ARC/ARCAsmPrinter.cpp =================================================================== --- lib/Target/ARC/ARCAsmPrinter.cpp +++ lib/Target/ARC/ARCAsmPrinter.cpp @@ -17,7 +17,7 @@ #include "ARCSubtarget.h" #include "ARCTargetMachine.h" #include "ARCTargetStreamer.h" -#include "InstPrinter/ARCInstPrinter.h" +#include "MCTargetDesc/ARCInstPrinter.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/AsmPrinter.h" Index: lib/Target/ARC/CMakeLists.txt =================================================================== --- lib/Target/ARC/CMakeLists.txt +++ lib/Target/ARC/CMakeLists.txt @@ -27,6 +27,5 @@ ) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/ARC/InstPrinter/ARCInstPrinter.h =================================================================== --- lib/Target/ARC/InstPrinter/ARCInstPrinter.h +++ lib/Target/ARC/InstPrinter/ARCInstPrinter.h @@ -1,45 +0,0 @@ -//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This file contains the declaration of the ARCInstPrinter class, -/// which is used to print ARC MCInst to a .s file. -/// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H -#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class ARCInstPrinter : public MCInstPrinter { -public: - ARCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - -private: - void printMemOperandRI(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O); -}; -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H Index: lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp =================================================================== --- lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp +++ lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp @@ -1,179 +0,0 @@ -//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an ARC MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "ARCInstPrinter.h" -#include "MCTargetDesc/ARCInfo.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#include "ARCGenAsmWriter.inc" - -template -static const char *BadConditionCode(T cc) { - LLVM_DEBUG(dbgs() << "Unknown condition code passed: " << cc << "\n"); - return "{unknown-cc}"; -} - -static const char *ARCBRCondCodeToString(ARCCC::BRCondCode BRCC) { - switch (BRCC) { - case ARCCC::BREQ: - return "eq"; - case ARCCC::BRNE: - return "ne"; - case ARCCC::BRLT: - return "lt"; - case ARCCC::BRGE: - return "ge"; - case ARCCC::BRLO: - return "lo"; - case ARCCC::BRHS: - return "hs"; - } - return BadConditionCode(BRCC); -} - -static const char *ARCCondCodeToString(ARCCC::CondCode CC) { - switch (CC) { - case ARCCC::EQ: - return "eq"; - case ARCCC::NE: - return "ne"; - case ARCCC::P: - return "p"; - case ARCCC::N: - return "n"; - case ARCCC::HS: - return "hs"; - case ARCCC::LO: - return "lo"; - case ARCCC::GT: - return "gt"; - case ARCCC::GE: - return "ge"; - case ARCCC::VS: - return "vs"; - case ARCCC::VC: - return "vc"; - case ARCCC::LT: - return "lt"; - case ARCCC::LE: - return "le"; - case ARCCC::HI: - return "hi"; - case ARCCC::LS: - return "ls"; - case ARCCC::PNZ: - return "pnz"; - case ARCCC::AL: - return "al"; - case ARCCC::NZ: - return "nz"; - case ARCCC::Z: - return "z"; - } - return BadConditionCode(CC); -} - -void ARCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << StringRef(getRegisterName(RegNo)).lower(); -} - -void ARCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI, - raw_ostream &OS) { - int Offset = 0; - const MCSymbolRefExpr *SRE; - - if (const auto *CE = dyn_cast(Expr)) { - OS << "0x"; - OS.write_hex(CE->getValue()); - return; - } - - if (const auto *BE = dyn_cast(Expr)) { - SRE = dyn_cast(BE->getLHS()); - const auto *CE = dyn_cast(BE->getRHS()); - assert(SRE && CE && "Binary expression must be sym+const."); - Offset = CE->getValue(); - } else { - SRE = dyn_cast(Expr); - assert(SRE && "Unexpected MCExpr type."); - } - assert(SRE->getKind() == MCSymbolRefExpr::VK_None); - - // Symbols are prefixed with '@' - OS << '@'; - SRE->getSymbol().print(OS, MAI); - - if (Offset) { - if (Offset > 0) - OS << '+'; - OS << Offset; - } -} - -void ARCInstPrinter::printOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - if (Op.isReg()) { - printRegName(O, Op.getReg()); - return; - } - - if (Op.isImm()) { - O << Op.getImm(); - return; - } - - assert(Op.isExpr() && "unknown operand kind in printOperand"); - printExpr(Op.getExpr(), &MAI, O); -} - -void ARCInstPrinter::printMemOperandRI(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - const MCOperand &base = MI->getOperand(OpNum); - const MCOperand &offset = MI->getOperand(OpNum + 1); - assert(base.isReg() && "Base should be register."); - assert(offset.isImm() && "Offset should be immediate."); - printRegName(O, base.getReg()); - O << "," << offset.getImm(); -} - -void ARCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - - const MCOperand &Op = MI->getOperand(OpNum); - assert(Op.isImm() && "Predicate operand is immediate."); - O << ARCCondCodeToString((ARCCC::CondCode)Op.getImm()); -} - -void ARCInstPrinter::printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - assert(Op.isImm() && "Predicate operand is immediate."); - O << ARCBRCondCodeToString((ARCCC::BRCondCode)Op.getImm()); -} Index: lib/Target/ARC/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/ARC/InstPrinter/CMakeLists.txt +++ lib/Target/ARC/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMARCAsmPrinter - ARCInstPrinter.cpp - ) Index: lib/Target/ARC/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/ARC/InstPrinter/LLVMBuild.txt +++ lib/Target/ARC/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/ARC/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = ARCAsmPrinter -parent = ARC -required_libraries = MC Support -add_to_library_groups = ARC Index: lib/Target/ARC/LLVMBuild.txt =================================================================== --- lib/Target/ARC/LLVMBuild.txt +++ lib/Target/ARC/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -38,7 +38,6 @@ Support Target TransformUtils - ARCAsmPrinter ARCDesc ARCInfo add_to_library_groups = ARC Index: lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp =================================================================== --- lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp +++ lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp @@ -13,7 +13,7 @@ #include "ARCMCTargetDesc.h" #include "ARCMCAsmInfo.h" #include "ARCTargetStreamer.h" -#include "InstPrinter/ARCInstPrinter.h" +#include "MCTargetDesc/ARCInstPrinter.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" Index: lib/Target/ARC/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/ARC/MCTargetDesc/CMakeLists.txt +++ lib/Target/ARC/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMARCDesc + ARCInstPrinter.cpp ARCMCTargetDesc.cpp ARCMCAsmInfo.cpp ) Index: lib/Target/ARC/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/ARC/MCTargetDesc/LLVMBuild.txt +++ lib/Target/ARC/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = ARCDesc parent = ARC -required_libraries = MC Support ARCAsmPrinter ARCInfo +required_libraries = MC Support ARCInfo add_to_library_groups = ARC Index: lib/Target/ARM/ARMAsmPrinter.cpp =================================================================== --- lib/Target/ARM/ARMAsmPrinter.cpp +++ lib/Target/ARM/ARMAsmPrinter.cpp @@ -17,8 +17,8 @@ #include "ARMMachineFunctionInfo.h" #include "ARMTargetMachine.h" #include "ARMTargetObjectFile.h" -#include "InstPrinter/ARMInstPrinter.h" #include "MCTargetDesc/ARMAddressingModes.h" +#include "MCTargetDesc/ARMInstPrinter.h" #include "MCTargetDesc/ARMMCExpr.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallString.h" Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7,10 +7,10 @@ //===----------------------------------------------------------------------===// #include "ARMFeatures.h" -#include "InstPrinter/ARMInstPrinter.h" #include "Utils/ARMBaseInfo.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" +#include "MCTargetDesc/ARMInstPrinter.h" #include "MCTargetDesc/ARMMCExpr.h" #include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/ADT/APFloat.h" Index: lib/Target/ARM/AsmParser/LLVMBuild.txt =================================================================== --- lib/Target/ARM/AsmParser/LLVMBuild.txt +++ lib/Target/ARM/AsmParser/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = ARMAsmParser parent = ARM -required_libraries = ARMDesc ARMInfo ARMAsmPrinter MC MCParser Support ARMUtils +required_libraries = ARMDesc ARMInfo MC MCParser Support ARMUtils add_to_library_groups = ARM Index: lib/Target/ARM/CMakeLists.txt =================================================================== --- lib/Target/ARM/CMakeLists.txt +++ lib/Target/ARM/CMakeLists.txt @@ -61,7 +61,6 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(Utils) Index: lib/Target/ARM/InstPrinter/ARMInstPrinter.h =================================================================== --- lib/Target/ARM/InstPrinter/ARMInstPrinter.h +++ lib/Target/ARM/InstPrinter/ARMInstPrinter.h @@ -1,249 +0,0 @@ -//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an ARM MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H -#define LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H - -#include "MCTargetDesc/ARMMCTargetDesc.h" -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class ARMInstPrinter : public MCInstPrinter { -public: - ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); - - bool applyTargetSpecificCLOption(StringRef Opt) override; - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - const MCSubtargetInfo &STI, - raw_ostream &O); - static const char *getRegisterName(unsigned RegNo, - unsigned AltIdx = ARM::NoRegAltName); - - void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - - void printSORegRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printSORegImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printAddrModeTBB(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrModeTBH(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, - bool AlwaysPrintImm0); - void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printMemBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printInstSyncBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printShiftImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - template - void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbSRImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbITMask(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O, unsigned Scale); - void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printT2SOOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printSetendOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printCPSIMod(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printCPSIFlag(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printBankedRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPredicateOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printRegisterList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printNoHashImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printPImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printCImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFPImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printRotImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printModImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printGPRPairOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - - void printPCLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFBits16(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFBits32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListOne(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListTwo(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListThree(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListFour(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O); - void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - template - void printComplexRotationOp(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); - -private: - unsigned DefaultAltIdx = ARM::NoRegAltName; -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H Index: lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp =================================================================== --- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -1,1582 +0,0 @@ -//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an ARM MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "ARMInstPrinter.h" -#include "Utils/ARMBaseInfo.h" -#include "MCTargetDesc/ARMAddressingModes.h" -#include "MCTargetDesc/ARMBaseInfo.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/SubtargetFeature.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/raw_ostream.h" -#include -#include -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#define PRINT_ALIAS_INSTR -#include "ARMGenAsmWriter.inc" - -/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. -/// -/// getSORegOffset returns an integer from 0-31, representing '32' as 0. -static unsigned translateShiftImm(unsigned imm) { - // lsr #32 and asr #32 exist, but should be encoded as a 0. - assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); - - if (imm == 0) - return 32; - return imm; -} - -/// Prints the shift value with an immediate value. -static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, - unsigned ShImm, bool UseMarkup) { - if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) - return; - O << ", "; - - assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); - O << getShiftOpcStr(ShOpc); - - if (ShOpc != ARM_AM::rrx) { - O << " "; - if (UseMarkup) - O << ""; - } -} - -ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - -bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { - if (Opt == "reg-names-std") { - DefaultAltIdx = ARM::NoRegAltName; - return true; - } - if (Opt == "reg-names-raw") { - DefaultAltIdx = ARM::RegNamesRaw; - return true; - } - return false; -} - -void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << markup(""); -} - -void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - unsigned Opcode = MI->getOpcode(); - - switch (Opcode) { - // Check for MOVs and print canonical forms, instead. - case ARM::MOVsr: { - // FIXME: Thumb variants? - const MCOperand &Dst = MI->getOperand(0); - const MCOperand &MO1 = MI->getOperand(1); - const MCOperand &MO2 = MI->getOperand(2); - const MCOperand &MO3 = MI->getOperand(3); - - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); - printSBitModifierOperand(MI, 6, STI, O); - printPredicateOperand(MI, 4, STI, O); - - O << '\t'; - printRegName(O, Dst.getReg()); - O << ", "; - printRegName(O, MO1.getReg()); - - O << ", "; - printRegName(O, MO2.getReg()); - assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); - printAnnotation(O, Annot); - return; - } - - case ARM::MOVsi: { - // FIXME: Thumb variants? - const MCOperand &Dst = MI->getOperand(0); - const MCOperand &MO1 = MI->getOperand(1); - const MCOperand &MO2 = MI->getOperand(2); - - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); - printSBitModifierOperand(MI, 5, STI, O); - printPredicateOperand(MI, 3, STI, O); - - O << '\t'; - printRegName(O, Dst.getReg()); - O << ", "; - printRegName(O, MO1.getReg()); - - if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { - printAnnotation(O, Annot); - return; - } - - O << ", " << markup(""); - printAnnotation(O, Annot); - return; - } - - // A8.6.123 PUSH - case ARM::STMDB_UPD: - case ARM::t2STMDB_UPD: - if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { - // Should only print PUSH if there are at least two registers in the list. - O << '\t' << "push"; - printPredicateOperand(MI, 2, STI, O); - if (Opcode == ARM::t2STMDB_UPD) - O << ".w"; - O << '\t'; - printRegisterList(MI, 4, STI, O); - printAnnotation(O, Annot); - return; - } else - break; - - case ARM::STR_PRE_IMM: - if (MI->getOperand(2).getReg() == ARM::SP && - MI->getOperand(3).getImm() == -4) { - O << '\t' << "push"; - printPredicateOperand(MI, 4, STI, O); - O << "\t{"; - printRegName(O, MI->getOperand(1).getReg()); - O << "}"; - printAnnotation(O, Annot); - return; - } else - break; - - // A8.6.122 POP - case ARM::LDMIA_UPD: - case ARM::t2LDMIA_UPD: - if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { - // Should only print POP if there are at least two registers in the list. - O << '\t' << "pop"; - printPredicateOperand(MI, 2, STI, O); - if (Opcode == ARM::t2LDMIA_UPD) - O << ".w"; - O << '\t'; - printRegisterList(MI, 4, STI, O); - printAnnotation(O, Annot); - return; - } else - break; - - case ARM::LDR_POST_IMM: - if (MI->getOperand(2).getReg() == ARM::SP && - MI->getOperand(4).getImm() == 4) { - O << '\t' << "pop"; - printPredicateOperand(MI, 5, STI, O); - O << "\t{"; - printRegName(O, MI->getOperand(0).getReg()); - O << "}"; - printAnnotation(O, Annot); - return; - } else - break; - - // A8.6.355 VPUSH - case ARM::VSTMSDB_UPD: - case ARM::VSTMDDB_UPD: - if (MI->getOperand(0).getReg() == ARM::SP) { - O << '\t' << "vpush"; - printPredicateOperand(MI, 2, STI, O); - O << '\t'; - printRegisterList(MI, 4, STI, O); - printAnnotation(O, Annot); - return; - } else - break; - - // A8.6.354 VPOP - case ARM::VLDMSIA_UPD: - case ARM::VLDMDIA_UPD: - if (MI->getOperand(0).getReg() == ARM::SP) { - O << '\t' << "vpop"; - printPredicateOperand(MI, 2, STI, O); - O << '\t'; - printRegisterList(MI, 4, STI, O); - printAnnotation(O, Annot); - return; - } else - break; - - case ARM::tLDMIA: { - bool Writeback = true; - unsigned BaseReg = MI->getOperand(0).getReg(); - for (unsigned i = 3; i < MI->getNumOperands(); ++i) { - if (MI->getOperand(i).getReg() == BaseReg) - Writeback = false; - } - - O << "\tldm"; - - printPredicateOperand(MI, 1, STI, O); - O << '\t'; - printRegName(O, BaseReg); - if (Writeback) - O << "!"; - O << ", "; - printRegisterList(MI, 3, STI, O); - printAnnotation(O, Annot); - return; - } - - // Combine 2 GPRs from disassember into a GPRPair to match with instr def. - // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, - // a single GPRPair reg operand is used in the .td file to replace the two - // GPRs. However, when decoding them, the two GRPs cannot be automatically - // expressed as a GPRPair, so we have to manually merge them. - // FIXME: We would really like to be able to tablegen'erate this. - case ARM::LDREXD: - case ARM::STREXD: - case ARM::LDAEXD: - case ARM::STLEXD: { - const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); - bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; - unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); - if (MRC.contains(Reg)) { - MCInst NewMI; - MCOperand NewReg; - NewMI.setOpcode(Opcode); - - if (isStore) - NewMI.addOperand(MI->getOperand(0)); - NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( - Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID))); - NewMI.addOperand(NewReg); - - // Copy the rest operands into NewMI. - for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i) - NewMI.addOperand(MI->getOperand(i)); - printInstruction(&NewMI, STI, O); - return; - } - break; - } - case ARM::TSB: - case ARM::t2TSB: - O << "\ttsb\tcsync"; - return; - case ARM::t2DSB: - switch (MI->getOperand(0).getImm()) { - default: - if (!printAliasInstr(MI, STI, O)) - printInstruction(MI, STI, O); - break; - case 0: - O << "\tssbb"; - break; - case 4: - O << "\tpssbb"; - break; - } - printAnnotation(O, Annot); - return; - } - - if (!printAliasInstr(MI, STI, O)) - printInstruction(MI, STI, O); - - printAnnotation(O, Annot); -} - -void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned Reg = Op.getReg(); - printRegName(O, Reg); - } else if (Op.isImm()) { - O << markup(""); - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - const MCExpr *Expr = Op.getExpr(); - switch (Expr->getKind()) { - case MCExpr::Binary: - O << '#'; - Expr->print(O, &MAI); - break; - case MCExpr::Constant: { - // If a symbolic branch target was added as a constant expression then - // print that address in hex. And only print 32 unsigned bits for the - // address. - const MCConstantExpr *Constant = cast(Expr); - int64_t TargetAddress; - if (!Constant->evaluateAsAbsolute(TargetAddress)) { - O << '#'; - Expr->print(O, &MAI); - } else { - O << "0x"; - O.write_hex(static_cast(TargetAddress)); - } - break; - } - default: - // FIXME: Should we always treat this as if it is a constant literal and - // prefix it with '#'? - Expr->print(O, &MAI); - break; - } - } -} - -void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - if (MO1.isExpr()) { - MO1.getExpr()->print(O, &MAI); - return; - } - - O << markup(""); - } else { - O << markup(""); - } - O << "]" << markup(">"); -} - -// so_reg is a 4-operand unit corresponding to register forms of the A5.1 -// "Addressing Mode 1 - Data-processing operands" forms. This includes: -// REG 0 0 - e.g. R5 -// REG REG 0,SH_OPC - e.g. R5, ROR R3 -// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - const MCOperand &MO3 = MI->getOperand(OpNum + 2); - - printRegName(O, MO1.getReg()); - - // Print the shift opc. - ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); - O << ", " << ARM_AM::getShiftOpcStr(ShOpc); - if (ShOpc == ARM_AM::rrx) - return; - - O << ' '; - printRegName(O, MO2.getReg()); - assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); -} - -void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - printRegName(O, MO1.getReg()); - - // Print the shift opc. - printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), - ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); -} - -//===--------------------------------------------------------------------===// -// Addressing Mode #2 -//===--------------------------------------------------------------------===// - -void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - const MCOperand &MO3 = MI->getOperand(Op + 2); - - O << markup(""); - } - O << "]" << markup(">"); - return; - } - - O << ", "; - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())); - printRegName(O, MO2.getReg()); - - printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()), - ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup); - O << "]" << markup(">"); -} - -void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - O << markup(""); -} - -void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - O << markup("") << "]" << markup(">"); -} - -void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, STI, O); - return; - } - -#ifndef NDEBUG - const MCOperand &MO3 = MI->getOperand(Op + 2); - unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); - assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); -#endif - - printAM2PreOrOffsetIndexOp(MI, Op, STI, O); -} - -void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - if (!MO1.getReg()) { - unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); - O << markup(""); - return; - } - - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())); - printRegName(O, MO1.getReg()); - - printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()), - ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup); -} - -//===--------------------------------------------------------------------===// -// Addressing Mode #3 -//===--------------------------------------------------------------------===// - -void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, - raw_ostream &O, - bool AlwaysPrintImm0) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - const MCOperand &MO3 = MI->getOperand(Op + 2); - - O << markup(""); - return; - } - - // If the op is sub we have to print the immediate even if it is 0 - unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); - ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); - - if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) { - O << ", " << markup(""); - } - O << ']' << markup(">"); -} - -template -void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - if (!MO1.isReg()) { // For label symbolic references. - printOperand(MI, Op, STI, O); - return; - } - - assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) != - ARMII::IndexModePost && - "unexpected idxmode"); - printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); -} - -void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - if (MO1.getReg()) { - O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())); - printRegName(O, MO1.getReg()); - return; - } - - unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); - O << markup(""); -} - -void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - unsigned Imm = MO.getImm(); - O << markup(""); -} - -void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - O << (MO2.getImm() ? "" : "-"); - printRegName(O, MO1.getReg()); -} - -void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - unsigned Imm = MO.getImm(); - O << markup(""); -} - -void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - ARM_AM::AMSubMode Mode = - ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm()); - O << ARM_AM::getAMSubModeStr(Mode); -} - -template -void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, STI, O); - return; - } - - O << markup(""); - } - O << "]" << markup(">"); -} - -template -void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum+1); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, STI, O); - return; - } - - O << markup(""); - } - O << "]" << markup(">"); -} - -void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - O << markup(""); -} - -void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - O << markup(""); -} - -void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - if (MO.getReg() == 0) - O << "!"; - else { - O << ", "; - printRegName(O, MO.getReg()); - } -} - -void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - uint32_t v = ~MO.getImm(); - int32_t lsb = countTrailingZeros(v); - int32_t width = (32 - countLeadingZeros(v)) - lsb; - assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); - O << markup("") << ", " << markup(""); -} - -void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]); -} - -void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_ISB::InstSyncBOptToString(val); -} - -void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_TSB::TraceSyncBOptToString(val); -} - -void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned ShiftOp = MI->getOperand(OpNum).getImm(); - bool isASR = (ShiftOp & (1 << 5)) != 0; - unsigned Amt = ShiftOp & 0x1f; - if (isASR) { - O << ", asr " << markup(""); - } else if (Amt) { - O << ", lsl " << markup(""); - } -} - -void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - if (Imm == 0) - return; - assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); - O << ", lsl " << markup(""); -} - -void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - // A shift amount of 32 is encoded as 0. - if (Imm == 0) - Imm = 32; - assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); - O << ", asr " << markup(""); -} - -void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - assert(std::is_sorted(MI->begin() + OpNum, MI->end(), - [&](const MCOperand &LHS, const MCOperand &RHS) { - return MRI.getEncodingValue(LHS.getReg()) < - MRI.getEncodingValue(RHS.getReg()); - })); - - O << "{"; - for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { - if (i != OpNum) - O << ", "; - printRegName(O, MI->getOperand(i).getReg()); - } - O << "}"; -} - -void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); - O << ", "; - printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); -} - -void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - if (Op.getImm()) - O << "be"; - else - O << "le"; -} - -void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - O << ARM_PROC::IModToString(Op.getImm()); -} - -void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - unsigned IFlags = Op.getImm(); - for (int i = 2; i >= 0; --i) - if (IFlags & (1 << i)) - O << ARM_PROC::IFlagsToString(1 << i); - - if (IFlags == 0) - O << "none"; -} - -void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNum); - const FeatureBitset &FeatureBits = STI.getFeatureBits(); - if (FeatureBits[ARM::FeatureMClass]) { - - unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm - unsigned Opcode = MI->getOpcode(); - - // For writes, handle extended mask bits if the DSP extension is present. - if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { - auto TheReg =ARMSysReg::lookupMClassSysRegBy12bitSYSmValue(SYSm); - if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) { - O << TheReg->Name; - return; - } - } - - // Handle the basic 8-bit mask. - SYSm &= 0xff; - if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { - // ARMv7-M deprecates using MSR APSR without a _ qualifier as an - // alias for MSR APSR_nzcvq. - auto TheReg = ARMSysReg::lookupMClassSysRegAPSRNonDeprecated(SYSm); - if (TheReg) { - O << TheReg->Name; - return; - } - } - - auto TheReg = ARMSysReg::lookupMClassSysRegBy8bitSYSmValue(SYSm); - if (TheReg) { - O << TheReg->Name; - return; - } - - O << SYSm; - - return; - } - - // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as - // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. - unsigned SpecRegRBit = Op.getImm() >> 4; - unsigned Mask = Op.getImm() & 0xf; - - if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { - O << "APSR_"; - switch (Mask) { - default: - llvm_unreachable("Unexpected mask value!"); - case 4: - O << "g"; - return; - case 8: - O << "nzcvq"; - return; - case 12: - O << "nzcvqg"; - return; - } - } - - if (SpecRegRBit) - O << "SPSR"; - else - O << "CPSR"; - - if (Mask) { - O << '_'; - if (Mask & 8) - O << 'f'; - if (Mask & 4) - O << 's'; - if (Mask & 2) - O << 'x'; - if (Mask & 1) - O << 'c'; - } -} - -void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint32_t Banked = MI->getOperand(OpNum).getImm(); - auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked); - assert(TheReg && "invalid banked register operand"); - std::string Name = TheReg->Name; - - uint32_t isSPSR = (Banked & 0x20) >> 5; - if (isSPSR) - Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_' - O << Name; -} - -void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); - // Handle the undefined 15 CC value here for printing so we don't abort(). - if ((unsigned)CC == 15) - O << ""; - else if (CC != ARMCC::AL) - O << ARMCondCodeToString(CC); -} - -void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); - O << ARMCondCodeToString(CC); -} - -void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (MI->getOperand(OpNum).getReg()) { - assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && - "Expect ARM CPSR register!"); - O << 's'; - } -} - -void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << MI->getOperand(OpNum).getImm(); -} - -void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "p" << MI->getOperand(OpNum).getImm(); -} - -void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "c" << MI->getOperand(OpNum).getImm(); -} - -void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "{" << MI->getOperand(OpNum).getImm() << "}"; -} - -void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); -} - -template -void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - - if (MO.isExpr()) { - MO.getExpr()->print(O, &MAI); - return; - } - - int32_t OffImm = (int32_t)MO.getImm() << scale; - - O << markup(""); -} - -void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << markup("getOperand(OpNum).getImm() * 4) - << markup(">"); -} - -void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - O << markup(""); -} - -void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // (3 - the number of trailing zeros) is the number of then / else. - unsigned Mask = MI->getOperand(OpNum).getImm(); - unsigned Firstcond = MI->getOperand(OpNum - 1).getImm(); - unsigned CondBit0 = Firstcond & 1; - unsigned NumTZ = countTrailingZeros(Mask); - assert(NumTZ <= 3 && "Invalid IT mask!"); - for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { - bool T = ((Mask >> Pos) & 1) == CondBit0; - if (T) - O << 't'; - else - O << 'e'; - } -} - -void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, STI, O); - return; - } - - O << markup(""); -} - -void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, - unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O, - unsigned Scale) { - const MCOperand &MO1 = MI->getOperand(Op); - const MCOperand &MO2 = MI->getOperand(Op + 1); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, STI, O); - return; - } - - O << markup(""); - } - O << "]" << markup(">"); -} - -void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, - unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1); -} - -void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, - unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2); -} - -void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, - unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4); -} - -void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, - const MCSubtargetInfo &STI, - raw_ostream &O) { - printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4); -} - -// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 -// register with shift forms. -// REG 0 0 - e.g. R5 -// REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - unsigned Reg = MO1.getReg(); - printRegName(O, Reg); - - // Print the shift opc. - assert(MO2.isImm() && "Not a valid t2_so_reg value!"); - printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), - ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); -} - -template -void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, STI, O); - return; - } - - O << markup(""); - } else if (AlwaysPrintImm0 || OffImm > 0) { - O << ", " << markup(""); - } - O << "]" << markup(">"); -} - -template -void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - O << markup(""); - } else if (AlwaysPrintImm0 || OffImm > 0) { - O << ", " << markup(""); - } - O << "]" << markup(">"); -} - -template -void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - if (!MO1.isReg()) { // For label symbolic references. - printOperand(MI, OpNum, STI, O); - return; - } - - O << markup(""); - } else if (AlwaysPrintImm0 || OffImm > 0) { - O << ", " << markup(""); - } - O << "]" << markup(">"); -} - -void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - - O << markup(""); - } - O << "]" << markup(">"); -} - -void ARMInstPrinter::printT2AddrModeImm8OffsetOperand( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - int32_t OffImm = (int32_t)MO1.getImm(); - O << ", " << markup(""); -} - -void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - int32_t OffImm = (int32_t)MO1.getImm(); - - assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); - - O << ", " << markup(""); -} - -void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO1 = MI->getOperand(OpNum); - const MCOperand &MO2 = MI->getOperand(OpNum + 1); - const MCOperand &MO3 = MI->getOperand(OpNum + 2); - - O << markup(""); - } - O << "]" << markup(">"); -} - -void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - O << markup(""); -} - -void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned EncodedImm = MI->getOperand(OpNum).getImm(); - unsigned EltBits; - uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); - O << markup(""); -} - -void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - O << markup(""); -} - -void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - if (Imm == 0) - return; - assert(Imm <= 3 && "illegal ror immediate!"); - O << ", ror " << markup(""); -} - -void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - MCOperand Op = MI->getOperand(OpNum); - - // Support for fixups (MCFixup) - if (Op.isExpr()) - return printOperand(MI, OpNum, STI, O); - - unsigned Bits = Op.getImm() & 0xFF; - unsigned Rot = (Op.getImm() & 0xF00) >> 7; - - bool PrintUnsigned = false; - switch (MI->getOpcode()) { - case ARM::MOVi: - // Movs to PC should be treated unsigned - PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC); - break; - case ARM::MSRi: - // Movs to special registers should be treated unsigned - PrintUnsigned = true; - break; - } - - int32_t Rotated = ARM_AM::rotr32(Bits, Rot); - if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) { - // #rot has the least possible value - O << "#" << markup("(Rotated); - else - O << Rotated; - O << markup(">"); - return; - } - - // Explicit #bits, #rot implied - O << "#" << markup("") << ", #" << markup(""); -} - -void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - O << markup("getOperand(OpNum).getImm() - << markup(">"); -} - -void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O) { - O << markup("getOperand(OpNum).getImm() - << markup(">"); -} - -void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "[" << MI->getOperand(OpNum).getImm() << "]"; -} - -void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "}"; -} - -void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); - O << "{"; - printRegName(O, Reg0); - O << ", "; - printRegName(O, Reg1); - O << "}"; -} - -void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); - O << "{"; - printRegName(O, Reg0); - O << ", "; - printRegName(O, Reg1); - O << "}"; -} - -void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 1); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << "}"; -} - -void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 1); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 3); - O << "}"; -} - -void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); - O << "{"; - printRegName(O, Reg0); - O << "[], "; - printRegName(O, Reg1); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 1); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 1); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 3); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListTwoSpacedAllLanes( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); - unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); - O << "{"; - printRegName(O, Reg0); - O << "[], "; - printRegName(O, Reg1); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListThreeSpacedAllLanes( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 4); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListFourSpacedAllLanes( - const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 4); - O << "[], "; - printRegName(O, MI->getOperand(OpNum).getReg() + 6); - O << "[]}"; -} - -void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI, - unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 4); - O << "}"; -} - -void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - O << "{"; - printRegName(O, MI->getOperand(OpNum).getReg()); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 2); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 4); - O << ", "; - printRegName(O, MI->getOperand(OpNum).getReg() + 6); - O << "}"; -} - -template -void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Val = MI->getOperand(OpNo).getImm(); - O << "#" << (Val * Angle) + Remainder; -} - Index: lib/Target/ARM/LLVMBuild.txt =================================================================== --- lib/Target/ARM/LLVMBuild.txt +++ lib/Target/ARM/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo Utils [component_0] type = TargetGroup @@ -30,5 +30,5 @@ type = Library name = ARMCodeGen parent = ARM -required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils TransformUtils +required_libraries = ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils TransformUtils add_to_library_groups = ARM Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -12,8 +12,8 @@ #include "ARMMCTargetDesc.h" #include "ARMBaseInfo.h" +#include "ARMInstPrinter.h" #include "ARMMCAsmInfo.h" -#include "InstPrinter/ARMInstPrinter.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCCodeEmitter.h" Index: lib/Target/ARM/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/ARM/MCTargetDesc/CMakeLists.txt +++ lib/Target/ARM/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ ARMAsmBackend.cpp ARMELFObjectWriter.cpp ARMELFStreamer.cpp + ARMInstPrinter.cpp ARMMachObjectWriter.cpp ARMMachORelocationInfo.cpp ARMMCAsmInfo.cpp Index: lib/Target/ARM/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/ARM/MCTargetDesc/LLVMBuild.txt +++ lib/Target/ARM/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = ARMDesc parent = ARM -required_libraries = ARMAsmPrinter ARMInfo MC MCDisassembler Support +required_libraries = ARMInfo ARMUtils MC MCDisassembler Support add_to_library_groups = ARM Index: lib/Target/AVR/AVRAsmPrinter.cpp =================================================================== --- lib/Target/AVR/AVRAsmPrinter.cpp +++ lib/Target/AVR/AVRAsmPrinter.cpp @@ -14,7 +14,7 @@ #include "AVR.h" #include "AVRMCInstLower.h" #include "AVRSubtarget.h" -#include "InstPrinter/AVRInstPrinter.h" +#include "MCTargetDesc/AVRInstPrinter.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunction.h" Index: lib/Target/AVR/CMakeLists.txt =================================================================== --- lib/Target/AVR/CMakeLists.txt +++ lib/Target/AVR/CMakeLists.txt @@ -32,6 +32,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/AVR/InstPrinter/AVRInstPrinter.h =================================================================== --- lib/Target/AVR/InstPrinter/AVRInstPrinter.h +++ lib/Target/AVR/InstPrinter/AVRInstPrinter.h @@ -1,53 +0,0 @@ -//===- AVRInstPrinter.h - Convert AVR MCInst to assembly syntax -*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an AVR MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_AVR_INST_PRINTER_H -#define LLVM_AVR_INST_PRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -#include "MCTargetDesc/AVRMCTargetDesc.h" - -namespace llvm { - -/// Prints AVR instructions to a textual stream. -class AVRInstPrinter : public MCInstPrinter { -public: - AVRInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - static const char *getPrettyRegisterName(unsigned RegNo, - MCRegisterInfo const &MRI); - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - -private: - static const char *getRegisterName(unsigned RegNo, - unsigned AltIdx = AVR::NoRegAltName); - - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMemri(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - // Autogenerated by TableGen. - void printInstruction(const MCInst *MI, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); -}; - -} // end namespace llvm - -#endif // LLVM_AVR_INST_PRINTER_H - Index: lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp =================================================================== --- lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp +++ lib/Target/AVR/InstPrinter/AVRInstPrinter.cpp @@ -1,170 +0,0 @@ -//===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an AVR MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "AVRInstPrinter.h" - -#include "MCTargetDesc/AVRMCTargetDesc.h" - -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" - -#include - -#define DEBUG_TYPE "asm-printer" - -namespace llvm { - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "AVRGenAsmWriter.inc" - -void AVRInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - unsigned Opcode = MI->getOpcode(); - - // First handle load and store instructions with postinc or predec - // of the form "ld reg, X+". - // TODO: We should be able to rewrite this using TableGen data. - switch (Opcode) { - case AVR::LDRdPtr: - case AVR::LDRdPtrPi: - case AVR::LDRdPtrPd: - O << "\tld\t"; - printOperand(MI, 0, O); - O << ", "; - - if (Opcode == AVR::LDRdPtrPd) - O << '-'; - - printOperand(MI, 1, O); - - if (Opcode == AVR::LDRdPtrPi) - O << '+'; - break; - case AVR::STPtrRr: - O << "\tst\t"; - printOperand(MI, 0, O); - O << ", "; - printOperand(MI, 1, O); - break; - case AVR::STPtrPiRr: - case AVR::STPtrPdRr: - O << "\tst\t"; - - if (Opcode == AVR::STPtrPdRr) - O << '-'; - - printOperand(MI, 1, O); - - if (Opcode == AVR::STPtrPiRr) - O << '+'; - - O << ", "; - printOperand(MI, 2, O); - break; - default: - if (!printAliasInstr(MI, O)) - printInstruction(MI, O); - - printAnnotation(O, Annot); - break; - } -} - -const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, - MCRegisterInfo const &MRI) { - // GCC prints register pairs by just printing the lower register - // If the register contains a subregister, print it instead - if (MRI.getNumSubRegIndices() > 0) { - unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); - RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; - } - - return getRegisterName(RegNum); -} - -void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo]; - - if (Op.isReg()) { - bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || - (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || - (MOI.RegClass == AVR::ZREGRegClassID); - - if (isPtrReg) { - O << getRegisterName(Op.getReg(), AVR::ptr); - } else { - O << getPrettyRegisterName(Op.getReg(), MRI); - } - } else if (Op.isImm()) { - O << Op.getImm(); - } else { - assert(Op.isExpr() && "Unknown operand kind in printOperand"); - O << *Op.getExpr(); - } -} - -/// This is used to print an immediate value that ends up -/// being encoded as a pc-relative value. -void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - - if (Op.isImm()) { - int64_t Imm = Op.getImm(); - O << '.'; - - // Print a position sign if needed. - // Negative values have their sign printed automatically. - if (Imm >= 0) - O << '+'; - - O << Imm; - } else { - assert(Op.isExpr() && "Unknown pcrel immediate operand"); - O << *Op.getExpr(); - } -} - -void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand"); - - const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); - - // Print the register. - printOperand(MI, OpNo, O); - - // Print the {+,-}offset. - if (OffsetOp.isImm()) { - int64_t Offset = OffsetOp.getImm(); - - if (Offset >= 0) - O << '+'; - - O << Offset; - } else if (OffsetOp.isExpr()) { - O << *OffsetOp.getExpr(); - } else { - llvm_unreachable("unknown type for offset"); - } -} - -} // end of namespace llvm - Index: lib/Target/AVR/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/AVR/InstPrinter/CMakeLists.txt +++ lib/Target/AVR/InstPrinter/CMakeLists.txt @@ -1,8 +0,0 @@ -include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. - ${CMAKE_CURRENT_SOURCE_DIR}/.. ) - -add_llvm_library(LLVMAVRAsmPrinter - AVRInstPrinter.cpp - ) - -add_dependencies(LLVMAVRAsmPrinter AVRCommonTableGen) \ No newline at end of file Index: lib/Target/AVR/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/AVR/InstPrinter/LLVMBuild.txt +++ lib/Target/AVR/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/AVR/InstPrinter/LLVMBuild.txt ----------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = AVRAsmPrinter -parent = AVR -required_libraries = MC Support -add_to_library_groups = AVR \ No newline at end of file Index: lib/Target/AVR/LLVMBuild.txt =================================================================== --- lib/Target/AVR/LLVMBuild.txt +++ lib/Target/AVR/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -29,6 +29,6 @@ type = Library name = AVRCodeGen parent = AVR -required_libraries = AsmPrinter CodeGen Core MC AVRAsmPrinter AVRDesc AVRInfo SelectionDAG Support Target +required_libraries = AsmPrinter CodeGen Core MC AVRDesc AVRInfo SelectionDAG Support Target add_to_library_groups = AVR Index: lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp =================================================================== --- lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp +++ lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp @@ -11,11 +11,11 @@ //===----------------------------------------------------------------------===// #include "AVRELFStreamer.h" +#include "AVRInstPrinter.h" #include "AVRMCAsmInfo.h" #include "AVRMCELFStreamer.h" #include "AVRMCTargetDesc.h" #include "AVRTargetStreamer.h" -#include "InstPrinter/AVRInstPrinter.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCELFStreamer.h" Index: lib/Target/AVR/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/AVR/MCTargetDesc/CMakeLists.txt +++ lib/Target/AVR/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ AVRAsmBackend.cpp AVRELFObjectWriter.cpp AVRELFStreamer.cpp + AVRInstPrinter.cpp AVRMCAsmInfo.cpp AVRMCCodeEmitter.cpp AVRMCELFStreamer.cpp Index: lib/Target/AVR/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/AVR/MCTargetDesc/LLVMBuild.txt +++ lib/Target/AVR/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = AVRDesc parent = AVR -required_libraries = MC AVRAsmPrinter AVRInfo Support +required_libraries = MC AVRInfo Support add_to_library_groups = AVR Index: lib/Target/BPF/BPFAsmPrinter.cpp =================================================================== --- lib/Target/BPF/BPFAsmPrinter.cpp +++ lib/Target/BPF/BPFAsmPrinter.cpp @@ -16,7 +16,7 @@ #include "BPFMCInstLower.h" #include "BPFTargetMachine.h" #include "BTFDebug.h" -#include "InstPrinter/BPFInstPrinter.h" +#include "MCTargetDesc/BPFInstPrinter.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: lib/Target/BPF/CMakeLists.txt =================================================================== --- lib/Target/BPF/CMakeLists.txt +++ lib/Target/BPF/CMakeLists.txt @@ -30,6 +30,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/BPF/InstPrinter/BPFInstPrinter.h =================================================================== --- lib/Target/BPF/InstPrinter/BPFInstPrinter.h +++ lib/Target/BPF/InstPrinter/BPFInstPrinter.h @@ -1,40 +0,0 @@ -//===-- BPFInstPrinter.h - Convert BPF MCInst to asm syntax -------*- C++ -*--// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a BPF MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_BPF_INSTPRINTER_BPFINSTPRINTER_H -#define LLVM_LIB_TARGET_BPF_INSTPRINTER_BPFINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { -class BPFInstPrinter : public MCInstPrinter { -public: - BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printImm64Operand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBrTargetOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); -}; -} - -#endif Index: lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp =================================================================== --- lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp +++ lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp @@ -1,107 +0,0 @@ -//===-- BPFInstPrinter.cpp - Convert BPF MCInst to asm syntax -------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an BPF MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "BPFInstPrinter.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#include "BPFGenAsmWriter.inc" - -void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -static void printExpr(const MCExpr *Expr, raw_ostream &O) { -#ifndef NDEBUG - const MCSymbolRefExpr *SRE; - - if (const MCBinaryExpr *BE = dyn_cast(Expr)) - SRE = dyn_cast(BE->getLHS()); - else - SRE = dyn_cast(Expr); - assert(SRE && "Unexpected MCExpr type."); - - MCSymbolRefExpr::VariantKind Kind = SRE->getKind(); - - assert(Kind == MCSymbolRefExpr::VK_None); -#endif - O << *Expr; -} - -void BPFInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier) { - assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - O << getRegisterName(Op.getReg()); - } else if (Op.isImm()) { - O << formatImm((int32_t)Op.getImm()); - } else { - assert(Op.isExpr() && "Expected an expression"); - printExpr(Op.getExpr(), O); - } -} - -void BPFInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier) { - const MCOperand &RegOp = MI->getOperand(OpNo); - const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); - - // register - assert(RegOp.isReg() && "Register operand not a register"); - O << getRegisterName(RegOp.getReg()); - - // offset - if (OffsetOp.isImm()) { - auto Imm = OffsetOp.getImm(); - if (Imm >= 0) - O << " + " << formatImm(Imm); - else - O << " - " << formatImm(-Imm); - } else { - assert(0 && "Expected an immediate"); - } -} - -void BPFInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) - O << formatImm(Op.getImm()); - else if (Op.isExpr()) - printExpr(Op.getExpr(), O); - else - O << Op; -} - -void BPFInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - int16_t Imm = Op.getImm(); - O << ((Imm >= 0) ? "+" : "") << formatImm(Imm); - } else if (Op.isExpr()) { - printExpr(Op.getExpr(), O); - } else { - O << Op; - } -} Index: lib/Target/BPF/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/BPF/InstPrinter/CMakeLists.txt +++ lib/Target/BPF/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMBPFAsmPrinter - BPFInstPrinter.cpp - ) Index: lib/Target/BPF/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/BPF/InstPrinter/LLVMBuild.txt +++ lib/Target/BPF/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/BPF/InstPrinter/LLVMBuild.txt ---------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = BPFAsmPrinter -parent = BPF -required_libraries = MC Support -add_to_library_groups = BPF Index: lib/Target/BPF/LLVMBuild.txt =================================================================== --- lib/Target/BPF/LLVMBuild.txt +++ lib/Target/BPF/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser InstPrinter Disassembler MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -33,7 +33,6 @@ CodeGen Core MC - BPFAsmPrinter BPFDesc BPFInfo SelectionDAG Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -12,7 +12,7 @@ #include "MCTargetDesc/BPFMCTargetDesc.h" #include "BPF.h" -#include "InstPrinter/BPFInstPrinter.h" +#include "MCTargetDesc/BPFInstPrinter.h" #include "MCTargetDesc/BPFMCAsmInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" Index: lib/Target/BPF/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/BPF/MCTargetDesc/CMakeLists.txt +++ lib/Target/BPF/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMBPFDesc BPFMCTargetDesc.cpp BPFAsmBackend.cpp + BPFInstPrinter.cpp BPFMCCodeEmitter.cpp BPFELFObjectWriter.cpp ) Index: lib/Target/BPF/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/BPF/MCTargetDesc/LLVMBuild.txt +++ lib/Target/BPF/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = BPFDesc parent = BPF -required_libraries = MC BPFAsmPrinter BPFInfo Support +required_libraries = MC BPFInfo Support add_to_library_groups = BPF Index: lib/Target/Lanai/CMakeLists.txt =================================================================== --- lib/Target/Lanai/CMakeLists.txt +++ lib/Target/Lanai/CMakeLists.txt @@ -31,6 +31,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/Lanai/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/Lanai/InstPrinter/CMakeLists.txt +++ lib/Target/Lanai/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMLanaiAsmPrinter - LanaiInstPrinter.cpp - ) Index: lib/Target/Lanai/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/Lanai/InstPrinter/LLVMBuild.txt +++ lib/Target/Lanai/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===-- ./lib/Target/Lanai/InstPrinter/LLVMBuild.txt ------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = LanaiAsmPrinter -parent = Lanai -required_libraries = MC Support -add_to_library_groups = Lanai Index: lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h =================================================================== --- lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h +++ lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h @@ -1,65 +0,0 @@ -//= LanaiInstPrinter.h - Convert Lanai MCInst to asm syntax -------*- C++ -*--// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a Lanai MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H -#define LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H - -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class LanaiInstPrinter : public MCInstPrinter { -public: - LanaiInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printCCOperand(const MCInst *MI, int OpNo, raw_ostream &O); - void printAluOperand(const MCInst *MI, int OpNo, raw_ostream &O); - void printHi16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printHi16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printLo16AndImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMemImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - -private: - bool printAlias(const MCInst *MI, raw_ostream &Ostream); - bool printInst(const MCInst *MI, raw_ostream &Ostream, StringRef Alias, - unsigned OpNo0, unsigned OpnNo1); - bool printMemoryLoadIncrement(const MCInst *MI, raw_ostream &Ostream, - StringRef Opcode, int AddOffset); - bool printMemoryStoreIncrement(const MCInst *MI, raw_ostream &Ostream, - StringRef Opcode, int AddOffset); -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H Index: lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp =================================================================== --- lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp +++ lib/Target/Lanai/InstPrinter/LanaiInstPrinter.cpp @@ -1,304 +0,0 @@ -//===-- LanaiInstPrinter.cpp - Convert Lanai MCInst to asm syntax ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an Lanai MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "LanaiInstPrinter.h" -#include "Lanai.h" -#include "MCTargetDesc/LanaiMCExpr.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "LanaiGenAsmWriter.inc" - -void LanaiInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << StringRef(getRegisterName(RegNo)).lower(); -} - -bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Alias, unsigned OpNo0, - unsigned OpNo1) { - OS << "\t" << Alias << " "; - printOperand(MI, OpNo0, OS); - OS << ", "; - printOperand(MI, OpNo1, OS); - return true; -} - -static bool usesGivenOffset(const MCInst *MI, int AddOffset) { - unsigned AluCode = MI->getOperand(3).getImm(); - return LPAC::encodeLanaiAluCode(AluCode) == LPAC::ADD && - (MI->getOperand(2).getImm() == AddOffset || - MI->getOperand(2).getImm() == -AddOffset); -} - -static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { - unsigned AluCode = MI->getOperand(3).getImm(); - return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); -} - -static bool isPostIncrementForm(const MCInst *MI, int AddOffset) { - unsigned AluCode = MI->getOperand(3).getImm(); - return LPAC::isPostOp(AluCode) && usesGivenOffset(MI, AddOffset); -} - -static StringRef decIncOperator(const MCInst *MI) { - if (MI->getOperand(2).getImm() < 0) - return "--"; - return "++"; -} - -bool LanaiInstPrinter::printMemoryLoadIncrement(const MCInst *MI, - raw_ostream &OS, - StringRef Opcode, - int AddOffset) { - if (isPreIncrementForm(MI, AddOffset)) { - OS << "\t" << Opcode << "\t[" << decIncOperator(MI) << "%" - << getRegisterName(MI->getOperand(1).getReg()) << "], %" - << getRegisterName(MI->getOperand(0).getReg()); - return true; - } - if (isPostIncrementForm(MI, AddOffset)) { - OS << "\t" << Opcode << "\t[%" - << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) - << "], %" << getRegisterName(MI->getOperand(0).getReg()); - return true; - } - return false; -} - -bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI, - raw_ostream &OS, - StringRef Opcode, - int AddOffset) { - if (isPreIncrementForm(MI, AddOffset)) { - OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg()) - << ", [" << decIncOperator(MI) << "%" - << getRegisterName(MI->getOperand(1).getReg()) << "]"; - return true; - } - if (isPostIncrementForm(MI, AddOffset)) { - OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg()) - << ", [%" << getRegisterName(MI->getOperand(1).getReg()) - << decIncOperator(MI) << "]"; - return true; - } - return false; -} - -bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) { - switch (MI->getOpcode()) { - case Lanai::LDW_RI: - // ld 4[*%rN], %rX => ld [++imm], %rX - // ld -4[*%rN], %rX => ld [--imm], %rX - // ld 4[%rN*], %rX => ld [imm++], %rX - // ld -4[%rN*], %rX => ld [imm--], %rX - return printMemoryLoadIncrement(MI, OS, "ld", 4); - case Lanai::LDHs_RI: - return printMemoryLoadIncrement(MI, OS, "ld.h", 2); - case Lanai::LDHz_RI: - return printMemoryLoadIncrement(MI, OS, "uld.h", 2); - case Lanai::LDBs_RI: - return printMemoryLoadIncrement(MI, OS, "ld.b", 1); - case Lanai::LDBz_RI: - return printMemoryLoadIncrement(MI, OS, "uld.b", 1); - case Lanai::SW_RI: - // st %rX, 4[*%rN] => st %rX, [++imm] - // st %rX, -4[*%rN] => st %rX, [--imm] - // st %rX, 4[%rN*] => st %rX, [imm++] - // st %rX, -4[%rN*] => st %rX, [imm--] - return printMemoryStoreIncrement(MI, OS, "st", 4); - case Lanai::STH_RI: - return printMemoryStoreIncrement(MI, OS, "st.h", 2); - case Lanai::STB_RI: - return printMemoryStoreIncrement(MI, OS, "st.b", 1); - default: - return false; - } -} - -void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annotation, - const MCSubtargetInfo & /*STI*/) { - if (!printAlias(MI, OS) && !printAliasInstr(MI, OS)) - printInstruction(MI, OS); - printAnnotation(OS, Annotation); -} - -void LanaiInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS, const char *Modifier) { - assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) - OS << "%" << getRegisterName(Op.getReg()); - else if (Op.isImm()) - OS << formatHex(Op.getImm()); - else { - assert(Op.isExpr() && "Expected an expression"); - Op.getExpr()->print(OS, &MAI); - } -} - -void LanaiInstPrinter::printMemImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - OS << '[' << formatHex(Op.getImm()) << ']'; - } else { - // Symbolic operand will be lowered to immediate value by linker - assert(Op.isExpr() && "Expected an expression"); - OS << '['; - Op.getExpr()->print(OS, &MAI); - OS << ']'; - } -} - -void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - OS << formatHex(Op.getImm() << 16); - } else { - // Symbolic operand will be lowered to immediate value by linker - assert(Op.isExpr() && "Expected an expression"); - Op.getExpr()->print(OS, &MAI); - } -} - -void LanaiInstPrinter::printHi16AndImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - OS << formatHex((Op.getImm() << 16) | 0xffff); - } else { - // Symbolic operand will be lowered to immediate value by linker - assert(Op.isExpr() && "Expected an expression"); - Op.getExpr()->print(OS, &MAI); - } -} - -void LanaiInstPrinter::printLo16AndImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - OS << formatHex(0xffff0000 | Op.getImm()); - } else { - // Symbolic operand will be lowered to immediate value by linker - assert(Op.isExpr() && "Expected an expression"); - Op.getExpr()->print(OS, &MAI); - } -} - -static void printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode, - const MCOperand &RegOp) { - assert(RegOp.isReg() && "Register operand expected"); - OS << "["; - if (LPAC::isPreOp(AluCode)) - OS << "*"; - OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); - if (LPAC::isPostOp(AluCode)) - OS << "*"; - OS << "]"; -} - -template -static void printMemoryImmediateOffset(const MCAsmInfo &MAI, - const MCOperand &OffsetOp, - raw_ostream &OS) { - assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); - if (OffsetOp.isImm()) { - assert(isInt(OffsetOp.getImm()) && "Constant value truncated"); - OS << OffsetOp.getImm(); - } else - OffsetOp.getExpr()->print(OS, &MAI); -} - -void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo, - raw_ostream &OS, - const char * /*Modifier*/) { - const MCOperand &RegOp = MI->getOperand(OpNo); - const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); - const MCOperand &AluOp = MI->getOperand(OpNo + 2); - const unsigned AluCode = AluOp.getImm(); - - // Offset - printMemoryImmediateOffset<16>(MAI, OffsetOp, OS); - - // Register - printMemoryBaseRegister(OS, AluCode, RegOp); -} - -void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo, - raw_ostream &OS, - const char * /*Modifier*/) { - const MCOperand &RegOp = MI->getOperand(OpNo); - const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); - const MCOperand &AluOp = MI->getOperand(OpNo + 2); - const unsigned AluCode = AluOp.getImm(); - assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); - - // [ Base OP Offset ] - OS << "["; - if (LPAC::isPreOp(AluCode)) - OS << "*"; - OS << "%" << getRegisterName(RegOp.getReg()); - if (LPAC::isPostOp(AluCode)) - OS << "*"; - OS << " " << LPAC::lanaiAluCodeToString(AluCode) << " "; - OS << "%" << getRegisterName(OffsetOp.getReg()); - OS << "]"; -} - -void LanaiInstPrinter::printMemSplsOperand(const MCInst *MI, int OpNo, - raw_ostream &OS, - const char * /*Modifier*/) { - const MCOperand &RegOp = MI->getOperand(OpNo); - const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); - const MCOperand &AluOp = MI->getOperand(OpNo + 2); - const unsigned AluCode = AluOp.getImm(); - - // Offset - printMemoryImmediateOffset<10>(MAI, OffsetOp, OS); - - // Register - printMemoryBaseRegister(OS, AluCode, RegOp); -} - -void LanaiInstPrinter::printCCOperand(const MCInst *MI, int OpNo, - raw_ostream &OS) { - LPCC::CondCode CC = - static_cast(MI->getOperand(OpNo).getImm()); - // Handle the undefined value here for printing so we don't abort(). - if (CC >= LPCC::UNKNOWN) - OS << ""; - else - OS << lanaiCondCodeToString(CC); -} - -void LanaiInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - LPCC::CondCode CC = - static_cast(MI->getOperand(OpNo).getImm()); - // Handle the undefined value here for printing so we don't abort(). - if (CC >= LPCC::UNKNOWN) - OS << ""; - else if (CC != LPCC::ICC_T) - OS << "." << lanaiCondCodeToString(CC); -} Index: lib/Target/Lanai/LLVMBuild.txt =================================================================== --- lib/Target/Lanai/LLVMBuild.txt +++ lib/Target/Lanai/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -35,7 +35,6 @@ LanaiAsmParser LanaiDesc LanaiInfo - LanaiAsmPrinter MC SelectionDAG Support Index: lib/Target/Lanai/LanaiAsmPrinter.cpp =================================================================== --- lib/Target/Lanai/LanaiAsmPrinter.cpp +++ lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/LanaiInstPrinter.h" +#include "MCTargetDesc/LanaiInstPrinter.h" #include "Lanai.h" #include "LanaiInstrInfo.h" #include "LanaiMCInstLower.h" Index: lib/Target/Lanai/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Lanai/MCTargetDesc/CMakeLists.txt +++ lib/Target/Lanai/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMLanaiDesc LanaiAsmBackend.cpp LanaiELFObjectWriter.cpp + LanaiInstPrinter.cpp LanaiMCAsmInfo.cpp LanaiMCCodeEmitter.cpp LanaiMCExpr.cpp Index: lib/Target/Lanai/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/Lanai/MCTargetDesc/LLVMBuild.txt +++ lib/Target/Lanai/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = LanaiDesc parent = Lanai -required_libraries = LanaiInfo LanaiAsmPrinter MC MCDisassembler Support +required_libraries = LanaiInfo MC MCDisassembler Support add_to_library_groups = Lanai Index: lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp =================================================================== --- lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "LanaiMCTargetDesc.h" -#include "InstPrinter/LanaiInstPrinter.h" +#include "LanaiInstPrinter.h" #include "LanaiMCAsmInfo.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" Index: lib/Target/MSP430/CMakeLists.txt =================================================================== --- lib/Target/MSP430/CMakeLists.txt +++ lib/Target/MSP430/CMakeLists.txt @@ -26,7 +26,6 @@ MSP430MCInstLower.cpp ) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(AsmParser) Index: lib/Target/MSP430/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/MSP430/InstPrinter/CMakeLists.txt +++ lib/Target/MSP430/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMMSP430AsmPrinter - MSP430InstPrinter.cpp - ) Index: lib/Target/MSP430/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/MSP430/InstPrinter/LLVMBuild.txt +++ lib/Target/MSP430/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/MSP430/InstPrinter/LLVMBuild.txt ------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = MSP430AsmPrinter -parent = MSP430 -required_libraries = MC Support -add_to_library_groups = MSP430 Index: lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h =================================================================== --- lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h +++ lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h @@ -1,49 +0,0 @@ -//= MSP430InstPrinter.h - Convert MSP430 MCInst to assembly syntax -*- C++ -*-// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a MSP430 MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_MSP430_INSTPRINTER_MSP430INSTPRINTER_H -#define LLVM_LIB_TARGET_MSP430_INSTPRINTER_MSP430INSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - class MSP430InstPrinter : public MCInstPrinter { - public: - MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - -private: - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = nullptr); - void printIndRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printPostIndRegOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O); - void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - }; -} - -#endif Index: lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp =================================================================== --- lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp +++ lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp @@ -1,137 +0,0 @@ -//===-- MSP430InstPrinter.cpp - Convert MSP430 MCInst to assembly syntax --===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an MSP430 MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "MSP430InstPrinter.h" -#include "MSP430.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "MSP430GenAsmWriter.inc" - -void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - if (!printAliasInstr(MI, O)) - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) { - int64_t Imm = Op.getImm() * 2 + 2; - O << "$"; - if (Imm >= 0) - O << '+'; - O << Imm; - } else { - assert(Op.isExpr() && "unknown pcrel immediate operand"); - Op.getExpr()->print(O, &MAI); - } -} - -void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier) { - assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported"); - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - O << getRegisterName(Op.getReg()); - } else if (Op.isImm()) { - O << '#' << Op.getImm(); - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - O << '#'; - Op.getExpr()->print(O, &MAI); - } -} - -void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, - const char *Modifier) { - const MCOperand &Base = MI->getOperand(OpNo); - const MCOperand &Disp = MI->getOperand(OpNo+1); - - // Print displacement first - - // If the global address expression is a part of displacement field with a - // register base, we should not emit any prefix symbol here, e.g. - // mov.w &foo, r1 - // vs - // mov.w glb(r1), r2 - // Otherwise (!) msp430-as will silently miscompile the output :( - if (Base.getReg() == MSP430::SR) - O << '&'; - - if (Disp.isExpr()) - Disp.getExpr()->print(O, &MAI); - else { - assert(Disp.isImm() && "Expected immediate in displacement field"); - O << Disp.getImm(); - } - - // Print register base field - if ((Base.getReg() != MSP430::SR) && - (Base.getReg() != MSP430::PC)) - O << '(' << getRegisterName(Base.getReg()) << ')'; -} - -void MSP430InstPrinter::printIndRegOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Base = MI->getOperand(OpNo); - O << "@" << getRegisterName(Base.getReg()); -} - -void MSP430InstPrinter::printPostIndRegOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Base = MI->getOperand(OpNo); - O << "@" << getRegisterName(Base.getReg()) << "+"; -} - -void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned CC = MI->getOperand(OpNo).getImm(); - - switch (CC) { - default: - llvm_unreachable("Unsupported CC code"); - case MSP430CC::COND_E: - O << "eq"; - break; - case MSP430CC::COND_NE: - O << "ne"; - break; - case MSP430CC::COND_HS: - O << "hs"; - break; - case MSP430CC::COND_LO: - O << "lo"; - break; - case MSP430CC::COND_GE: - O << "ge"; - break; - case MSP430CC::COND_L: - O << 'l'; - break; - case MSP430CC::COND_N: - O << 'n'; - break; - } -} Index: lib/Target/MSP430/LLVMBuild.txt =================================================================== --- lib/Target/MSP430/LLVMBuild.txt +++ lib/Target/MSP430/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -29,5 +29,5 @@ type = Library name = MSP430CodeGen parent = MSP430 -required_libraries = AsmPrinter CodeGen Core MC MSP430AsmPrinter MSP430Desc MSP430Info SelectionDAG Support Target +required_libraries = AsmPrinter CodeGen Core MC MSP430Desc MSP430Info SelectionDAG Support Target add_to_library_groups = MSP430 Index: lib/Target/MSP430/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/MSP430/MCTargetDesc/CMakeLists.txt +++ lib/Target/MSP430/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ MSP430AsmBackend.cpp MSP430ELFObjectWriter.cpp MSP430ELFStreamer.cpp + MSP430InstPrinter.cpp MSP430MCAsmInfo.cpp MSP430MCCodeEmitter.cpp MSP430MCTargetDesc.cpp Index: lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt +++ lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = MSP430Desc parent = MSP430 -required_libraries = MC MSP430AsmPrinter MSP430Info Support +required_libraries = MC MSP430Info Support add_to_library_groups = MSP430 Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "MSP430MCTargetDesc.h" -#include "InstPrinter/MSP430InstPrinter.h" +#include "MSP430InstPrinter.h" #include "MSP430MCAsmInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" Index: lib/Target/MSP430/MSP430AsmPrinter.cpp =================================================================== --- lib/Target/MSP430/MSP430AsmPrinter.cpp +++ lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/MSP430InstPrinter.h" +#include "MCTargetDesc/MSP430InstPrinter.h" #include "MSP430.h" #include "MSP430InstrInfo.h" #include "MSP430MCInstLower.h" Index: lib/Target/Mips/CMakeLists.txt =================================================================== --- lib/Target/Mips/CMakeLists.txt +++ lib/Target/Mips/CMakeLists.txt @@ -60,6 +60,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/Mips/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/Mips/InstPrinter/CMakeLists.txt +++ lib/Target/Mips/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMMipsAsmPrinter - MipsInstPrinter.cpp - ) Index: lib/Target/Mips/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/Mips/InstPrinter/LLVMBuild.txt +++ lib/Target/Mips/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/Mips/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = MipsAsmPrinter -parent = Mips -required_libraries = MC Support -add_to_library_groups = Mips Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.h =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.h +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.h @@ -1,112 +0,0 @@ -//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a Mips MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H -#define LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { -// These enumeration declarations were originally in MipsInstrInfo.h but -// had to be moved here to avoid circular dependencies between -// LLVMMipsCodeGen and LLVMMipsAsmPrinter. -namespace Mips { -// Mips Branch Codes -enum FPBranchCode { - BRANCH_F, - BRANCH_T, - BRANCH_FL, - BRANCH_TL, - BRANCH_INVALID -}; - -// Mips Condition Codes -enum CondCode { - // To be used with float branch True - FCOND_F, - FCOND_UN, - FCOND_OEQ, - FCOND_UEQ, - FCOND_OLT, - FCOND_ULT, - FCOND_OLE, - FCOND_ULE, - FCOND_SF, - FCOND_NGLE, - FCOND_SEQ, - FCOND_NGL, - FCOND_LT, - FCOND_NGE, - FCOND_LE, - FCOND_NGT, - - // To be used with float branch False - // This conditions have the same mnemonic as the - // above ones, but are used with a branch False; - FCOND_T, - FCOND_OR, - FCOND_UNE, - FCOND_ONE, - FCOND_UGE, - FCOND_OGE, - FCOND_UGT, - FCOND_OGT, - FCOND_ST, - FCOND_GLE, - FCOND_SNE, - FCOND_GL, - FCOND_NLT, - FCOND_GE, - FCOND_NLE, - FCOND_GT -}; - -const char *MipsFCCToString(Mips::CondCode CC); -} // end namespace Mips - -class MipsInstPrinter : public MCInstPrinter { -public: - MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); - -private: - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - template - void printUImm(const MCInst *MI, int opNum, raw_ostream &O); - void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); - void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); - void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O); - void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O); - - bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo, - raw_ostream &OS); - bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, - unsigned OpNo1, raw_ostream &OS); - bool printAlias(const MCInst &MI, raw_ostream &OS); - void printSaveRestore(const MCInst *MI, raw_ostream &O); - void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O); -}; -} // end namespace llvm - -#endif Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -1,287 +0,0 @@ -//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an Mips MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "MipsInstPrinter.h" -#include "MCTargetDesc/MipsMCExpr.h" -#include "MipsInstrInfo.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#define PRINT_ALIAS_INSTR -#include "MipsGenAsmWriter.inc" - -template -static bool isReg(const MCInst &MI, unsigned OpNo) { - assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); - return MI.getOperand(OpNo).getReg() == R; -} - -const char* Mips::MipsFCCToString(Mips::CondCode CC) { - switch (CC) { - case FCOND_F: - case FCOND_T: return "f"; - case FCOND_UN: - case FCOND_OR: return "un"; - case FCOND_OEQ: - case FCOND_UNE: return "eq"; - case FCOND_UEQ: - case FCOND_ONE: return "ueq"; - case FCOND_OLT: - case FCOND_UGE: return "olt"; - case FCOND_ULT: - case FCOND_OGE: return "ult"; - case FCOND_OLE: - case FCOND_UGT: return "ole"; - case FCOND_ULE: - case FCOND_OGT: return "ule"; - case FCOND_SF: - case FCOND_ST: return "sf"; - case FCOND_NGLE: - case FCOND_GLE: return "ngle"; - case FCOND_SEQ: - case FCOND_SNE: return "seq"; - case FCOND_NGL: - case FCOND_GL: return "ngl"; - case FCOND_LT: - case FCOND_NLT: return "lt"; - case FCOND_NGE: - case FCOND_GE: return "nge"; - case FCOND_LE: - case FCOND_NLE: return "le"; - case FCOND_NGT: - case FCOND_GT: return "ngt"; - } - llvm_unreachable("Impossible condition code!"); -} - -void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << '$' << StringRef(getRegisterName(RegNo)).lower(); -} - -void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - switch (MI->getOpcode()) { - default: - break; - case Mips::RDHWR: - case Mips::RDHWR64: - O << "\t.set\tpush\n"; - O << "\t.set\tmips32r2\n"; - break; - case Mips::Save16: - O << "\tsave\t"; - printSaveRestore(MI, O); - O << " # 16 bit inst\n"; - return; - case Mips::SaveX16: - O << "\tsave\t"; - printSaveRestore(MI, O); - O << "\n"; - return; - case Mips::Restore16: - O << "\trestore\t"; - printSaveRestore(MI, O); - O << " # 16 bit inst\n"; - return; - case Mips::RestoreX16: - O << "\trestore\t"; - printSaveRestore(MI, O); - O << "\n"; - return; - } - - // Try to print any aliases first. - if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) - printInstruction(MI, O); - printAnnotation(O, Annot); - - switch (MI->getOpcode()) { - default: - break; - case Mips::RDHWR: - case Mips::RDHWR64: - O << "\n\t.set\tpop"; - } -} - -void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - printRegName(O, Op.getReg()); - return; - } - - if (Op.isImm()) { - O << formatImm(Op.getImm()); - return; - } - - assert(Op.isExpr() && "unknown operand kind in printOperand"); - Op.getExpr()->print(O, &MAI, true); -} - -template -void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { - const MCOperand &MO = MI->getOperand(opNum); - if (MO.isImm()) { - uint64_t Imm = MO.getImm(); - Imm -= Offset; - Imm &= (1 << Bits) - 1; - Imm += Offset; - O << formatImm(Imm); - return; - } - - printOperand(MI, opNum, O); -} - -void MipsInstPrinter:: -printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { - // Load/Store memory operands -- imm($reg) - // If PIC target the target is loaded as the - // pattern lw $25,%call16($28) - - // opNum can be invalid if instruction had reglist as operand. - // MemOperand is always last operand of instruction (base + offset). - switch (MI->getOpcode()) { - default: - break; - case Mips::SWM32_MM: - case Mips::LWM32_MM: - case Mips::SWM16_MM: - case Mips::SWM16_MMR6: - case Mips::LWM16_MM: - case Mips::LWM16_MMR6: - opNum = MI->getNumOperands() - 2; - break; - } - - printOperand(MI, opNum+1, O); - O << "("; - printOperand(MI, opNum, O); - O << ")"; -} - -void MipsInstPrinter:: -printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) { - // when using stack locations for not load/store instructions - // print the same way as all normal 3 operand instructions. - printOperand(MI, opNum, O); - O << ", "; - printOperand(MI, opNum+1, O); -} - -void MipsInstPrinter:: -printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { - const MCOperand& MO = MI->getOperand(opNum); - O << MipsFCCToString((Mips::CondCode)MO.getImm()); -} - -void MipsInstPrinter:: -printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) { - llvm_unreachable("TODO"); -} - -bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, - unsigned OpNo, raw_ostream &OS) { - OS << "\t" << Str << "\t"; - printOperand(&MI, OpNo, OS); - return true; -} - -bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, - unsigned OpNo0, unsigned OpNo1, - raw_ostream &OS) { - printAlias(Str, MI, OpNo0, OS); - OS << ", "; - printOperand(&MI, OpNo1, OS); - return true; -} - -bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { - switch (MI.getOpcode()) { - case Mips::BEQ: - case Mips::BEQ_MM: - // beq $zero, $zero, $L2 => b $L2 - // beq $r0, $zero, $L2 => beqz $r0, $L2 - return (isReg(MI, 0) && isReg(MI, 1) && - printAlias("b", MI, 2, OS)) || - (isReg(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); - case Mips::BEQ64: - // beq $r0, $zero, $L2 => beqz $r0, $L2 - return isReg(MI, 1) && printAlias("beqz", MI, 0, 2, OS); - case Mips::BNE: - case Mips::BNE_MM: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - return isReg(MI, 1) && printAlias("bnez", MI, 0, 2, OS); - case Mips::BNE64: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - return isReg(MI, 1) && printAlias("bnez", MI, 0, 2, OS); - case Mips::BGEZAL: - // bgezal $zero, $L1 => bal $L1 - return isReg(MI, 0) && printAlias("bal", MI, 1, OS); - case Mips::BC1T: - // bc1t $fcc0, $L1 => bc1t $L1 - return isReg(MI, 0) && printAlias("bc1t", MI, 1, OS); - case Mips::BC1F: - // bc1f $fcc0, $L1 => bc1f $L1 - return isReg(MI, 0) && printAlias("bc1f", MI, 1, OS); - case Mips::JALR: - // jalr $ra, $r1 => jalr $r1 - return isReg(MI, 0) && printAlias("jalr", MI, 1, OS); - case Mips::JALR64: - // jalr $ra, $r1 => jalr $r1 - return isReg(MI, 0) && printAlias("jalr", MI, 1, OS); - case Mips::NOR: - case Mips::NOR_MM: - case Mips::NOR_MMR6: - // nor $r0, $r1, $zero => not $r0, $r1 - return isReg(MI, 2) && printAlias("not", MI, 0, 1, OS); - case Mips::NOR64: - // nor $r0, $r1, $zero => not $r0, $r1 - return isReg(MI, 2) && printAlias("not", MI, 0, 1, OS); - case Mips::OR: - // or $r0, $r1, $zero => move $r0, $r1 - return isReg(MI, 2) && printAlias("move", MI, 0, 1, OS); - default: return false; - } -} - -void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - if (i != 0) O << ", "; - if (MI->getOperand(i).isReg()) - printRegName(O, MI->getOperand(i).getReg()); - else - printUImm<16>(MI, i, O); - } -} - -void MipsInstPrinter:: -printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) { - // - 2 because register List is always first operand of instruction and it is - // always followed by memory operand (base + offset). - for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) { - if (i != opNum) - O << ", "; - printRegName(O, MI->getOperand(i).getReg()); - } -} Index: lib/Target/Mips/LLVMBuild.txt =================================================================== --- lib/Target/Mips/LLVMBuild.txt +++ lib/Target/Mips/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -36,7 +36,6 @@ CodeGen Core MC - MipsAsmPrinter MipsDesc MipsInfo SelectionDAG Index: lib/Target/Mips/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Mips/MCTargetDesc/CMakeLists.txt +++ lib/Target/Mips/MCTargetDesc/CMakeLists.txt @@ -4,6 +4,7 @@ MipsAsmBackend.cpp MipsELFObjectWriter.cpp MipsELFStreamer.cpp + MipsInstPrinter.cpp MipsMCAsmInfo.cpp MipsMCCodeEmitter.cpp MipsMCExpr.cpp Index: lib/Target/Mips/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/Mips/MCTargetDesc/LLVMBuild.txt +++ lib/Target/Mips/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = MipsDesc parent = Mips -required_libraries = MC MipsAsmPrinter MipsInfo Support +required_libraries = MC MipsInfo Support add_to_library_groups = Mips Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -11,9 +11,9 @@ //===----------------------------------------------------------------------===// #include "MipsMCTargetDesc.h" -#include "InstPrinter/MipsInstPrinter.h" #include "MipsAsmBackend.h" #include "MipsELFStreamer.h" +#include "MipsInstPrinter.h" #include "MipsMCAsmInfo.h" #include "MipsMCNaCl.h" #include "MipsTargetStreamer.h" Index: lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -11,8 +11,8 @@ //===----------------------------------------------------------------------===// #include "MipsTargetStreamer.h" -#include "InstPrinter/MipsInstPrinter.h" #include "MCTargetDesc/MipsABIInfo.h" +#include "MCTargetDesc/MipsInstPrinter.h" #include "MipsELFStreamer.h" #include "MipsMCExpr.h" #include "MipsMCTargetDesc.h" Index: lib/Target/Mips/MipsAsmPrinter.cpp =================================================================== --- lib/Target/Mips/MipsAsmPrinter.cpp +++ lib/Target/Mips/MipsAsmPrinter.cpp @@ -12,9 +12,9 @@ //===----------------------------------------------------------------------===// #include "MipsAsmPrinter.h" -#include "InstPrinter/MipsInstPrinter.h" #include "MCTargetDesc/MipsABIInfo.h" #include "MCTargetDesc/MipsBaseInfo.h" +#include "MCTargetDesc/MipsInstPrinter.h" #include "MCTargetDesc/MipsMCNaCl.h" #include "MCTargetDesc/MipsMCTargetDesc.h" #include "Mips.h" Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "MipsISelLowering.h" -#include "InstPrinter/MipsInstPrinter.h" #include "MCTargetDesc/MipsBaseInfo.h" +#include "MCTargetDesc/MipsInstPrinter.h" #include "MCTargetDesc/MipsMCTargetDesc.h" #include "MipsCCState.h" #include "MipsInstrInfo.h" Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "MipsSEInstrInfo.h" -#include "InstPrinter/MipsInstPrinter.h" +#include "MCTargetDesc/MipsInstPrinter.h" #include "MipsAnalyzeImmediate.h" #include "MipsMachineFunction.h" #include "MipsTargetMachine.h" Index: lib/Target/NVPTX/CMakeLists.txt =================================================================== --- lib/Target/NVPTX/CMakeLists.txt +++ lib/Target/NVPTX/CMakeLists.txt @@ -37,6 +37,5 @@ add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources}) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/NVPTX/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/NVPTX/InstPrinter/CMakeLists.txt +++ lib/Target/NVPTX/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMNVPTXAsmPrinter - NVPTXInstPrinter.cpp - ) Index: lib/Target/NVPTX/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/NVPTX/InstPrinter/LLVMBuild.txt +++ lib/Target/NVPTX/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/NVPTX/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = NVPTXAsmPrinter -parent = NVPTX -required_libraries = MC Support -add_to_library_groups = NVPTX Index: lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h =================================================================== --- lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h +++ lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h @@ -1,51 +0,0 @@ -//= NVPTXInstPrinter.h - Convert NVPTX MCInst to assembly syntax --*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an NVPTX MCInst to .ptx file syntax. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_NVPTX_INSTPRINTER_NVPTXINSTPRINTER_H -#define LLVM_LIB_TARGET_NVPTX_INSTPRINTER_NVPTXINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class MCSubtargetInfo; - -class NVPTXInstPrinter : public MCInstPrinter { -public: - NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, - const MCSubtargetInfo &STI) override; - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - // End - - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, - const char *Modifier = nullptr); - void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, - const char *Modifier = nullptr); - void printLdStCode(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier = nullptr); - void printMemOperand(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier = nullptr); - void printProtoIdent(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier = nullptr); -}; - -} - -#endif Index: lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp =================================================================== --- lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp +++ lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp @@ -1,295 +0,0 @@ -//===-- NVPTXInstPrinter.cpp - PTX assembly instruction printing ----------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Print MCInst instructions to .ptx format. -// -//===----------------------------------------------------------------------===// - -#include "InstPrinter/NVPTXInstPrinter.h" -#include "MCTargetDesc/NVPTXBaseInfo.h" -#include "NVPTX.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -#include -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#include "NVPTXGenAsmWriter.inc" - -NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - -void NVPTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - // Decode the virtual register - // Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister - unsigned RCId = (RegNo >> 28); - switch (RCId) { - default: report_fatal_error("Bad virtual register encoding"); - case 0: - // This is actually a physical register, so defer to the autogenerated - // register printer - OS << getRegisterName(RegNo); - return; - case 1: - OS << "%p"; - break; - case 2: - OS << "%rs"; - break; - case 3: - OS << "%r"; - break; - case 4: - OS << "%rd"; - break; - case 5: - OS << "%f"; - break; - case 6: - OS << "%fd"; - break; - case 7: - OS << "%h"; - break; - case 8: - OS << "%hh"; - break; - } - - unsigned VReg = RegNo & 0x0FFFFFFF; - OS << VReg; -} - -void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annot, const MCSubtargetInfo &STI) { - printInstruction(MI, OS); - - // Next always print the annotation. - printAnnotation(OS, Annot); -} - -void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned Reg = Op.getReg(); - printRegName(O, Reg); - } else if (Op.isImm()) { - O << markup(""); - } else { - assert(Op.isExpr() && "Unknown operand kind in printOperand"); - Op.getExpr()->print(O, &MAI); - } -} - -void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, - const char *Modifier) { - const MCOperand &MO = MI->getOperand(OpNum); - int64_t Imm = MO.getImm(); - - if (strcmp(Modifier, "ftz") == 0) { - // FTZ flag - if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) - O << ".ftz"; - } else if (strcmp(Modifier, "sat") == 0) { - // SAT flag - if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) - O << ".sat"; - } else if (strcmp(Modifier, "base") == 0) { - // Default operand - switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { - default: - return; - case NVPTX::PTXCvtMode::NONE: - break; - case NVPTX::PTXCvtMode::RNI: - O << ".rni"; - break; - case NVPTX::PTXCvtMode::RZI: - O << ".rzi"; - break; - case NVPTX::PTXCvtMode::RMI: - O << ".rmi"; - break; - case NVPTX::PTXCvtMode::RPI: - O << ".rpi"; - break; - case NVPTX::PTXCvtMode::RN: - O << ".rn"; - break; - case NVPTX::PTXCvtMode::RZ: - O << ".rz"; - break; - case NVPTX::PTXCvtMode::RM: - O << ".rm"; - break; - case NVPTX::PTXCvtMode::RP: - O << ".rp"; - break; - } - } else { - llvm_unreachable("Invalid conversion modifier"); - } -} - -void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, - const char *Modifier) { - const MCOperand &MO = MI->getOperand(OpNum); - int64_t Imm = MO.getImm(); - - if (strcmp(Modifier, "ftz") == 0) { - // FTZ flag - if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) - O << ".ftz"; - } else if (strcmp(Modifier, "base") == 0) { - switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { - default: - return; - case NVPTX::PTXCmpMode::EQ: - O << ".eq"; - break; - case NVPTX::PTXCmpMode::NE: - O << ".ne"; - break; - case NVPTX::PTXCmpMode::LT: - O << ".lt"; - break; - case NVPTX::PTXCmpMode::LE: - O << ".le"; - break; - case NVPTX::PTXCmpMode::GT: - O << ".gt"; - break; - case NVPTX::PTXCmpMode::GE: - O << ".ge"; - break; - case NVPTX::PTXCmpMode::LO: - O << ".lo"; - break; - case NVPTX::PTXCmpMode::LS: - O << ".ls"; - break; - case NVPTX::PTXCmpMode::HI: - O << ".hi"; - break; - case NVPTX::PTXCmpMode::HS: - O << ".hs"; - break; - case NVPTX::PTXCmpMode::EQU: - O << ".equ"; - break; - case NVPTX::PTXCmpMode::NEU: - O << ".neu"; - break; - case NVPTX::PTXCmpMode::LTU: - O << ".ltu"; - break; - case NVPTX::PTXCmpMode::LEU: - O << ".leu"; - break; - case NVPTX::PTXCmpMode::GTU: - O << ".gtu"; - break; - case NVPTX::PTXCmpMode::GEU: - O << ".geu"; - break; - case NVPTX::PTXCmpMode::NUM: - O << ".num"; - break; - case NVPTX::PTXCmpMode::NotANumber: - O << ".nan"; - break; - } - } else { - llvm_unreachable("Empty Modifier"); - } -} - -void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier) { - if (Modifier) { - const MCOperand &MO = MI->getOperand(OpNum); - int Imm = (int) MO.getImm(); - if (!strcmp(Modifier, "volatile")) { - if (Imm) - O << ".volatile"; - } else if (!strcmp(Modifier, "addsp")) { - switch (Imm) { - case NVPTX::PTXLdStInstCode::GLOBAL: - O << ".global"; - break; - case NVPTX::PTXLdStInstCode::SHARED: - O << ".shared"; - break; - case NVPTX::PTXLdStInstCode::LOCAL: - O << ".local"; - break; - case NVPTX::PTXLdStInstCode::PARAM: - O << ".param"; - break; - case NVPTX::PTXLdStInstCode::CONSTANT: - O << ".const"; - break; - case NVPTX::PTXLdStInstCode::GENERIC: - break; - default: - llvm_unreachable("Wrong Address Space"); - } - } else if (!strcmp(Modifier, "sign")) { - if (Imm == NVPTX::PTXLdStInstCode::Signed) - O << "s"; - else if (Imm == NVPTX::PTXLdStInstCode::Unsigned) - O << "u"; - else if (Imm == NVPTX::PTXLdStInstCode::Untyped) - O << "b"; - else if (Imm == NVPTX::PTXLdStInstCode::Float) - O << "f"; - else - llvm_unreachable("Unknown register type"); - } else if (!strcmp(Modifier, "vec")) { - if (Imm == NVPTX::PTXLdStInstCode::V2) - O << ".v2"; - else if (Imm == NVPTX::PTXLdStInstCode::V4) - O << ".v4"; - } else - llvm_unreachable("Unknown Modifier"); - } else - llvm_unreachable("Empty Modifier"); -} - -void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier) { - printOperand(MI, OpNum, O); - - if (Modifier && !strcmp(Modifier, "add")) { - O << ", "; - printOperand(MI, OpNum + 1, O); - } else { - if (MI->getOperand(OpNum + 1).isImm() && - MI->getOperand(OpNum + 1).getImm() == 0) - return; // don't print ',0' or '+0' - O << "+"; - printOperand(MI, OpNum + 1, O); - } -} - -void NVPTXInstPrinter::printProtoIdent(const MCInst *MI, int OpNum, - raw_ostream &O, const char *Modifier) { - const MCOperand &Op = MI->getOperand(OpNum); - assert(Op.isExpr() && "Call prototype is not an MCExpr?"); - const MCExpr *Expr = Op.getExpr(); - const MCSymbol &Sym = cast(Expr)->getSymbol(); - O << Sym.getName(); -} Index: lib/Target/NVPTX/LLVMBuild.txt =================================================================== --- lib/Target/NVPTX/LLVMBuild.txt +++ lib/Target/NVPTX/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = InstPrinter MCTargetDesc TargetInfo +subdirectories = MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -27,5 +27,5 @@ type = Library name = NVPTXCodeGen parent = NVPTX -required_libraries = Analysis AsmPrinter CodeGen Core IPO MC NVPTXAsmPrinter NVPTXDesc NVPTXInfo Scalar SelectionDAG Support Target TransformUtils Vectorize +required_libraries = Analysis AsmPrinter CodeGen Core IPO MC NVPTXDesc NVPTXInfo Scalar SelectionDAG Support Target TransformUtils Vectorize add_to_library_groups = NVPTX Index: lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt +++ lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,6 @@ add_llvm_library(LLVMNVPTXDesc NVPTXMCAsmInfo.cpp + NVPTXInstPrinter.cpp NVPTXMCTargetDesc.cpp NVPTXTargetStreamer.cpp ) Index: lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt +++ lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = NVPTXDesc parent = NVPTX -required_libraries = MC NVPTXAsmPrinter NVPTXInfo Support +required_libraries = MC NVPTXInfo Support add_to_library_groups = NVPTX Index: lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp @@ -10,7 +10,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/NVPTXInstPrinter.h" +#include "MCTargetDesc/NVPTXInstPrinter.h" #include "MCTargetDesc/NVPTXBaseInfo.h" #include "NVPTX.h" #include "llvm/MC/MCExpr.h" Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -10,7 +10,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/NVPTXInstPrinter.h" +#include "NVPTXInstPrinter.h" #include "NVPTXMCAsmInfo.h" #include "NVPTXMCTargetDesc.h" #include "NVPTXTargetStreamer.h" Index: lib/Target/NVPTX/NVPTXAsmPrinter.cpp =================================================================== --- lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "NVPTXAsmPrinter.h" -#include "InstPrinter/NVPTXInstPrinter.h" #include "MCTargetDesc/NVPTXBaseInfo.h" +#include "MCTargetDesc/NVPTXInstPrinter.h" #include "MCTargetDesc/NVPTXMCAsmInfo.h" #include "MCTargetDesc/NVPTXTargetStreamer.h" #include "NVPTX.h" Index: lib/Target/PowerPC/CMakeLists.txt =================================================================== --- lib/Target/PowerPC/CMakeLists.txt +++ lib/Target/PowerPC/CMakeLists.txt @@ -52,6 +52,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/PowerPC/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/PowerPC/InstPrinter/CMakeLists.txt +++ lib/Target/PowerPC/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMPowerPCAsmPrinter - PPCInstPrinter.cpp - ) Index: lib/Target/PowerPC/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/PowerPC/InstPrinter/LLVMBuild.txt +++ lib/Target/PowerPC/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/PowerPC/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = PowerPCAsmPrinter -parent = PowerPC -required_libraries = MC Support -add_to_library_groups = PowerPC Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h =================================================================== --- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h +++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h @@ -1,76 +0,0 @@ -//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an PPC MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H -#define LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H - -#include "llvm/ADT/Triple.h" -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class PPCInstPrinter : public MCInstPrinter { - Triple TT; -private: - bool showRegistersWithPercentPrefix(const char *RegName) const; - bool showRegistersWithPrefix() const; - const char *getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) const; - -public: - PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI, Triple T) - : MCInstPrinter(MAI, MII, MRI), TT(T) {} - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - raw_ostream &OS); - - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printPredicateOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier = nullptr); - void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O); -}; -} // end namespace llvm - -#endif Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp =================================================================== --- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -1,543 +0,0 @@ -//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an PPC MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "PPCInstPrinter.h" -#include "MCTargetDesc/PPCMCTargetDesc.h" -#include "MCTargetDesc/PPCPredicates.h" -#include "PPCInstrInfo.h" -#include "llvm/CodeGen/TargetOpcodes.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// FIXME: Once the integrated assembler supports full register names, tie this -// to the verbose-asm setting. -static cl::opt -FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), - cl::desc("Use full register names when printing assembly")); - -// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively. -static cl::opt -ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), - cl::desc("Prints full register names with vs{31-63} as v{0-31}")); - -// Prints full register names with percent symbol. -static cl::opt -FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, - cl::init(false), - cl::desc("Prints full register names with percent")); - -#define PRINT_ALIAS_INSTR -#include "PPCGenAsmWriter.inc" - -void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - const char *RegName = getRegisterName(RegNo); - if (RegName[0] == 'q' /* QPX */) { - // The system toolchain on the BG/Q does not understand QPX register names - // in .cfi_* directives, so print the name of the floating-point - // subregister instead. - std::string RN(RegName); - - RN[0] = 'f'; - OS << RN; - - return; - } - - OS << RegName; -} - -void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - // Check for slwi/srwi mnemonics. - if (MI->getOpcode() == PPC::RLWINM) { - unsigned char SH = MI->getOperand(2).getImm(); - unsigned char MB = MI->getOperand(3).getImm(); - unsigned char ME = MI->getOperand(4).getImm(); - bool useSubstituteMnemonic = false; - if (SH <= 31 && MB == 0 && ME == (31-SH)) { - O << "\tslwi "; useSubstituteMnemonic = true; - } - if (SH <= 31 && MB == (32-SH) && ME == 31) { - O << "\tsrwi "; useSubstituteMnemonic = true; - SH = 32-SH; - } - if (useSubstituteMnemonic) { - printOperand(MI, 0, O); - O << ", "; - printOperand(MI, 1, O); - O << ", " << (unsigned int)SH; - - printAnnotation(O, Annot); - return; - } - } - - if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && - MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { - O << "\tmr "; - printOperand(MI, 0, O); - O << ", "; - printOperand(MI, 1, O); - printAnnotation(O, Annot); - return; - } - - if (MI->getOpcode() == PPC::RLDICR || - MI->getOpcode() == PPC::RLDICR_32) { - unsigned char SH = MI->getOperand(2).getImm(); - unsigned char ME = MI->getOperand(3).getImm(); - // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH - if (63-SH == ME) { - O << "\tsldi "; - printOperand(MI, 0, O); - O << ", "; - printOperand(MI, 1, O); - O << ", " << (unsigned int)SH; - printAnnotation(O, Annot); - return; - } - } - - // dcbt[st] is printed manually here because: - // 1. The assembly syntax is different between embedded and server targets - // 2. We must print the short mnemonics for TH == 0 because the - // embedded/server syntax default will not be stable across assemblers - // The syntax for dcbt is: - // dcbt ra, rb, th [server] - // dcbt th, ra, rb [embedded] - // where th can be omitted when it is 0. dcbtst is the same. - if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { - unsigned char TH = MI->getOperand(0).getImm(); - O << "\tdcbt"; - if (MI->getOpcode() == PPC::DCBTST) - O << "st"; - if (TH == 16) - O << "t"; - O << " "; - - bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; - if (IsBookE && TH != 0 && TH != 16) - O << (unsigned int) TH << ", "; - - printOperand(MI, 1, O); - O << ", "; - printOperand(MI, 2, O); - - if (!IsBookE && TH != 0 && TH != 16) - O << ", " << (unsigned int) TH; - - printAnnotation(O, Annot); - return; - } - - if (MI->getOpcode() == PPC::DCBF) { - unsigned char L = MI->getOperand(0).getImm(); - if (!L || L == 1 || L == 3) { - O << "\tdcbf"; - if (L == 1 || L == 3) - O << "l"; - if (L == 3) - O << "p"; - O << " "; - - printOperand(MI, 1, O); - O << ", "; - printOperand(MI, 2, O); - - printAnnotation(O, Annot); - return; - } - } - - if (!printAliasInstr(MI, O)) - printInstruction(MI, O); - printAnnotation(O, Annot); -} - - -void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, - const char *Modifier) { - unsigned Code = MI->getOperand(OpNo).getImm(); - - if (StringRef(Modifier) == "cc") { - switch ((PPC::Predicate)Code) { - case PPC::PRED_LT_MINUS: - case PPC::PRED_LT_PLUS: - case PPC::PRED_LT: - O << "lt"; - return; - case PPC::PRED_LE_MINUS: - case PPC::PRED_LE_PLUS: - case PPC::PRED_LE: - O << "le"; - return; - case PPC::PRED_EQ_MINUS: - case PPC::PRED_EQ_PLUS: - case PPC::PRED_EQ: - O << "eq"; - return; - case PPC::PRED_GE_MINUS: - case PPC::PRED_GE_PLUS: - case PPC::PRED_GE: - O << "ge"; - return; - case PPC::PRED_GT_MINUS: - case PPC::PRED_GT_PLUS: - case PPC::PRED_GT: - O << "gt"; - return; - case PPC::PRED_NE_MINUS: - case PPC::PRED_NE_PLUS: - case PPC::PRED_NE: - O << "ne"; - return; - case PPC::PRED_UN_MINUS: - case PPC::PRED_UN_PLUS: - case PPC::PRED_UN: - O << "un"; - return; - case PPC::PRED_NU_MINUS: - case PPC::PRED_NU_PLUS: - case PPC::PRED_NU: - O << "nu"; - return; - case PPC::PRED_BIT_SET: - case PPC::PRED_BIT_UNSET: - llvm_unreachable("Invalid use of bit predicate code"); - } - llvm_unreachable("Invalid predicate code"); - } - - if (StringRef(Modifier) == "pm") { - switch ((PPC::Predicate)Code) { - case PPC::PRED_LT: - case PPC::PRED_LE: - case PPC::PRED_EQ: - case PPC::PRED_GE: - case PPC::PRED_GT: - case PPC::PRED_NE: - case PPC::PRED_UN: - case PPC::PRED_NU: - return; - case PPC::PRED_LT_MINUS: - case PPC::PRED_LE_MINUS: - case PPC::PRED_EQ_MINUS: - case PPC::PRED_GE_MINUS: - case PPC::PRED_GT_MINUS: - case PPC::PRED_NE_MINUS: - case PPC::PRED_UN_MINUS: - case PPC::PRED_NU_MINUS: - O << "-"; - return; - case PPC::PRED_LT_PLUS: - case PPC::PRED_LE_PLUS: - case PPC::PRED_EQ_PLUS: - case PPC::PRED_GE_PLUS: - case PPC::PRED_GT_PLUS: - case PPC::PRED_NE_PLUS: - case PPC::PRED_UN_PLUS: - case PPC::PRED_NU_PLUS: - O << "+"; - return; - case PPC::PRED_BIT_SET: - case PPC::PRED_BIT_UNSET: - llvm_unreachable("Invalid use of bit predicate code"); - } - llvm_unreachable("Invalid predicate code"); - } - - assert(StringRef(Modifier) == "reg" && - "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!"); - printOperand(MI, OpNo+1, O); -} - -void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned Code = MI->getOperand(OpNo).getImm(); - if (Code == 2) - O << "-"; - else if (Code == 3) - O << "+"; -} - -void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 1 && "Invalid u1imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 3 && "Invalid u2imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 8 && "Invalid u3imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 15 && "Invalid u4imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - int Value = MI->getOperand(OpNo).getImm(); - Value = SignExtend32<5>(Value); - O << (int)Value; -} - -void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 31 && "Invalid u5imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 63 && "Invalid u6imm argument!"); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned int Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 127 && "Invalid u7imm argument!"); - O << (unsigned int)Value; -} - -// Operands of BUILD_VECTOR are signed and we use this to print operands -// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and -// print as unsigned. -void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned char Value = MI->getOperand(OpNo).getImm(); - O << (unsigned int)Value; -} - -void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned short Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 1023 && "Invalid u10imm argument!"); - O << (unsigned short)Value; -} - -void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned short Value = MI->getOperand(OpNo).getImm(); - assert(Value <= 4095 && "Invalid u12imm argument!"); - O << (unsigned short)Value; -} - -void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (MI->getOperand(OpNo).isImm()) - O << (short)MI->getOperand(OpNo).getImm(); - else - printOperand(MI, OpNo, O); -} - -void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (MI->getOperand(OpNo).isImm()) - O << (unsigned short)MI->getOperand(OpNo).getImm(); - else - printOperand(MI, OpNo, O); -} - -void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (!MI->getOperand(OpNo).isImm()) - return printOperand(MI, OpNo, O); - - // Branches can take an immediate operand. This is used by the branch - // selection pass to print .+8, an eight byte displacement from the PC. - O << "."; - int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); - if (Imm >= 0) - O << "+"; - O << Imm; -} - -void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (!MI->getOperand(OpNo).isImm()) - return printOperand(MI, OpNo, O); - - O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); -} - - -void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned CCReg = MI->getOperand(OpNo).getReg(); - unsigned RegNo; - switch (CCReg) { - default: llvm_unreachable("Unknown CR register"); - case PPC::CR0: RegNo = 0; break; - case PPC::CR1: RegNo = 1; break; - case PPC::CR2: RegNo = 2; break; - case PPC::CR3: RegNo = 3; break; - case PPC::CR4: RegNo = 4; break; - case PPC::CR5: RegNo = 5; break; - case PPC::CR6: RegNo = 6; break; - case PPC::CR7: RegNo = 7; break; - } - O << (0x80 >> RegNo); -} - -void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - printS16ImmOperand(MI, OpNo, O); - O << '('; - if (MI->getOperand(OpNo+1).getReg() == PPC::R0) - O << "0"; - else - printOperand(MI, OpNo+1, O); - O << ')'; -} - -void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - // When used as the base register, r0 reads constant zero rather than - // the value contained in the register. For this reason, the darwin - // assembler requires that we print r0 as 0 (no r) when used as the base. - if (MI->getOperand(OpNo).getReg() == PPC::R0) - O << "0"; - else - printOperand(MI, OpNo, O); - O << ", "; - printOperand(MI, OpNo+1, O); -} - -void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must - // come at the _end_ of the expression. - const MCOperand &Op = MI->getOperand(OpNo); - const MCSymbolRefExpr *RefExp = nullptr; - const MCConstantExpr *ConstExp = nullptr; - if (const MCBinaryExpr *BinExpr = dyn_cast(Op.getExpr())) { - RefExp = cast(BinExpr->getLHS()); - ConstExp = cast(BinExpr->getRHS()); - } else - RefExp = cast(Op.getExpr()); - - O << RefExp->getSymbol().getName(); - O << '('; - printOperand(MI, OpNo+1, O); - O << ')'; - if (RefExp->getKind() != MCSymbolRefExpr::VK_None) - O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind()); - if (ConstExp != nullptr) - O << '+' << ConstExp->getValue(); -} - -/// showRegistersWithPercentPrefix - Check if this register name should be -/// printed with a percentage symbol as prefix. -bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { - if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX) - return false; - - switch (RegName[0]) { - default: - return false; - case 'r': - case 'f': - case 'q': - case 'v': - case 'c': - return true; - } -} - -/// getVerboseConditionalRegName - This method expands the condition register -/// when requested explicitly or targetting Darwin. -const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) - const { - if (!TT.isOSDarwin() && !FullRegNames) - return nullptr; - if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN) - return nullptr; - const char *CRBits[] = { - "lt", "gt", "eq", "un", - "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un", - "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un", - "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un", - "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un", - "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un", - "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un", - "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un" - }; - return CRBits[RegEncoding]; -} - -// showRegistersWithPrefix - This method determines whether registers -// should be number-only or include the prefix. -bool PPCInstPrinter::showRegistersWithPrefix() const { - if (TT.getOS() == Triple::AIX) - return false; - return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames; -} - -void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned Reg = Op.getReg(); - if (!ShowVSRNumsAsVR) - Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()), - Reg, OpNo); - - const char *RegName; - RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); - if (RegName == nullptr) - RegName = getRegisterName(Reg); - if (showRegistersWithPercentPrefix(RegName)) - O << "%"; - if (!showRegistersWithPrefix()) - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); - - O << RegName; - return; - } - - if (Op.isImm()) { - O << Op.getImm(); - return; - } - - assert(Op.isExpr() && "unknown operand kind in printOperand"); - Op.getExpr()->print(O, &MAI); -} - Index: lib/Target/PowerPC/LLVMBuild.txt =================================================================== --- lib/Target/PowerPC/LLVMBuild.txt +++ lib/Target/PowerPC/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -30,5 +30,5 @@ type = Library name = PowerPCCodeGen parent = PowerPC -required_libraries = Analysis AsmPrinter CodeGen Core MC PowerPCAsmPrinter PowerPCDesc PowerPCInfo Scalar SelectionDAG Support Target TransformUtils +required_libraries = Analysis AsmPrinter CodeGen Core MC PowerPCDesc PowerPCInfo Scalar SelectionDAG Support Target TransformUtils add_to_library_groups = PowerPC Index: lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt +++ lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,6 @@ add_llvm_library(LLVMPowerPCDesc PPCAsmBackend.cpp + PPCInstPrinter.cpp PPCMCTargetDesc.cpp PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp Index: lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt +++ lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = PowerPCDesc parent = PowerPC -required_libraries = MC PowerPCAsmPrinter PowerPCInfo Support +required_libraries = MC PowerPCInfo Support add_to_library_groups = PowerPC Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/PPCMCTargetDesc.h" -#include "InstPrinter/PPCInstPrinter.h" +#include "MCTargetDesc/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCAsmInfo.h" #include "PPCTargetStreamer.h" #include "llvm/ADT/StringRef.h" Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp +++ lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -15,7 +15,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/PPCInstPrinter.h" +#include "MCTargetDesc/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCExpr.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCPredicates.h" Index: lib/Target/RISCV/CMakeLists.txt =================================================================== --- lib/Target/RISCV/CMakeLists.txt +++ lib/Target/RISCV/CMakeLists.txt @@ -31,7 +31,6 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(Utils) Index: lib/Target/RISCV/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/RISCV/InstPrinter/CMakeLists.txt +++ lib/Target/RISCV/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMRISCVAsmPrinter - RISCVInstPrinter.cpp - ) Index: lib/Target/RISCV/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/RISCV/InstPrinter/LLVMBuild.txt +++ lib/Target/RISCV/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/RISCV/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = RISCVAsmPrinter -parent = RISCV -required_libraries = MC RISCVUtils Support -add_to_library_groups = RISCV Index: lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h =================================================================== --- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h @@ -1,54 +0,0 @@ -//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a RISCV MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_RISCV_INSTPRINTER_RISCVINSTPRINTER_H -#define LLVM_LIB_TARGET_RISCV_INSTPRINTER_RISCVINSTPRINTER_H - -#include "MCTargetDesc/RISCVMCTargetDesc.h" -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { -class MCOperand; - -class RISCVInstPrinter : public MCInstPrinter { -public: - RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - void printRegName(raw_ostream &O, unsigned RegNo) const override; - - void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O, const char *Modifier = nullptr); - void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFenceArg(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - const MCSubtargetInfo &STI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo, - unsigned AltIdx = RISCV::ABIRegAltName); -}; -} // namespace llvm - -#endif Index: lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp =================================================================== --- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp @@ -1,114 +0,0 @@ -//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an RISCV MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "RISCVInstPrinter.h" -#include "MCTargetDesc/RISCVMCExpr.h" -#include "Utils/RISCVBaseInfo.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "RISCVGenAsmWriter.inc" - -// Include the auto-generated portion of the compress emitter. -#define GEN_UNCOMPRESS_INSTR -#include "RISCVGenCompressInstEmitter.inc" - -static cl::opt - NoAliases("riscv-no-aliases", - cl::desc("Disable the emission of assembler pseudo instructions"), - cl::init(false), cl::Hidden); - -void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - bool Res = false; - const MCInst *NewMI = MI; - MCInst UncompressedMI; - if (!NoAliases) - Res = uncompressInst(UncompressedMI, *MI, MRI, STI); - if (Res) - NewMI = const_cast(&UncompressedMI); - if (NoAliases || !printAliasInstr(NewMI, STI, O)) - printInstruction(NewMI, STI, O); - printAnnotation(O, Annot); -} - -void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const { - O << getRegisterName(RegNo); -} - -void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O, - const char *Modifier) { - assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); - const MCOperand &MO = MI->getOperand(OpNo); - - if (MO.isReg()) { - printRegName(O, MO.getReg()); - return; - } - - if (MO.isImm()) { - O << MO.getImm(); - return; - } - - assert(MO.isExpr() && "Unknown operand kind in printOperand"); - MO.getExpr()->print(O, &MAI); -} - -void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNo).getImm(); - auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); - if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) - O << SysReg->Name; - else - O << Imm; -} - -void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned FenceArg = MI->getOperand(OpNo).getImm(); - assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); - - if ((FenceArg & RISCVFenceField::I) != 0) - O << 'i'; - if ((FenceArg & RISCVFenceField::O) != 0) - O << 'o'; - if ((FenceArg & RISCVFenceField::R) != 0) - O << 'r'; - if ((FenceArg & RISCVFenceField::W) != 0) - O << 'w'; - if (FenceArg == 0) - O << "unknown"; -} - -void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - auto FRMArg = - static_cast(MI->getOperand(OpNo).getImm()); - O << RISCVFPRndMode::roundingModeToString(FRMArg); -} Index: lib/Target/RISCV/LLVMBuild.txt =================================================================== --- lib/Target/RISCV/LLVMBuild.txt +++ lib/Target/RISCV/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc Utils +subdirectories = AsmParser Disassembler TargetInfo MCTargetDesc Utils [component_0] type = TargetGroup @@ -29,6 +29,6 @@ type = Library name = RISCVCodeGen parent = RISCV -required_libraries = AsmPrinter Core CodeGen MC RISCVAsmPrinter RISCVDesc +required_libraries = AsmPrinter Core CodeGen MC RISCVDesc RISCVInfo RISCVUtils SelectionDAG Support Target add_to_library_groups = RISCV Index: lib/Target/RISCV/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/RISCV/MCTargetDesc/CMakeLists.txt +++ lib/Target/RISCV/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMRISCVDesc RISCVAsmBackend.cpp RISCVELFObjectWriter.cpp + RISCVInstPrinter.cpp RISCVMCAsmInfo.cpp RISCVMCCodeEmitter.cpp RISCVMCExpr.cpp Index: lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt +++ lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = RISCVDesc parent = RISCV -required_libraries = MC RISCVAsmPrinter RISCVInfo RISCVUtils Support +required_libraries = MC RISCVInfo RISCVUtils Support add_to_library_groups = RISCV Index: lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp =================================================================== --- lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -11,8 +11,8 @@ //===----------------------------------------------------------------------===// #include "RISCVMCTargetDesc.h" -#include "InstPrinter/RISCVInstPrinter.h" #include "RISCVELFStreamer.h" +#include "RISCVInstPrinter.h" #include "RISCVMCAsmInfo.h" #include "RISCVTargetStreamer.h" #include "llvm/ADT/STLExtras.h" Index: lib/Target/RISCV/RISCVAsmPrinter.cpp =================================================================== --- lib/Target/RISCV/RISCVAsmPrinter.cpp +++ lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "RISCV.h" -#include "InstPrinter/RISCVInstPrinter.h" +#include "MCTargetDesc/RISCVInstPrinter.h" #include "MCTargetDesc/RISCVMCExpr.h" #include "RISCVTargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" Index: lib/Target/Sparc/CMakeLists.txt =================================================================== --- lib/Target/Sparc/CMakeLists.txt +++ lib/Target/Sparc/CMakeLists.txt @@ -30,6 +30,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/Sparc/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/Sparc/InstPrinter/CMakeLists.txt +++ lib/Target/Sparc/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMSparcAsmPrinter - SparcInstPrinter.cpp - ) Index: lib/Target/Sparc/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/Sparc/InstPrinter/LLVMBuild.txt +++ lib/Target/Sparc/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/Sparc/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = SparcAsmPrinter -parent = Sparc -required_libraries = MC Support -add_to_library_groups = Sparc Index: lib/Target/Sparc/InstPrinter/SparcInstPrinter.h =================================================================== --- lib/Target/Sparc/InstPrinter/SparcInstPrinter.h +++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.h @@ -1,56 +0,0 @@ -//===-- SparcInstPrinter.h - Convert Sparc MCInst to assembly syntax ------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an Sparc MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_SPARC_INSTPRINTER_SPARCINSTPRINTER_H -#define LLVM_LIB_TARGET_SPARC_INSTPRINTER_SPARCINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class SparcInstPrinter : public MCInstPrinter { -public: - SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &OS); - bool isV9(const MCSubtargetInfo &STI) const; - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - const MCSubtargetInfo &STI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, - raw_ostream &OS); - void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, - raw_ostream &OS, const char *Modifier = nullptr); - void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, - raw_ostream &OS); - bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &OS); - void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, - raw_ostream &O); -}; -} // end namespace llvm - -#endif Index: lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp =================================================================== --- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -1,219 +0,0 @@ -//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an Sparc MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "SparcInstPrinter.h" -#include "Sparc.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCRegisterInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target -// namespace. But SPARC backend uses "SP" as its namespace. -namespace llvm { -namespace Sparc { - using namespace SP; -} -} - -#define GET_INSTRUCTION_NAME -#define PRINT_ALIAS_INSTR -#include "SparcGenAsmWriter.inc" - -bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { - return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; -} - -void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const -{ - OS << '%' << StringRef(getRegisterName(RegNo)).lower(); -} - -void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) - printInstruction(MI, STI, O); - printAnnotation(O, Annot); -} - -bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, - const MCSubtargetInfo &STI, - raw_ostream &O) { - switch (MI->getOpcode()) { - default: return false; - case SP::JMPLrr: - case SP::JMPLri: { - if (MI->getNumOperands() != 3) - return false; - if (!MI->getOperand(0).isReg()) - return false; - switch (MI->getOperand(0).getReg()) { - default: return false; - case SP::G0: // jmp $addr | ret | retl - if (MI->getOperand(2).isImm() && - MI->getOperand(2).getImm() == 8) { - switch(MI->getOperand(1).getReg()) { - default: break; - case SP::I7: O << "\tret"; return true; - case SP::O7: O << "\tretl"; return true; - } - } - O << "\tjmp "; printMemOperand(MI, 1, STI, O); - return true; - case SP::O7: // call $addr - O << "\tcall "; printMemOperand(MI, 1, STI, O); - return true; - } - } - case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: - case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { - if (isV9(STI) - || (MI->getNumOperands() != 3) - || (!MI->getOperand(0).isReg()) - || (MI->getOperand(0).getReg() != SP::FCC0)) - return false; - // if V8, skip printing %fcc0. - switch(MI->getOpcode()) { - default: - case SP::V9FCMPS: O << "\tfcmps "; break; - case SP::V9FCMPD: O << "\tfcmpd "; break; - case SP::V9FCMPQ: O << "\tfcmpq "; break; - case SP::V9FCMPES: O << "\tfcmpes "; break; - case SP::V9FCMPED: O << "\tfcmped "; break; - case SP::V9FCMPEQ: O << "\tfcmpeq "; break; - } - printOperand(MI, 1, STI, O); - O << ", "; - printOperand(MI, 2, STI, O); - return true; - } - } -} - -void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand (opNum); - - if (MO.isReg()) { - printRegName(O, MO.getReg()); - return ; - } - - if (MO.isImm()) { - switch (MI->getOpcode()) { - default: - O << (int)MO.getImm(); - return; - - case SP::TICCri: // Fall through - case SP::TICCrr: // Fall through - case SP::TRAPri: // Fall through - case SP::TRAPrr: // Fall through - case SP::TXCCri: // Fall through - case SP::TXCCrr: // Fall through - // Only seven-bit values up to 127. - O << ((int) MO.getImm() & 0x7f); - return; - } - } - - assert(MO.isExpr() && "Unknown operand kind in printOperand"); - MO.getExpr()->print(O, &MAI); -} - -void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum, - const MCSubtargetInfo &STI, - raw_ostream &O, const char *Modifier) { - printOperand(MI, opNum, STI, O); - - // If this is an ADD operand, emit it like normal operands. - if (Modifier && !strcmp(Modifier, "arith")) { - O << ", "; - printOperand(MI, opNum+1, STI, O); - return; - } - const MCOperand &MO = MI->getOperand(opNum+1); - - if (MO.isReg() && MO.getReg() == SP::G0) - return; // don't print "+%g0" - if (MO.isImm() && MO.getImm() == 0) - return; // don't print "+0" - - O << "+"; - - printOperand(MI, opNum+1, STI, O); -} - -void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int CC = (int)MI->getOperand(opNum).getImm(); - switch (MI->getOpcode()) { - default: break; - case SP::FBCOND: - case SP::FBCONDA: - case SP::BPFCC: - case SP::BPFCCA: - case SP::BPFCCNT: - case SP::BPFCCANT: - case SP::MOVFCCrr: case SP::V9MOVFCCrr: - case SP::MOVFCCri: case SP::V9MOVFCCri: - case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: - case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: - case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC: - // Make sure CC is a fp conditional flag. - CC = (CC < 16) ? (CC + 16) : CC; - break; - case SP::CBCOND: - case SP::CBCONDA: - // Make sure CC is a cp conditional flag. - CC = (CC < 32) ? (CC + 32) : CC; - break; - } - O << SPARCCondCodeToString((SPCC::CondCodes)CC); -} - -bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX."); - return true; -} - -void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - static const char *const TagNames[] = { - "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore", - "#Lookaside", "#MemIssue", "#Sync"}; - - unsigned Imm = MI->getOperand(opNum).getImm(); - - if (Imm > 127) { - O << Imm; - return; - } - - bool First = true; - for (unsigned i = 0; i < sizeof(TagNames) / sizeof(char *); i++) { - if (Imm & (1 << i)) { - O << (First ? "" : " | ") << TagNames[i]; - First = false; - } - } -} Index: lib/Target/Sparc/LLVMBuild.txt =================================================================== --- lib/Target/Sparc/LLVMBuild.txt +++ lib/Target/Sparc/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -30,6 +30,6 @@ type = Library name = SparcCodeGen parent = Sparc -required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcAsmPrinter +required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcDesc SparcInfo Support Target add_to_library_groups = Sparc Index: lib/Target/Sparc/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Sparc/MCTargetDesc/CMakeLists.txt +++ lib/Target/Sparc/MCTargetDesc/CMakeLists.txt @@ -1,6 +1,7 @@ add_llvm_library(LLVMSparcDesc SparcAsmBackend.cpp SparcELFObjectWriter.cpp + SparcInstPrinter.cpp SparcMCAsmInfo.cpp SparcMCCodeEmitter.cpp SparcMCTargetDesc.cpp Index: lib/Target/Sparc/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/Sparc/MCTargetDesc/LLVMBuild.txt +++ lib/Target/Sparc/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = SparcDesc parent = Sparc -required_libraries = MC SparcAsmPrinter SparcInfo Support +required_libraries = MC SparcInfo Support add_to_library_groups = Sparc Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "SparcMCTargetDesc.h" -#include "InstPrinter/SparcInstPrinter.h" +#include "SparcInstPrinter.h" #include "SparcMCAsmInfo.h" #include "SparcTargetStreamer.h" #include "llvm/MC/MCInstrInfo.h" Index: lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "SparcTargetStreamer.h" -#include "InstPrinter/SparcInstPrinter.h" +#include "SparcInstPrinter.h" #include "llvm/Support/FormattedStream.h" using namespace llvm; Index: lib/Target/Sparc/SparcAsmPrinter.cpp =================================================================== --- lib/Target/Sparc/SparcAsmPrinter.cpp +++ lib/Target/Sparc/SparcAsmPrinter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/SparcInstPrinter.h" +#include "MCTargetDesc/SparcInstPrinter.h" #include "MCTargetDesc/SparcMCExpr.h" #include "MCTargetDesc/SparcTargetStreamer.h" #include "Sparc.h" Index: lib/Target/SystemZ/AsmParser/LLVMBuild.txt =================================================================== --- lib/Target/SystemZ/AsmParser/LLVMBuild.txt +++ lib/Target/SystemZ/AsmParser/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = SystemZAsmParser parent = SystemZ -required_libraries = MC MCParser Support SystemZDesc SystemZInfo SystemZAsmPrinter +required_libraries = MC MCParser Support SystemZDesc SystemZInfo add_to_library_groups = SystemZ Index: lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp =================================================================== --- lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/SystemZInstPrinter.h" +#include "MCTargetDesc/SystemZInstPrinter.h" #include "MCTargetDesc/SystemZMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" Index: lib/Target/SystemZ/CMakeLists.txt =================================================================== --- lib/Target/SystemZ/CMakeLists.txt +++ lib/Target/SystemZ/CMakeLists.txt @@ -39,6 +39,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/SystemZ/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/SystemZ/InstPrinter/CMakeLists.txt +++ lib/Target/SystemZ/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMSystemZAsmPrinter - SystemZInstPrinter.cpp - ) Index: lib/Target/SystemZ/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/SystemZ/InstPrinter/LLVMBuild.txt +++ lib/Target/SystemZ/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/SystemZ/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = SystemZAsmPrinter -parent = SystemZ -required_libraries = MC Support -add_to_library_groups = SystemZ Index: lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h =================================================================== --- lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h +++ lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h @@ -1,77 +0,0 @@ -//==- SystemZInstPrinter.h - Convert SystemZ MCInst to assembly --*- C++ -*-==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints a SystemZ MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_SYSTEMZ_INSTPRINTER_SYSTEMZINSTPRINTER_H -#define LLVM_LIB_TARGET_SYSTEMZ_INSTPRINTER_SYSTEMZINSTPRINTER_H - -#include "llvm/MC/MCInstPrinter.h" -#include - -namespace llvm { - -class MCOperand; - -class SystemZInstPrinter : public MCInstPrinter { -public: - SystemZInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - // Automatically generated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - // Print an address with the given base, displacement and index. - static void printAddress(unsigned Base, int64_t Disp, unsigned Index, - raw_ostream &O); - - // Print the given operand. - static void printOperand(const MCOperand &MO, const MCAsmInfo *MAI, - raw_ostream &O); - - // Override MCInstPrinter. - void printRegName(raw_ostream &O, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - -private: - // Print various types of operand. - void printOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printBDRAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printBDVAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU1ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU2ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU3ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printPCRelOperand(const MCInst *MI, int OpNum, raw_ostream &O); - void printPCRelTLSOperand(const MCInst *MI, int OpNum, raw_ostream &O); - - // Print the mnemonic for a condition-code mask ("ne", "lh", etc.) - // This forms part of the instruction name rather than the operand list. - void printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O); -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_SYSTEMZ_INSTPRINTER_SYSTEMZINSTPRINTER_H Index: lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp =================================================================== --- lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp +++ lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp @@ -1,233 +0,0 @@ -//===- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax -===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "SystemZInstPrinter.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/Support/raw_ostream.h" -#include -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#include "SystemZGenAsmWriter.inc" - -void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, - unsigned Index, raw_ostream &O) { - O << Disp; - if (Base || Index) { - O << '('; - if (Index) { - O << '%' << getRegisterName(Index); - if (Base) - O << ','; - } - if (Base) - O << '%' << getRegisterName(Base); - O << ')'; - } -} - -void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI, - raw_ostream &O) { - if (MO.isReg()) - O << '%' << getRegisterName(MO.getReg()); - else if (MO.isImm()) - O << MO.getImm(); - else if (MO.isExpr()) - MO.getExpr()->print(O, MAI); - else - llvm_unreachable("Invalid operand"); -} - -void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, - const MCSubtargetInfo &STI) { - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -void SystemZInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const { - O << '%' << getRegisterName(RegNo); -} - -template -static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt(Value) && "Invalid uimm argument"); - O << Value; -} - -template -static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isInt(Value) && "Invalid simm argument"); - O << Value; -} - -void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<1>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<2>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU3ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<3>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<4>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<6>(MI, OpNum, O); -} - -void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printSImmOperand<8>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<8>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU12ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<12>(MI, OpNum, O); -} - -void SystemZInstPrinter::printS16ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printSImmOperand<16>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU16ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<16>(MI, OpNum, O); -} - -void SystemZInstPrinter::printS32ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printSImmOperand<32>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU32ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<32>(MI, OpNum, O); -} - -void SystemZInstPrinter::printU48ImmOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printUImmOperand<48>(MI, OpNum, O); -} - -void SystemZInstPrinter::printPCRelOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNum); - if (MO.isImm()) { - O << "0x"; - O.write_hex(MO.getImm()); - } else - MO.getExpr()->print(O, &MAI); -} - -void SystemZInstPrinter::printPCRelTLSOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - // Output the PC-relative operand. - printPCRelOperand(MI, OpNum, O); - - // Output the TLS marker if present. - if ((unsigned)OpNum + 1 < MI->getNumOperands()) { - const MCOperand &MO = MI->getOperand(OpNum + 1); - const MCSymbolRefExpr &refExp = cast(*MO.getExpr()); - switch (refExp.getKind()) { - case MCSymbolRefExpr::VK_TLSGD: - O << ":tls_gdcall:"; - break; - case MCSymbolRefExpr::VK_TLSLDM: - O << ":tls_ldcall:"; - break; - default: - llvm_unreachable("Unexpected symbol kind"); - } - O << refExp.getSymbol().getName(); - } -} - -void SystemZInstPrinter::printOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printOperand(MI->getOperand(OpNum), &MAI, O); -} - -void SystemZInstPrinter::printBDAddrOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printAddress(MI->getOperand(OpNum).getReg(), - MI->getOperand(OpNum + 1).getImm(), 0, O); -} - -void SystemZInstPrinter::printBDXAddrOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printAddress(MI->getOperand(OpNum).getReg(), - MI->getOperand(OpNum + 1).getImm(), - MI->getOperand(OpNum + 2).getReg(), O); -} - -void SystemZInstPrinter::printBDLAddrOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - unsigned Base = MI->getOperand(OpNum).getReg(); - uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); - uint64_t Length = MI->getOperand(OpNum + 2).getImm(); - O << Disp << '(' << Length; - if (Base) - O << ",%" << getRegisterName(Base); - O << ')'; -} - -void SystemZInstPrinter::printBDRAddrOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - unsigned Base = MI->getOperand(OpNum).getReg(); - uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); - unsigned Length = MI->getOperand(OpNum + 2).getReg(); - O << Disp << "(%" << getRegisterName(Length); - if (Base) - O << ",%" << getRegisterName(Base); - O << ')'; -} - -void SystemZInstPrinter::printBDVAddrOperand(const MCInst *MI, int OpNum, - raw_ostream &O) { - printAddress(MI->getOperand(OpNum).getReg(), - MI->getOperand(OpNum + 1).getImm(), - MI->getOperand(OpNum + 2).getReg(), O); -} - -void SystemZInstPrinter::printCond4Operand(const MCInst *MI, int OpNum, - raw_ostream &O) { - static const char *const CondNames[] = { - "o", "h", "nle", "l", "nhe", "lh", "ne", - "e", "nlh", "he", "nl", "le", "nh", "no" - }; - uint64_t Imm = MI->getOperand(OpNum).getImm(); - assert(Imm > 0 && Imm < 15 && "Invalid condition"); - O << CondNames[Imm - 1]; -} Index: lib/Target/SystemZ/LLVMBuild.txt =================================================================== --- lib/Target/SystemZ/LLVMBuild.txt +++ lib/Target/SystemZ/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -30,5 +30,5 @@ type = Library name = SystemZCodeGen parent = SystemZ -required_libraries = Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support SystemZAsmPrinter SystemZDesc SystemZInfo Target +required_libraries = Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support SystemZDesc SystemZInfo Target add_to_library_groups = SystemZ Index: lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt +++ lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMSystemZDesc + SystemZInstPrinter.cpp SystemZMCAsmBackend.cpp SystemZMCAsmInfo.cpp SystemZMCCodeEmitter.cpp Index: lib/Target/SystemZ/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/SystemZ/MCTargetDesc/LLVMBuild.txt +++ lib/Target/SystemZ/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = SystemZDesc parent = SystemZ -required_libraries = MC Support SystemZAsmPrinter SystemZInfo +required_libraries = MC Support SystemZInfo add_to_library_groups = SystemZ Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "SystemZMCTargetDesc.h" -#include "InstPrinter/SystemZInstPrinter.h" +#include "SystemZInstPrinter.h" #include "SystemZMCAsmInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" Index: lib/Target/SystemZ/SystemZAsmPrinter.cpp =================================================================== --- lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "SystemZAsmPrinter.h" -#include "InstPrinter/SystemZInstPrinter.h" +#include "MCTargetDesc/SystemZInstPrinter.h" #include "SystemZConstantPoolValue.h" #include "SystemZMCInstLower.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" Index: lib/Target/WebAssembly/CMakeLists.txt =================================================================== --- lib/Target/WebAssembly/CMakeLists.txt +++ lib/Target/WebAssembly/CMakeLists.txt @@ -60,6 +60,5 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/WebAssembly/Disassembler/LLVMBuild.txt =================================================================== --- lib/Target/WebAssembly/Disassembler/LLVMBuild.txt +++ lib/Target/WebAssembly/Disassembler/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = WebAssemblyDisassembler parent = WebAssembly -required_libraries = MCDisassembler WebAssemblyInfo WebAssemblyAsmPrinter Support +required_libraries = MCDisassembler WebAssemblyInfo Support add_to_library_groups = WebAssembly Index: lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp =================================================================== --- lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp +++ lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp @@ -14,7 +14,7 @@ /// //===----------------------------------------------------------------------===// -#include "InstPrinter/WebAssemblyInstPrinter.h" +#include "MCTargetDesc/WebAssemblyInstPrinter.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" Index: lib/Target/WebAssembly/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/WebAssembly/InstPrinter/CMakeLists.txt +++ lib/Target/WebAssembly/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMWebAssemblyAsmPrinter - WebAssemblyInstPrinter.cpp - ) Index: lib/Target/WebAssembly/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/WebAssembly/InstPrinter/LLVMBuild.txt +++ lib/Target/WebAssembly/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/WebAssembly/InstPrinter/LLVMBuild.txt -------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = WebAssemblyAsmPrinter -parent = WebAssembly -required_libraries = MC Support -add_to_library_groups = WebAssembly Index: lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.h =================================================================== --- lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.h +++ lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.h @@ -1,65 +0,0 @@ -// WebAssemblyInstPrinter.h - Print wasm MCInst to assembly syntax -*- C++ -*-// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This class prints an WebAssembly MCInst to wasm file syntax. -/// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H -#define LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H - -#include "llvm/ADT/SmallVector.h" -#include "llvm/BinaryFormat/Wasm.h" -#include "llvm/MC/MCInstPrinter.h" -#include "llvm/Support/MachineValueType.h" - -namespace llvm { - -class MCSubtargetInfo; - -class WebAssemblyInstPrinter final : public MCInstPrinter { - uint64_t ControlFlowCounter = 0; - uint64_t EHPadStackCounter = 0; - SmallVector, 4> ControlFlowStack; - SmallVector EHPadStack; - - enum EHInstKind { TRY, CATCH, END_TRY }; - EHInstKind LastSeenEHInst = END_TRY; - -public: - WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI); - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, - const MCSubtargetInfo &STI) override; - - // Used by tblegen code. - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printBrList(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printWebAssemblyP2AlignOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O); - void printWebAssemblySignatureOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); -}; - -namespace WebAssembly { - -const char *typeToString(wasm::ValType Ty); -const char *anyTypeToString(unsigned Ty); - -} // end namespace WebAssembly - -} // end namespace llvm - -#endif Index: lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp =================================================================== --- lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp +++ lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp @@ -1,296 +0,0 @@ -//=- WebAssemblyInstPrinter.cpp - WebAssembly assembly instruction printing -=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// Print MCInst instructions to wasm format. -/// -//===----------------------------------------------------------------------===// - -#include "InstPrinter/WebAssemblyInstPrinter.h" -#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" -#include "WebAssembly.h" -#include "WebAssemblyMachineFunctionInfo.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#include "WebAssemblyGenAsmWriter.inc" - -WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - -void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, - unsigned RegNo) const { - assert(RegNo != WebAssemblyFunctionInfo::UnusedReg); - // Note that there's an implicit local.get/local.set here! - OS << "$" << RegNo; -} - -void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annot, - const MCSubtargetInfo &STI) { - // Print the instruction (this uses the AsmStrings from the .td files). - printInstruction(MI, OS); - - // Print any additional variadic operands. - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - if (Desc.isVariadic()) - for (auto I = Desc.getNumOperands(), E = MI->getNumOperands(); I < E; ++I) { - // FIXME: For CALL_INDIRECT_VOID, don't print a leading comma, because - // we have an extra flags operand which is not currently printed, for - // compatiblity reasons. - if (I != 0 && ((MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID && - MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID_S) || - I != Desc.getNumOperands())) - OS << ", "; - printOperand(MI, I, OS); - } - - // Print any added annotation. - printAnnotation(OS, Annot); - - if (CommentStream) { - // Observe any effects on the control flow stack, for use in annotating - // control flow label references. - unsigned Opc = MI->getOpcode(); - switch (Opc) { - default: - break; - - case WebAssembly::LOOP: - case WebAssembly::LOOP_S: - printAnnotation(OS, "label" + utostr(ControlFlowCounter) + ':'); - ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, true)); - break; - - case WebAssembly::BLOCK: - case WebAssembly::BLOCK_S: - ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, false)); - break; - - case WebAssembly::TRY: - case WebAssembly::TRY_S: - ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, false)); - EHPadStack.push_back(EHPadStackCounter++); - LastSeenEHInst = TRY; - break; - - case WebAssembly::END_LOOP: - case WebAssembly::END_LOOP_S: - if (ControlFlowStack.empty()) { - printAnnotation(OS, "End marker mismatch!"); - } else { - ControlFlowStack.pop_back(); - } - break; - - case WebAssembly::END_BLOCK: - case WebAssembly::END_BLOCK_S: - if (ControlFlowStack.empty()) { - printAnnotation(OS, "End marker mismatch!"); - } else { - printAnnotation( - OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':'); - } - break; - - case WebAssembly::END_TRY: - case WebAssembly::END_TRY_S: - if (ControlFlowStack.empty()) { - printAnnotation(OS, "End marker mismatch!"); - } else { - printAnnotation( - OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':'); - LastSeenEHInst = END_TRY; - } - break; - - case WebAssembly::CATCH: - case WebAssembly::CATCH_S: - if (EHPadStack.empty()) { - printAnnotation(OS, "try-catch mismatch!"); - } else { - printAnnotation(OS, "catch" + utostr(EHPadStack.pop_back_val()) + ':'); - } - break; - } - - // Annotate any control flow label references. - - // rethrow instruction does not take any depth argument and rethrows to the - // nearest enclosing catch scope, if any. If there's no enclosing catch - // scope, it throws up to the caller. - if (Opc == WebAssembly::RETHROW || Opc == WebAssembly::RETHROW_S) { - if (EHPadStack.empty()) { - printAnnotation(OS, "to caller"); - } else { - printAnnotation(OS, "down to catch" + utostr(EHPadStack.back())); - } - - } else { - unsigned NumFixedOperands = Desc.NumOperands; - SmallSet Printed; - for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I) { - // See if this operand denotes a basic block target. - if (I < NumFixedOperands) { - // A non-variable_ops operand, check its type. - if (Desc.OpInfo[I].OperandType != WebAssembly::OPERAND_BASIC_BLOCK) - continue; - } else { - // A variable_ops operand, which currently can be immediates (used in - // br_table) which are basic block targets, or for call instructions - // when using -wasm-keep-registers (in which case they are registers, - // and should not be processed). - if (!MI->getOperand(I).isImm()) - continue; - } - uint64_t Depth = MI->getOperand(I).getImm(); - if (!Printed.insert(Depth).second) - continue; - if (Depth >= ControlFlowStack.size()) { - printAnnotation(OS, "Invalid depth argument!"); - } else { - const auto &Pair = ControlFlowStack.rbegin()[Depth]; - printAnnotation(OS, utostr(Depth) + ": " + - (Pair.second ? "up" : "down") + " to label" + - utostr(Pair.first)); - } - } - } - } -} - -static std::string toString(const APFloat &FP) { - // Print NaNs with custom payloads specially. - if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && - !FP.bitwiseIsEqual( - APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) { - APInt AI = FP.bitcastToAPInt(); - return std::string(AI.isNegative() ? "-" : "") + "nan:0x" + - utohexstr(AI.getZExtValue() & - (AI.getBitWidth() == 32 ? INT64_C(0x007fffff) - : INT64_C(0x000fffffffffffff)), - /*LowerCase=*/true); - } - - // Use C99's hexadecimal floating-point representation. - static const size_t BufBytes = 128; - char Buf[BufBytes]; - auto Written = FP.convertToHexString( - Buf, /*hexDigits=*/0, /*upperCase=*/false, APFloat::rmNearestTiesToEven); - (void)Written; - assert(Written != 0); - assert(Written < BufBytes); - return Buf; -} - -void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - unsigned WAReg = Op.getReg(); - if (int(WAReg) >= 0) - printRegName(O, WAReg); - else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs()) - O << "$pop" << WebAssemblyFunctionInfo::getWARegStackId(WAReg); - else if (WAReg != WebAssemblyFunctionInfo::UnusedReg) - O << "$push" << WebAssemblyFunctionInfo::getWARegStackId(WAReg); - else - O << "$drop"; - // Add a '=' suffix if this is a def. - if (OpNo < MII.get(MI->getOpcode()).getNumDefs()) - O << '='; - } else if (Op.isImm()) { - O << Op.getImm(); - } else if (Op.isFPImm()) { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - const MCOperandInfo &Info = Desc.OpInfo[OpNo]; - if (Info.OperandType == WebAssembly::OPERAND_F32IMM) { - // TODO: MC converts all floating point immediate operands to double. - // This is fine for numeric values, but may cause NaNs to change bits. - O << ::toString(APFloat(float(Op.getFPImm()))); - } else { - assert(Info.OperandType == WebAssembly::OPERAND_F64IMM); - O << ::toString(APFloat(Op.getFPImm())); - } - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - Op.getExpr()->print(O, &MAI); - } -} - -void WebAssemblyInstPrinter::printBrList(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - O << "{"; - for (unsigned I = OpNo, E = MI->getNumOperands(); I != E; ++I) { - if (I != OpNo) - O << ", "; - O << MI->getOperand(I).getImm(); - } - O << "}"; -} - -void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI, - unsigned OpNo, - raw_ostream &O) { - int64_t Imm = MI->getOperand(OpNo).getImm(); - if (Imm == WebAssembly::GetDefaultP2Align(MI->getOpcode())) - return; - O << ":p2align=" << Imm; -} - -void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI, - unsigned OpNo, - raw_ostream &O) { - auto Imm = static_cast(MI->getOperand(OpNo).getImm()); - if (Imm != wasm::WASM_TYPE_NORESULT) - O << WebAssembly::anyTypeToString(Imm); -} - -// We have various enums representing a subset of these types, use this -// function to convert any of them to text. -const char *llvm::WebAssembly::anyTypeToString(unsigned Ty) { - switch (Ty) { - case wasm::WASM_TYPE_I32: - return "i32"; - case wasm::WASM_TYPE_I64: - return "i64"; - case wasm::WASM_TYPE_F32: - return "f32"; - case wasm::WASM_TYPE_F64: - return "f64"; - case wasm::WASM_TYPE_V128: - return "v128"; - case wasm::WASM_TYPE_FUNCREF: - return "funcref"; - case wasm::WASM_TYPE_FUNC: - return "func"; - case wasm::WASM_TYPE_EXCEPT_REF: - return "except_ref"; - case wasm::WASM_TYPE_NORESULT: - return "void"; - default: - return "invalid_type"; - } -} - -const char *llvm::WebAssembly::typeToString(wasm::ValType Ty) { - return anyTypeToString(static_cast(Ty)); -} Index: lib/Target/WebAssembly/LLVMBuild.txt =================================================================== --- lib/Target/WebAssembly/LLVMBuild.txt +++ lib/Target/WebAssembly/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -29,5 +29,5 @@ type = Library name = WebAssemblyCodeGen parent = WebAssembly -required_libraries = Analysis AsmPrinter BinaryFormat CodeGen Core MC Scalar SelectionDAG Support Target TransformUtils WebAssemblyAsmPrinter WebAssemblyDesc WebAssemblyInfo +required_libraries = Analysis AsmPrinter BinaryFormat CodeGen Core MC Scalar SelectionDAG Support Target TransformUtils WebAssemblyDesc WebAssemblyInfo add_to_library_groups = WebAssembly Index: lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt +++ lib/Target/WebAssembly/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,6 @@ add_llvm_library(LLVMWebAssemblyDesc WebAssemblyAsmBackend.cpp + WebAssemblyInstPrinter.cpp WebAssemblyMCAsmInfo.cpp WebAssemblyMCCodeEmitter.cpp WebAssemblyMCTargetDesc.cpp Index: lib/Target/WebAssembly/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/LLVMBuild.txt +++ lib/Target/WebAssembly/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = WebAssemblyDesc parent = WebAssembly -required_libraries = MC Support WebAssemblyAsmPrinter WebAssemblyInfo +required_libraries = MC Support WebAssemblyInfo add_to_library_groups = WebAssembly Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp @@ -11,7 +11,7 @@ /// //===----------------------------------------------------------------------===// -#include "InstPrinter/WebAssemblyInstPrinter.h" +#include "MCTargetDesc/WebAssemblyInstPrinter.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" #include "WebAssembly.h" #include "WebAssemblyMachineFunctionInfo.h" Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyMCTargetDesc.h" -#include "InstPrinter/WebAssemblyInstPrinter.h" +#include "WebAssemblyInstPrinter.h" #include "WebAssemblyMCAsmInfo.h" #include "WebAssemblyTargetStreamer.h" #include "llvm/MC/MCInstrInfo.h" Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyTargetStreamer.h" -#include "InstPrinter/WebAssemblyInstPrinter.h" +#include "WebAssemblyInstPrinter.h" #include "WebAssemblyMCTargetDesc.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionWasm.h" Index: lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -14,7 +14,7 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyAsmPrinter.h" -#include "InstPrinter/WebAssemblyInstPrinter.h" +#include "MCTargetDesc/WebAssemblyInstPrinter.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" #include "MCTargetDesc/WebAssemblyTargetStreamer.h" #include "WebAssembly.h" Index: lib/Target/X86/AsmParser/LLVMBuild.txt =================================================================== --- lib/Target/X86/AsmParser/LLVMBuild.txt +++ lib/Target/X86/AsmParser/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = X86AsmParser parent = X86 -required_libraries = MC MCParser Support X86Desc X86Info X86AsmPrinter +required_libraries = MC MCParser Support X86Desc X86Info add_to_library_groups = X86 Index: lib/Target/X86/AsmParser/X86AsmParser.cpp =================================================================== --- lib/Target/X86/AsmParser/X86AsmParser.cpp +++ lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/X86IntelInstPrinter.h" #include "MCTargetDesc/X86BaseInfo.h" +#include "MCTargetDesc/X86IntelInstPrinter.h" #include "MCTargetDesc/X86MCExpr.h" #include "MCTargetDesc/X86TargetStreamer.h" #include "X86AsmParserCommon.h" Index: lib/Target/X86/AsmParser/X86Operand.h =================================================================== --- lib/Target/X86/AsmParser/X86Operand.h +++ lib/Target/X86/AsmParser/X86Operand.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H -#include "InstPrinter/X86IntelInstPrinter.h" +#include "MCTargetDesc/X86IntelInstPrinter.h" #include "MCTargetDesc/X86MCTargetDesc.h" #include "X86AsmParserCommon.h" #include "llvm/ADT/STLExtras.h" Index: lib/Target/X86/CMakeLists.txt =================================================================== --- lib/Target/X86/CMakeLists.txt +++ lib/Target/X86/CMakeLists.txt @@ -74,7 +74,6 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) add_subdirectory(Utils) Index: lib/Target/X86/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/X86/InstPrinter/CMakeLists.txt +++ lib/Target/X86/InstPrinter/CMakeLists.txt @@ -1,6 +0,0 @@ -add_llvm_library(LLVMX86AsmPrinter - X86ATTInstPrinter.cpp - X86IntelInstPrinter.cpp - X86InstComments.cpp - X86InstPrinterCommon.cpp - ) Index: lib/Target/X86/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/X86/InstPrinter/LLVMBuild.txt +++ lib/Target/X86/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/X86/InstPrinter/LLVMBuild.txt ---------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = X86AsmPrinter -parent = X86 -required_libraries = MC Support X86Utils -add_to_library_groups = X86 Index: lib/Target/X86/InstPrinter/X86ATTInstPrinter.h =================================================================== --- lib/Target/X86/InstPrinter/X86ATTInstPrinter.h +++ lib/Target/X86/InstPrinter/X86ATTInstPrinter.h @@ -1,124 +0,0 @@ -//=- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax --*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an X86 MCInst to AT&T style .s file syntax. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H -#define LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H - -#include "X86InstPrinterCommon.h" - -namespace llvm { - -class X86ATTInstPrinter final : public X86InstPrinterCommon { -public: - X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : X86InstPrinterCommon(MAI, MII, MRI) {} - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, - const MCSubtargetInfo &STI) override; - bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); - - // Autogenerated by tblgen, returns true if we successfully printed an - // alias. - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &OS); - static const char *getRegisterName(unsigned RegNo); - - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override; - void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); - void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O); - void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O); - void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS); - void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - - void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - - void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - - void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printSrcIdx(MI, OpNo, O); - } - void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printDstIdx(MI, OpNo, O); - } - void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printDstIdx(MI, OpNo, O); - } - void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printDstIdx(MI, OpNo, O); - } - void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printDstIdx(MI, OpNo, O); - } - void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemOffset(MI, OpNo, O); - } - void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemOffset(MI, OpNo, O); - } - void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemOffset(MI, OpNo, O); - } - void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemOffset(MI, OpNo, O); - } - -private: - bool HasCustomInstComment; -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H Index: lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp =================================================================== --- lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -1,487 +0,0 @@ -//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file includes code for rendering MCInst instances as AT&T-style -// assembly. -// -//===----------------------------------------------------------------------===// - -#include "X86ATTInstPrinter.h" -#include "MCTargetDesc/X86BaseInfo.h" -#include "X86InstComments.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/Format.h" -#include "llvm/Support/raw_ostream.h" -#include -#include -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "X86GenAsmWriter.inc" - -void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << markup(""); -} - -void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annot, const MCSubtargetInfo &STI) { - // If verbose assembly is enabled, we can print some informative comments. - if (CommentStream) - HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII); - - printInstFlags(MI, OS); - - // Output CALLpcrel32 as "callq" in 64-bit mode. - // In Intel annotation it's always emitted as "call". - // - // TODO: Probably this hack should be redesigned via InstAlias in - // InstrInfo.td as soon as Requires clause is supported properly - // for InstAlias. - if (MI->getOpcode() == X86::CALLpcrel32 && - (STI.getFeatureBits()[X86::Mode64Bit])) { - OS << "\tcallq\t"; - printPCRelImm(MI, 0, OS); - } - // data16 and data32 both have the same encoding of 0x66. While data32 is - // valid only in 16 bit systems, data16 is valid in the rest. - // There seems to be some lack of support of the Requires clause that causes - // 0x66 to be interpreted as "data16" by the asm printer. - // Thus we add an adjustment here in order to print the "right" instruction. - else if (MI->getOpcode() == X86::DATA16_PREFIX && - STI.getFeatureBits()[X86::Mode16Bit]) { - OS << "\tdata32"; - } - // Try to print any aliases first. - else if (!printAliasInstr(MI, OS) && - !printVecCompareInstr(MI, OS)) - printInstruction(MI, OS); - - // Next always print the annotation. - printAnnotation(OS, Annot); -} - -bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI, - raw_ostream &OS) { - if (MI->getNumOperands() == 0 || - !MI->getOperand(MI->getNumOperands() - 1).isImm()) - return false; - - int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); - - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - - // Custom print the vector compare instructions to get the immediate - // translated into the mnemonic. - switch (MI->getOpcode()) { - case X86::CMPPDrmi: case X86::CMPPDrri: - case X86::CMPPSrmi: case X86::CMPPSrri: - case X86::CMPSDrm: case X86::CMPSDrr: - case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: - case X86::CMPSSrm: case X86::CMPSSrr: - case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: - if (Imm >= 0 && Imm <= 7) { - OS << '\t'; - printCMPMnemonic(MI, /*IsVCMP*/false, OS); - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) - printdwordmem(MI, 2, OS); - else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) - printqwordmem(MI, 2, OS); - else - printxmmwordmem(MI, 2, OS); - } else - printOperand(MI, 2, OS); - - // Skip operand 1 as its tied to the dest. - - OS << ", "; - printOperand(MI, 0, OS); - return true; - } - break; - - case X86::VCMPPDrmi: case X86::VCMPPDrri: - case X86::VCMPPDYrmi: case X86::VCMPPDYrri: - case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: - case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: - case X86::VCMPPDZrmi: case X86::VCMPPDZrri: - case X86::VCMPPSrmi: case X86::VCMPPSrri: - case X86::VCMPPSYrmi: case X86::VCMPPSYrri: - case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: - case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: - case X86::VCMPPSZrmi: case X86::VCMPPSZrri: - case X86::VCMPSDrm: case X86::VCMPSDrr: - case X86::VCMPSDZrm: case X86::VCMPSDZrr: - case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: - case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: - case X86::VCMPSSrm: case X86::VCMPSSrr: - case X86::VCMPSSZrm: case X86::VCMPSSZrr: - case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: - case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: - case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: - case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: - case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: - case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: - case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: - case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: - case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: - case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: - case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: - case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: - case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: - case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: - case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: - case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: - case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: - case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: - case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: - case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: - if (Imm >= 0 && Imm <= 31) { - OS << '\t'; - printCMPMnemonic(MI, /*IsVCMP*/true, OS); - - unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if (Desc.TSFlags & X86II::EVEX_B) { - // Broadcast form. - // Load size is based on W-bit. - if (Desc.TSFlags & X86II::VEX_W) - printqwordmem(MI, CurOp--, OS); - else - printdwordmem(MI, CurOp--, OS); - - // Print the number of elements broadcasted. - unsigned NumElts; - if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; - else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; - else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; - OS << "{1to" << NumElts << "}"; - } else { - if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) - printdwordmem(MI, CurOp--, OS); - else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) - printqwordmem(MI, CurOp--, OS); - else if (Desc.TSFlags & X86II::EVEX_L2) - printzmmwordmem(MI, CurOp--, OS); - else if (Desc.TSFlags & X86II::VEX_L) - printymmwordmem(MI, CurOp--, OS); - else - printxmmwordmem(MI, CurOp--, OS); - } - } else { - if (Desc.TSFlags & X86II::EVEX_B) - OS << "{sae}, "; - printOperand(MI, CurOp--, OS); - } - - OS << ", "; - printOperand(MI, CurOp--, OS); - OS << ", "; - printOperand(MI, 0, OS); - if (CurOp > 0) { - // Print mask operand. - OS << " {"; - printOperand(MI, CurOp--, OS); - OS << "}"; - } - - return true; - } - break; - - case X86::VPCOMBmi: case X86::VPCOMBri: - case X86::VPCOMDmi: case X86::VPCOMDri: - case X86::VPCOMQmi: case X86::VPCOMQri: - case X86::VPCOMUBmi: case X86::VPCOMUBri: - case X86::VPCOMUDmi: case X86::VPCOMUDri: - case X86::VPCOMUQmi: case X86::VPCOMUQri: - case X86::VPCOMUWmi: case X86::VPCOMUWri: - case X86::VPCOMWmi: case X86::VPCOMWri: - if (Imm >= 0 && Imm <= 7) { - OS << '\t'; - printVPCOMMnemonic(MI, OS); - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) - printxmmwordmem(MI, 2, OS); - else - printOperand(MI, 2, OS); - - OS << ", "; - printOperand(MI, 1, OS); - OS << ", "; - printOperand(MI, 0, OS); - return true; - } - break; - - case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: - case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: - case X86::VPCMPBZrmi: case X86::VPCMPBZrri: - case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: - case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: - case X86::VPCMPDZrmi: case X86::VPCMPDZrri: - case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: - case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: - case X86::VPCMPQZrmi: case X86::VPCMPQZrri: - case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: - case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: - case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: - case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: - case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: - case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: - case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: - case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: - case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: - case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: - case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri: - case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: - case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: - case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: - case X86::VPCMPWZrmi: case X86::VPCMPWZrri: - case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: - case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: - case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: - case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: - case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: - case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: - case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: - case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: - case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: - case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: - case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: - case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: - case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: - case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: - case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: - case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: - case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: - case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: - case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: - case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik: - case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: - case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: - case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: - case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: - case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: - case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: - case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: - case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: - case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: - case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: - case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: - case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: - case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: - case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: - case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: - case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: - if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) { - OS << '\t'; - printVPCMPMnemonic(MI, OS); - - unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if (Desc.TSFlags & X86II::EVEX_B) { - // Broadcast form. - // Load size is based on W-bit as only D and Q are supported. - if (Desc.TSFlags & X86II::VEX_W) - printqwordmem(MI, CurOp--, OS); - else - printdwordmem(MI, CurOp--, OS); - - // Print the number of elements broadcasted. - unsigned NumElts; - if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; - else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; - else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; - OS << "{1to" << NumElts << "}"; - } else { - if (Desc.TSFlags & X86II::EVEX_L2) - printzmmwordmem(MI, CurOp--, OS); - else if (Desc.TSFlags & X86II::VEX_L) - printymmwordmem(MI, CurOp--, OS); - else - printxmmwordmem(MI, CurOp--, OS); - } - } else { - printOperand(MI, CurOp--, OS); - } - - OS << ", "; - printOperand(MI, CurOp--, OS); - OS << ", "; - printOperand(MI, 0, OS); - if (CurOp > 0) { - // Print mask operand. - OS << " {"; - printOperand(MI, CurOp--, OS); - OS << "}"; - } - - return true; - } - break; - } - - return false; -} - -void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - printRegName(O, Op.getReg()); - } else if (Op.isImm()) { - // Print immediates as signed values. - int64_t Imm = Op.getImm(); - O << markup(""); - - // TODO: This should be in a helper function in the base class, so it can - // be used by other printers. - - // If there are no instruction-specific comments, add a comment clarifying - // the hex value of the immediate operand when it isn't in the range - // [-256,255]. - if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) { - // Don't print unnecessary hex sign bits. - if (Imm == (int16_t)(Imm)) - *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm); - else if (Imm == (int32_t)(Imm)) - *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm); - else - *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm); - } - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - O << markup("print(O, &MAI); - O << markup(">"); - } -} - -void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, - raw_ostream &O) { - const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); - const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); - const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp); - - O << markup("print(O, &MAI); - } - - if (IndexReg.getReg() || BaseReg.getReg()) { - O << '('; - if (BaseReg.getReg()) - printOperand(MI, Op + X86::AddrBaseReg, O); - - if (IndexReg.getReg()) { - O << ','; - printOperand(MI, Op + X86::AddrIndexReg, O); - unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm(); - if (ScaleVal != 1) { - O << ',' << markup(""); - } - } - O << ')'; - } - - O << markup(">"); -} - -void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, - raw_ostream &O) { - O << markup(""); -} - -void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, - raw_ostream &O) { - O << markup(""); -} - -void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, - raw_ostream &O) { - const MCOperand &DispSpec = MI->getOperand(Op); - - O << markup("print(O, &MAI); - } - - O << markup(">"); -} - -void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op, - raw_ostream &O) { - if (MI->getOperand(Op).isExpr()) - return printOperand(MI, Op, O); - - O << markup("getOperand(Op).getImm() & 0xff) - << markup(">"); -} - -void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - unsigned Reg = Op.getReg(); - // Override the default printing to print st(0) instead st. - if (Reg == X86::ST0) - OS << markup(""); - else - printRegName(OS, Reg); -} Index: lib/Target/X86/InstPrinter/X86InstComments.h =================================================================== --- lib/Target/X86/InstPrinter/X86InstComments.h +++ lib/Target/X86/InstPrinter/X86InstComments.h @@ -1,26 +0,0 @@ -//=- X86InstComments.h - Generate verbose-asm comments for instrs -*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This defines functionality used to emit comments about X86 instructions to -// an output stream for -fverbose-asm. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTCOMMENTS_H -#define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTCOMMENTS_H - -namespace llvm { - - class MCInst; - class MCInstrInfo; - class raw_ostream; - bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, - const MCInstrInfo &MCII); -} - -#endif Index: lib/Target/X86/InstPrinter/X86InstComments.cpp =================================================================== --- lib/Target/X86/InstPrinter/X86InstComments.cpp +++ lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -1,1310 +0,0 @@ -//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This defines functionality used to emit comments about X86 instructions to -// an output stream for -fverbose-asm. -// -//===----------------------------------------------------------------------===// - -#include "X86InstComments.h" -#include "X86ATTInstPrinter.h" -#include "MCTargetDesc/X86BaseInfo.h" -#include "MCTargetDesc/X86MCTargetDesc.h" -#include "Utils/X86ShuffleDecode.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -#define CASE_SSE_INS_COMMON(Inst, src) \ - case X86::Inst##src: - -#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ - case X86::V##Inst##Suffix##src: - -#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ - case X86::V##Inst##Suffix##src##k: - -#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \ - case X86::V##Inst##Suffix##src##kz: - -#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \ - CASE_AVX_INS_COMMON(Inst, Suffix, src) \ - CASE_MASK_INS_COMMON(Inst, Suffix, src) \ - CASE_MASKZ_INS_COMMON(Inst, Suffix, src) - -#define CASE_MOVDUP(Inst, src) \ - CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ - CASE_AVX_INS_COMMON(Inst, , r##src) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src) \ - CASE_SSE_INS_COMMON(Inst, r##src) - -#define CASE_MASK_MOVDUP(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src) - -#define CASE_MASKZ_MOVDUP(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) - -#define CASE_PMOVZX(Inst, src) \ - CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ - CASE_AVX_INS_COMMON(Inst, , r##src) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src) \ - CASE_SSE_INS_COMMON(Inst, r##src) - -#define CASE_MASK_PMOVZX(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src) - -#define CASE_MASKZ_PMOVZX(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) - -#define CASE_UNPCK(Inst, src) \ - CASE_AVX512_INS_COMMON(Inst, Z, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \ - CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \ - CASE_AVX_INS_COMMON(Inst, , r##src) \ - CASE_AVX_INS_COMMON(Inst, Y, r##src) \ - CASE_SSE_INS_COMMON(Inst, r##src) - -#define CASE_MASK_UNPCK(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src) - -#define CASE_MASKZ_UNPCK(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \ - CASE_MASKZ_INS_COMMON(Inst, Z128, r##src) - -#define CASE_SHUF(Inst, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z128, suf) \ - CASE_AVX_INS_COMMON(Inst, , suf) \ - CASE_AVX_INS_COMMON(Inst, Y, suf) \ - CASE_SSE_INS_COMMON(Inst, suf) - -#define CASE_MASK_SHUF(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ - CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) - -#define CASE_MASKZ_SHUF(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \ - CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i) - -#define CASE_VPERMILPI(Inst, src) \ - CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ - CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ - CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \ - CASE_AVX_INS_COMMON(Inst, , src##i) \ - CASE_AVX_INS_COMMON(Inst, Y, src##i) - -#define CASE_MASK_VPERMILPI(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, src##i) \ - CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ - CASE_MASK_INS_COMMON(Inst, Z128, src##i) - -#define CASE_MASKZ_VPERMILPI(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \ - CASE_MASKZ_INS_COMMON(Inst, Z128, src##i) - -#define CASE_VPERM(Inst, src) \ - CASE_AVX512_INS_COMMON(Inst, Z, src##i) \ - CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \ - CASE_AVX_INS_COMMON(Inst, Y, src##i) - -#define CASE_MASK_VPERM(Inst, src) \ - CASE_MASK_INS_COMMON(Inst, Z, src##i) \ - CASE_MASK_INS_COMMON(Inst, Z256, src##i) - -#define CASE_MASKZ_VPERM(Inst, src) \ - CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \ - CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) - -#define CASE_VSHUF(Inst, src) \ - CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ - CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ - CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ - CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i) - -#define CASE_MASK_VSHUF(Inst, src) \ - CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ - CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) - -#define CASE_MASKZ_VSHUF(Inst, src) \ - CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ - CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ - CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ - CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i) - -#define CASE_AVX512_FMA(Inst, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z256, suf) \ - CASE_AVX512_INS_COMMON(Inst, Z128, suf) - -#define CASE_FMA(Inst, suf) \ - CASE_AVX512_FMA(Inst, suf) \ - CASE_AVX_INS_COMMON(Inst, , suf) \ - CASE_AVX_INS_COMMON(Inst, Y, suf) - -#define CASE_FMA_PACKED_REG(Inst) \ - CASE_FMA(Inst##PD, r) \ - CASE_FMA(Inst##PS, r) - -#define CASE_FMA_PACKED_MEM(Inst) \ - CASE_FMA(Inst##PD, m) \ - CASE_FMA(Inst##PS, m) \ - CASE_AVX512_FMA(Inst##PD, mb) \ - CASE_AVX512_FMA(Inst##PS, mb) - -#define CASE_FMA_SCALAR_REG(Inst) \ - CASE_AVX_INS_COMMON(Inst##SD, , r) \ - CASE_AVX_INS_COMMON(Inst##SS, , r) \ - CASE_AVX_INS_COMMON(Inst##SD, , r_Int) \ - CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \ - CASE_AVX_INS_COMMON(Inst##SD, Z, r) \ - CASE_AVX_INS_COMMON(Inst##SS, Z, r) \ - CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \ - CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int) - -#define CASE_FMA_SCALAR_MEM(Inst) \ - CASE_AVX_INS_COMMON(Inst##SD, , m) \ - CASE_AVX_INS_COMMON(Inst##SS, , m) \ - CASE_AVX_INS_COMMON(Inst##SD, , m_Int) \ - CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \ - CASE_AVX_INS_COMMON(Inst##SD, Z, m) \ - CASE_AVX_INS_COMMON(Inst##SS, Z, m) \ - CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \ - CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int) - -static unsigned getVectorRegSize(unsigned RegNo) { - if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31) - return 512; - if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31) - return 256; - if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31) - return 128; - if (X86::MM0 <= RegNo && RegNo <= X86::MM7) - return 64; - - llvm_unreachable("Unknown vector reg!"); -} - -static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, - unsigned OperandIndex) { - unsigned OpReg = MI->getOperand(OperandIndex).getReg(); - return getVectorRegSize(OpReg) / ScalarSize; -} - -static const char *getRegName(unsigned Reg) { - return X86ATTInstPrinter::getRegisterName(Reg); -} - -/// Wraps the destination register name with AVX512 mask/maskz filtering. -static void printMasking(raw_ostream &OS, const MCInst *MI, - const MCInstrInfo &MCII) { - const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); - uint64_t TSFlags = Desc.TSFlags; - - if (!(TSFlags & X86II::EVEX_K)) - return; - - bool MaskWithZero = (TSFlags & X86II::EVEX_Z); - unsigned MaskOp = Desc.getNumDefs(); - - if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) - ++MaskOp; - - const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); - - // MASK: zmmX {%kY} - OS << " {%" << MaskRegName << "}"; - - // MASKZ: zmmX {%kY} {z} - if (MaskWithZero) - OS << " {z}"; -} - -static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) { - const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr; - unsigned NumOperands = MI->getNumOperands(); - bool RegForm = false; - bool Negate = false; - StringRef AccStr = "+"; - - // The operands for FMA instructions without rounding fall into two forms. - // dest, src1, src2, src3 - // dest, src1, mask, src2, src3 - // Where src3 is either a register or 5 memory address operands. So to find - // dest and src1 we can index from the front. To find src2 and src3 we can - // index from the end by taking into account memory vs register form when - // finding src2. - - switch (MI->getOpcode()) { - default: - return false; - CASE_FMA_PACKED_REG(FMADD132) - CASE_FMA_SCALAR_REG(FMADD132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADD132) - CASE_FMA_SCALAR_MEM(FMADD132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - break; - - CASE_FMA_PACKED_REG(FMADD213) - CASE_FMA_SCALAR_REG(FMADD213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADD213) - CASE_FMA_SCALAR_MEM(FMADD213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - break; - - CASE_FMA_PACKED_REG(FMADD231) - CASE_FMA_SCALAR_REG(FMADD231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADD231) - CASE_FMA_SCALAR_MEM(FMADD231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - break; - - CASE_FMA_PACKED_REG(FMSUB132) - CASE_FMA_SCALAR_REG(FMSUB132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUB132) - CASE_FMA_SCALAR_MEM(FMSUB132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - break; - - CASE_FMA_PACKED_REG(FMSUB213) - CASE_FMA_SCALAR_REG(FMSUB213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUB213) - CASE_FMA_SCALAR_MEM(FMSUB213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - break; - - CASE_FMA_PACKED_REG(FMSUB231) - CASE_FMA_SCALAR_REG(FMSUB231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUB231) - CASE_FMA_SCALAR_MEM(FMSUB231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - break; - - CASE_FMA_PACKED_REG(FNMADD132) - CASE_FMA_SCALAR_REG(FNMADD132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMADD132) - CASE_FMA_SCALAR_MEM(FNMADD132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - Negate = true; - break; - - CASE_FMA_PACKED_REG(FNMADD213) - CASE_FMA_SCALAR_REG(FNMADD213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMADD213) - CASE_FMA_SCALAR_MEM(FNMADD213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - Negate = true; - break; - - CASE_FMA_PACKED_REG(FNMADD231) - CASE_FMA_SCALAR_REG(FNMADD231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMADD231) - CASE_FMA_SCALAR_MEM(FNMADD231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - Negate = true; - break; - - CASE_FMA_PACKED_REG(FNMSUB132) - CASE_FMA_SCALAR_REG(FNMSUB132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMSUB132) - CASE_FMA_SCALAR_MEM(FNMSUB132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - Negate = true; - break; - - CASE_FMA_PACKED_REG(FNMSUB213) - CASE_FMA_SCALAR_REG(FNMSUB213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMSUB213) - CASE_FMA_SCALAR_MEM(FNMSUB213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - Negate = true; - break; - - CASE_FMA_PACKED_REG(FNMSUB231) - CASE_FMA_SCALAR_REG(FNMSUB231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FNMSUB231) - CASE_FMA_SCALAR_MEM(FNMSUB231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - AccStr = "-"; - Negate = true; - break; - - CASE_FMA_PACKED_REG(FMADDSUB132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADDSUB132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "+/-"; - break; - - CASE_FMA_PACKED_REG(FMADDSUB213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADDSUB213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "+/-"; - break; - - CASE_FMA_PACKED_REG(FMADDSUB231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMADDSUB231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - AccStr = "+/-"; - break; - - CASE_FMA_PACKED_REG(FMSUBADD132) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUBADD132) - AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul1Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-/+"; - break; - - CASE_FMA_PACKED_REG(FMSUBADD213) - AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUBADD213) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - Mul2Name = getRegName(MI->getOperand(1).getReg()); - AccStr = "-/+"; - break; - - CASE_FMA_PACKED_REG(FMSUBADD231) - Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - CASE_FMA_PACKED_MEM(FMSUBADD231) - Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - AccName = getRegName(MI->getOperand(1).getReg()); - AccStr = "-/+"; - break; - } - - const char *DestName = getRegName(MI->getOperand(0).getReg()); - - if (!Mul1Name) Mul1Name = "mem"; - if (!Mul2Name) Mul2Name = "mem"; - if (!AccName) AccName = "mem"; - - OS << DestName << " = "; - // TODO: Print masking information? - - if (Negate) - OS << '-'; - - OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' ' - << AccName; - - return true; -} - - -//===----------------------------------------------------------------------===// -// Top Level Entrypoint -//===----------------------------------------------------------------------===// - -/// EmitAnyX86InstComments - This function decodes x86 instructions and prints -/// newline terminated strings to the specified string if desired. This -/// information is shown in disassembly dumps when verbose assembly is enabled. -bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, - const MCInstrInfo &MCII) { - // If this is a shuffle operation, the switch should fill in this state. - SmallVector ShuffleMask; - const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr; - unsigned NumOperands = MI->getNumOperands(); - bool RegForm = false; - - if (printFMA3Comments(MI, OS)) - return true; - - switch (MI->getOpcode()) { - default: - // Not an instruction for which we can decode comments. - return false; - - case X86::BLENDPDrri: - case X86::VBLENDPDrri: - case X86::VBLENDPDYrri: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - case X86::BLENDPDrmi: - case X86::VBLENDPDrmi: - case X86::VBLENDPDYrmi: - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::BLENDPSrri: - case X86::VBLENDPSrri: - case X86::VBLENDPSYrri: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - case X86::BLENDPSrmi: - case X86::VBLENDPSrmi: - case X86::VBLENDPSYrmi: - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::PBLENDWrri: - case X86::VPBLENDWrri: - case X86::VPBLENDWYrri: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - case X86::PBLENDWrmi: - case X86::VPBLENDWrmi: - case X86::VPBLENDWYrmi: - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::VPBLENDDrri: - case X86::VPBLENDDYrri: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - case X86::VPBLENDDrmi: - case X86::VPBLENDDYrmi: - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::INSERTPSrr: - case X86::VINSERTPSrr: - case X86::VINSERTPSZrr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - case X86::INSERTPSrm: - case X86::VINSERTPSrm: - case X86::VINSERTPSZrm: - DestName = getRegName(MI->getOperand(0).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - case X86::MOVLHPSrr: - case X86::VMOVLHPSrr: - case X86::VMOVLHPSZrr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeMOVLHPSMask(2, ShuffleMask); - break; - - case X86::MOVHLPSrr: - case X86::VMOVHLPSrr: - case X86::VMOVHLPSZrr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeMOVHLPSMask(2, ShuffleMask); - break; - - case X86::MOVHPDrm: - case X86::VMOVHPDrm: - case X86::VMOVHPDZ128rm: - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeInsertElementMask(2, 1, 1, ShuffleMask); - break; - - case X86::MOVHPSrm: - case X86::VMOVHPSrm: - case X86::VMOVHPSZ128rm: - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeInsertElementMask(4, 2, 2, ShuffleMask); - break; - - case X86::MOVLPDrm: - case X86::VMOVLPDrm: - case X86::VMOVLPDZ128rm: - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeInsertElementMask(2, 0, 1, ShuffleMask); - break; - - case X86::MOVLPSrm: - case X86::VMOVLPSrm: - case X86::VMOVLPSZ128rm: - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeInsertElementMask(4, 0, 2, ShuffleMask); - break; - - CASE_MOVDUP(MOVSLDUP, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - - CASE_MOVDUP(MOVSLDUP, m) - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask); - break; - - CASE_MOVDUP(MOVSHDUP, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - - CASE_MOVDUP(MOVSHDUP, m) - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask); - break; - - CASE_MOVDUP(MOVDDUP, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - - CASE_MOVDUP(MOVDDUP, m) - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask); - break; - - case X86::PSLLDQri: - case X86::VPSLLDQri: - case X86::VPSLLDQYri: - case X86::VPSLLDQZ128rr: - case X86::VPSLLDQZ256rr: - case X86::VPSLLDQZrr: - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - case X86::VPSLLDQZ128rm: - case X86::VPSLLDQZ256rm: - case X86::VPSLLDQZrm: - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - case X86::PSRLDQri: - case X86::VPSRLDQri: - case X86::VPSRLDQYri: - case X86::VPSRLDQZ128rr: - case X86::VPSRLDQZ256rr: - case X86::VPSRLDQZrr: - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - case X86::VPSRLDQZ128rm: - case X86::VPSRLDQZ256rm: - case X86::VPSRLDQZrm: - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_SHUF(PALIGNR, rri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_SHUF(PALIGNR, rmi) - Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri) - CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri) - CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi) - CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi) - CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi) - Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_AVX512_INS_COMMON(ALIGND, Z, rri) - CASE_AVX512_INS_COMMON(ALIGND, Z256, rri) - CASE_AVX512_INS_COMMON(ALIGND, Z128, rri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_AVX512_INS_COMMON(ALIGND, Z, rmi) - CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi) - CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi) - Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_SHUF(PSHUFD, ri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_SHUF(PSHUFD, mi) - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_SHUF(PSHUFHW, ri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_SHUF(PSHUFHW, mi) - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - CASE_SHUF(PSHUFLW, ri) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_SHUF(PSHUFLW, mi) - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - case X86::MMX_PSHUFWri: - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - - case X86::MMX_PSHUFWmi: - DestName = getRegName(MI->getOperand(0).getReg()); - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - break; - - case X86::PSWAPDrr: - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - - case X86::PSWAPDrm: - DestName = getRegName(MI->getOperand(0).getReg()); - DecodePSWAPMask(2, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKHBW, r) - case X86::MMX_PUNPCKHBWirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKHBW, m) - case X86::MMX_PUNPCKHBWirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKHWD, r) - case X86::MMX_PUNPCKHWDirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKHWD, m) - case X86::MMX_PUNPCKHWDirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKHDQ, r) - case X86::MMX_PUNPCKHDQirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKHDQ, m) - case X86::MMX_PUNPCKHDQirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKHQDQ, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKHQDQ, m) - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKLBW, r) - case X86::MMX_PUNPCKLBWirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKLBW, m) - case X86::MMX_PUNPCKLBWirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKLWD, r) - case X86::MMX_PUNPCKLWDirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKLWD, m) - case X86::MMX_PUNPCKLWDirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKLDQ, r) - case X86::MMX_PUNPCKLDQirr: - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKLDQ, m) - case X86::MMX_PUNPCKLDQirm: - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); - break; - - CASE_UNPCK(PUNPCKLQDQ, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(PUNPCKLQDQ, m) - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); - break; - - CASE_SHUF(SHUFPD, rri) - Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_SHUF(SHUFPD, rmi) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64, - MI->getOperand(NumOperands - 1).getImm(), ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_SHUF(SHUFPS, rri) - Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_SHUF(SHUFPS, rmi) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VSHUF(64X2, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_VSHUF(64X2, m) - decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VSHUF(32X4, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_VSHUF(32X4, m) - decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_UNPCK(UNPCKLPD, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(UNPCKLPD, m) - DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_UNPCK(UNPCKLPS, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(UNPCKLPS, m) - DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_UNPCK(UNPCKHPD, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(UNPCKHPD, m) - DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_UNPCK(UNPCKHPS, r) - Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - RegForm = true; - LLVM_FALLTHROUGH; - - CASE_UNPCK(UNPCKHPS, m) - DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask); - Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VPERMILPI(PERMILPS, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_VPERMILPI(PERMILPS, m) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VPERMILPI(PERMILPD, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_VPERMILPI(PERMILPD, m) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64, - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::VPERM2F128rr: - case X86::VPERM2I128rr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - LLVM_FALLTHROUGH; - - case X86::VPERM2F128rm: - case X86::VPERM2I128rm: - // For instruction comments purpose, assume the 256-bit vector is v4i64. - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - Src1Name = getRegName(MI->getOperand(1).getReg()); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VPERM(PERMPD, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_VPERM(PERMPD, m) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_VPERM(PERMQ, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - LLVM_FALLTHROUGH; - - CASE_VPERM(PERMQ, m) - if (MI->getOperand(NumOperands - 1).isImm()) - DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0), - MI->getOperand(NumOperands - 1).getImm(), - ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::MOVSDrr: - case X86::VMOVSDrr: - case X86::VMOVSDZrr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - - case X86::MOVSDrm: - case X86::VMOVSDrm: - case X86::VMOVSDZrm: - DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::MOVSSrr: - case X86::VMOVSSrr: - case X86::VMOVSSZrr: - Src2Name = getRegName(MI->getOperand(2).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - - case X86::MOVSSrm: - case X86::VMOVSSrm: - case X86::VMOVSSZrm: - DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::MOVPQI2QIrr: - case X86::MOVZPQILo2PQIrr: - case X86::VMOVPQI2QIrr: - case X86::VMOVPQI2QIZrr: - case X86::VMOVZPQILo2PQIrr: - case X86::VMOVZPQILo2PQIZrr: - Src1Name = getRegName(MI->getOperand(1).getReg()); - LLVM_FALLTHROUGH; - - case X86::MOVQI2PQIrm: - case X86::VMOVQI2PQIrm: - case X86::VMOVQI2PQIZrm: - DecodeZeroMoveLowMask(2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::MOVDI2PDIrm: - case X86::VMOVDI2PDIrm: - case X86::VMOVDI2PDIZrm: - DecodeZeroMoveLowMask(4, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - case X86::EXTRQI: - if (MI->getOperand(2).isImm() && - MI->getOperand(3).isImm()) - DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(), - MI->getOperand(3).getImm(), ShuffleMask); - - DestName = getRegName(MI->getOperand(0).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - break; - - case X86::INSERTQI: - if (MI->getOperand(3).isImm() && - MI->getOperand(4).isImm()) - DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(), - MI->getOperand(4).getImm(), ShuffleMask); - - DestName = getRegName(MI->getOperand(0).getReg()); - Src1Name = getRegName(MI->getOperand(1).getReg()); - Src2Name = getRegName(MI->getOperand(2).getReg()); - break; - - case X86::VBROADCASTF128: - case X86::VBROADCASTI128: - CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm) - CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm) - DecodeSubVectorBroadcast(4, 2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm) - CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm) - DecodeSubVectorBroadcast(8, 2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm) - CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm) - DecodeSubVectorBroadcast(8, 4, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm) - CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm) - DecodeSubVectorBroadcast(8, 4, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm) - CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm) - DecodeSubVectorBroadcast(16, 4, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm) - CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm) - DecodeSubVectorBroadcast(16, 8, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m) - DecodeSubVectorBroadcast(4, 2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r) - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m) - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m) - DecodeSubVectorBroadcast(8, 2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r) - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m) - CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m) - DecodeSubVectorBroadcast(16, 2, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXBW, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXBW, m) - DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXBD, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXBD, m) - DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXBQ, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXBQ, m) - DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXWD, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXWD, m) - DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXWQ, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXWQ, m) - DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - - CASE_PMOVZX(PMOVZXDQ, r) - Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - LLVM_FALLTHROUGH; - CASE_PMOVZX(PMOVZXDQ, m) - DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - } - - // The only comments we decode are shuffles, so give up if we were unable to - // decode a shuffle mask. - if (ShuffleMask.empty()) - return false; - - if (!DestName) DestName = Src1Name; - if (DestName) { - OS << DestName; - printMasking(OS, MI, MCII); - } else - OS << "mem"; - - OS << " = "; - - // If the two sources are the same, canonicalize the input elements to be - // from the first src so that we get larger element spans. - if (Src1Name == Src2Name) { - for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { - if ((int)ShuffleMask[i] >= 0 && // Not sentinel. - ShuffleMask[i] >= (int)e) // From second mask. - ShuffleMask[i] -= e; - } - } - - // The shuffle mask specifies which elements of the src1/src2 fill in the - // destination, with a few sentinel values. Loop through and print them - // out. - for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { - if (i != 0) - OS << ','; - if (ShuffleMask[i] == SM_SentinelZero) { - OS << "zero"; - continue; - } - - // Otherwise, it must come from src1 or src2. Print the span of elements - // that comes from this src. - bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size(); - const char *SrcName = isSrc1 ? Src1Name : Src2Name; - OS << (SrcName ? SrcName : "mem") << '['; - bool IsFirst = true; - while (i != e && (int)ShuffleMask[i] != SM_SentinelZero && - (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) { - if (!IsFirst) - OS << ','; - else - IsFirst = false; - if (ShuffleMask[i] == SM_SentinelUndef) - OS << "u"; - else - OS << ShuffleMask[i] % ShuffleMask.size(); - ++i; - } - OS << ']'; - --i; // For loop increments element #. - } - OS << '\n'; - - // We successfully added a comment to this instruction. - return true; -} Index: lib/Target/X86/InstPrinter/X86InstPrinterCommon.h =================================================================== --- lib/Target/X86/InstPrinter/X86InstPrinterCommon.h +++ lib/Target/X86/InstPrinter/X86InstPrinterCommon.h @@ -1,40 +0,0 @@ -//===-- X86InstPrinterCommon.cpp - X86 assembly instruction printing ------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file includes code common for rendering MCInst instances as AT&T-style -// and Intel-style assembly. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H -#define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H - -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class X86InstPrinterCommon : public MCInstPrinter { -public: - using MCInstPrinter::MCInstPrinter; - - virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) = 0; - void printCondCode(const MCInst *MI, unsigned Op, raw_ostream &OS); - void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS); - void printVPCOMMnemonic(const MCInst *MI, raw_ostream &OS); - void printVPCMPMnemonic(const MCInst *MI, raw_ostream &OS); - void printCMPMnemonic(const MCInst *MI, bool IsVCmp, raw_ostream &OS); - void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O); - void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); -protected: - void printInstFlags(const MCInst *MI, raw_ostream &O); - void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O); -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H Index: lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp =================================================================== --- lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp +++ lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp @@ -1,337 +0,0 @@ -//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file includes common code for rendering MCInst instances as Intel-style -// and Intel-style assembly. -// -//===----------------------------------------------------------------------===// - -#include "X86InstPrinterCommon.h" -#include "MCTargetDesc/X86BaseInfo.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Support/Casting.h" -#include -#include - -using namespace llvm; - -void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid condcode argument!"); - case 0: O << "o"; break; - case 1: O << "no"; break; - case 2: O << "b"; break; - case 3: O << "ae"; break; - case 4: O << "e"; break; - case 5: O << "ne"; break; - case 6: O << "be"; break; - case 7: O << "a"; break; - case 8: O << "s"; break; - case 9: O << "ns"; break; - case 0xa: O << "p"; break; - case 0xb: O << "np"; break; - case 0xc: O << "l"; break; - case 0xd: O << "ge"; break; - case 0xe: O << "le"; break; - case 0xf: O << "g"; break; - } -} - -void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid ssecc/avxcc argument!"); - case 0: O << "eq"; break; - case 1: O << "lt"; break; - case 2: O << "le"; break; - case 3: O << "unord"; break; - case 4: O << "neq"; break; - case 5: O << "nlt"; break; - case 6: O << "nle"; break; - case 7: O << "ord"; break; - case 8: O << "eq_uq"; break; - case 9: O << "nge"; break; - case 0xa: O << "ngt"; break; - case 0xb: O << "false"; break; - case 0xc: O << "neq_oq"; break; - case 0xd: O << "ge"; break; - case 0xe: O << "gt"; break; - case 0xf: O << "true"; break; - case 0x10: O << "eq_os"; break; - case 0x11: O << "lt_oq"; break; - case 0x12: O << "le_oq"; break; - case 0x13: O << "unord_s"; break; - case 0x14: O << "neq_us"; break; - case 0x15: O << "nlt_uq"; break; - case 0x16: O << "nle_uq"; break; - case 0x17: O << "ord_s"; break; - case 0x18: O << "eq_us"; break; - case 0x19: O << "nge_uq"; break; - case 0x1a: O << "ngt_uq"; break; - case 0x1b: O << "false_os"; break; - case 0x1c: O << "neq_os"; break; - case 0x1d: O << "ge_oq"; break; - case 0x1e: O << "gt_oq"; break; - case 0x1f: O << "true_us"; break; - } -} - -void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI, - raw_ostream &OS) { - OS << "vpcom"; - - int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid vpcom argument!"); - case 0: OS << "lt"; break; - case 1: OS << "le"; break; - case 2: OS << "gt"; break; - case 3: OS << "ge"; break; - case 4: OS << "eq"; break; - case 5: OS << "neq"; break; - case 6: OS << "false"; break; - case 7: OS << "true"; break; - } - - switch (MI->getOpcode()) { - default: llvm_unreachable("Unexpected opcode!"); - case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; - case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; - case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; - case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; - case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; - case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; - case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; - case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; - } -} - -void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI, - raw_ostream &OS) { - OS << "vpcmp"; - - printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); - - switch (MI->getOpcode()) { - default: llvm_unreachable("Unexpected opcode!"); - case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: - case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: - case X86::VPCMPBZrmi: case X86::VPCMPBZrri: - case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: - case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: - case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: - OS << "b\t"; - break; - case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: - case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: - case X86::VPCMPDZrmi: case X86::VPCMPDZrri: - case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: - case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: - case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: - case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: - case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: - case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: - OS << "d\t"; - break; - case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: - case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: - case X86::VPCMPQZrmi: case X86::VPCMPQZrri: - case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: - case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: - case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: - case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: - case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: - case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: - OS << "q\t"; - break; - case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: - case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: - case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: - case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: - case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: - case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: - OS << "ub\t"; - break; - case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: - case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: - case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: - case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: - case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: - case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: - case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: - case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: - case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: - OS << "ud\t"; - break; - case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: - case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: - case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: - case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: - case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: - case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: - case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: - case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: - case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: - OS << "uq\t"; - break; - case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: - case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi: - case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: - case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: - case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik: - case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: - OS << "uw\t"; - break; - case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: - case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: - case X86::VPCMPWZrmi: case X86::VPCMPWZrri: - case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: - case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: - case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: - OS << "w\t"; - break; - } -} - -void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp, - raw_ostream &OS) { - OS << (IsVCmp ? "vcmp" : "cmp"); - - printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); - - switch (MI->getOpcode()) { - default: llvm_unreachable("Unexpected opcode!"); - case X86::CMPPDrmi: case X86::CMPPDrri: - case X86::VCMPPDrmi: case X86::VCMPPDrri: - case X86::VCMPPDYrmi: case X86::VCMPPDYrri: - case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: - case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: - case X86::VCMPPDZrmi: case X86::VCMPPDZrri: - case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: - case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: - case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: - case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: - case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: - case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: - case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: - OS << "pd\t"; - break; - case X86::CMPPSrmi: case X86::CMPPSrri: - case X86::VCMPPSrmi: case X86::VCMPPSrri: - case X86::VCMPPSYrmi: case X86::VCMPPSYrri: - case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: - case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: - case X86::VCMPPSZrmi: case X86::VCMPPSZrri: - case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: - case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: - case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: - case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: - case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: - case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: - case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: - OS << "ps\t"; - break; - case X86::CMPSDrm: case X86::CMPSDrr: - case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: - case X86::VCMPSDrm: case X86::VCMPSDrr: - case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: - case X86::VCMPSDZrm: case X86::VCMPSDZrr: - case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: - case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: - case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: - OS << "sd\t"; - break; - case X86::CMPSSrm: case X86::CMPSSrr: - case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: - case X86::VCMPSSrm: case X86::VCMPSSrr: - case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: - case X86::VCMPSSZrm: case X86::VCMPSSZrr: - case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: - case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: - case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: - OS << "ss\t"; - break; - } -} - -void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: - llvm_unreachable("Invalid rounding control!"); - case X86::TO_NEAREST_INT: - O << "{rn-sae}"; - break; - case X86::TO_NEG_INF: - O << "{rd-sae}"; - break; - case X86::TO_POS_INF: - O << "{ru-sae}"; - break; - case X86::TO_ZERO: - O << "{rz-sae}"; - break; - } -} - -/// printPCRelImm - This is used to print an immediate value that ends up -/// being encoded as a pc-relative value (e.g. for jumps and calls). In -/// Intel-style these print slightly differently than normal immediates. -/// for example, a $ is not emitted. -void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) - O << formatImm(Op.getImm()); - else { - assert(Op.isExpr() && "unknown pcrel immediate operand"); - // If a symbolic branch target was added as a constant expression then print - // that address in hex. - const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr()); - int64_t Address; - if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { - O << formatHex((uint64_t)Address); - } else { - // Otherwise, just print the expression. - Op.getExpr()->print(O, &MAI); - } - } -} - -void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - if (MI->getOperand(OpNo).getReg()) { - printOperand(MI, OpNo, O); - O << ':'; - } -} - -void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - uint64_t TSFlags = Desc.TSFlags; - unsigned Flags = MI->getFlags(); - - if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) - O << "\tlock\t"; - - if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) - O << "\tnotrack\t"; - - if (Flags & X86::IP_HAS_REPEAT_NE) - O << "\trepne\t"; - else if (Flags & X86::IP_HAS_REPEAT) - O << "\trep\t"; -} Index: lib/Target/X86/InstPrinter/X86IntelInstPrinter.h =================================================================== --- lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +++ lib/Target/X86/InstPrinter/X86IntelInstPrinter.h @@ -1,144 +0,0 @@ -//= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an X86 MCInst to Intel style .s file syntax. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H -#define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H - -#include "X86InstPrinterCommon.h" -#include "llvm/Support/raw_ostream.h" - -namespace llvm { - -class X86IntelInstPrinter final : public X86InstPrinterCommon { -public: - X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : X86InstPrinterCommon(MAI, MII, MRI) {} - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, - const MCSubtargetInfo &STI) override; - bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); - - // Autogenerated by tblgen, returns true if we successfully printed an - // alias. - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override; - void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); - void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O); - void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - - void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - - void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - printMemReference(MI, OpNo, O); - } - - void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "byte ptr "; - printMemReference(MI, OpNo, O); - } - void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "word ptr "; - printMemReference(MI, OpNo, O); - } - void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "dword ptr "; - printMemReference(MI, OpNo, O); - } - void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "qword ptr "; - printMemReference(MI, OpNo, O); - } - void printxmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "xmmword ptr "; - printMemReference(MI, OpNo, O); - } - void printymmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "ymmword ptr "; - printMemReference(MI, OpNo, O); - } - void printzmmwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "zmmword ptr "; - printMemReference(MI, OpNo, O); - } - void printtbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "tbyte ptr "; - printMemReference(MI, OpNo, O); - } - - - void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "byte ptr "; - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "word ptr "; - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "dword ptr "; - printSrcIdx(MI, OpNo, O); - } - void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "qword ptr "; - printSrcIdx(MI, OpNo, O); - } - void printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "byte ptr "; - printDstIdx(MI, OpNo, O); - } - void printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "word ptr "; - printDstIdx(MI, OpNo, O); - } - void printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "dword ptr "; - printDstIdx(MI, OpNo, O); - } - void printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "qword ptr "; - printDstIdx(MI, OpNo, O); - } - void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "byte ptr "; - printMemOffset(MI, OpNo, O); - } - void printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "word ptr "; - printMemOffset(MI, OpNo, O); - } - void printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "dword ptr "; - printMemOffset(MI, OpNo, O); - } - void printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << "qword ptr "; - printMemOffset(MI, OpNo, O); - } -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H Index: lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp =================================================================== --- lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +++ lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp @@ -1,445 +0,0 @@ -//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file includes code for rendering MCInst instances as Intel-style -// assembly. -// -//===----------------------------------------------------------------------===// - -#include "X86IntelInstPrinter.h" -#include "MCTargetDesc/X86BaseInfo.h" -#include "X86InstComments.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/MC/MCInstrInfo.h" -#include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "X86GenAsmWriter1.inc" - -void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << getRegisterName(RegNo); -} - -void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, - StringRef Annot, - const MCSubtargetInfo &STI) { - printInstFlags(MI, OS); - - // In 16-bit mode, print data16 as data32. - if (MI->getOpcode() == X86::DATA16_PREFIX && - STI.getFeatureBits()[X86::Mode16Bit]) { - OS << "\tdata32"; - } else if (!printAliasInstr(MI, OS) && - !printVecCompareInstr(MI, OS)) - printInstruction(MI, OS); - - // Next always print the annotation. - printAnnotation(OS, Annot); - - // If verbose assembly is enabled, we can print some informative comments. - if (CommentStream) - EmitAnyX86InstComments(MI, *CommentStream, MII); -} - -bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) { - if (MI->getNumOperands() == 0 || - !MI->getOperand(MI->getNumOperands() - 1).isImm()) - return false; - - int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); - - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - - // Custom print the vector compare instructions to get the immediate - // translated into the mnemonic. - switch (MI->getOpcode()) { - case X86::CMPPDrmi: case X86::CMPPDrri: - case X86::CMPPSrmi: case X86::CMPPSrri: - case X86::CMPSDrm: case X86::CMPSDrr: - case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: - case X86::CMPSSrm: case X86::CMPSSrr: - case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: - if (Imm >= 0 && Imm <= 7) { - OS << '\t'; - printCMPMnemonic(MI, /*IsVCMP*/false, OS); - printOperand(MI, 0, OS); - OS << ", "; - // Skip operand 1 as its tied to the dest. - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) - printdwordmem(MI, 2, OS); - else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) - printqwordmem(MI, 2, OS); - else - printxmmwordmem(MI, 2, OS); - } else - printOperand(MI, 2, OS); - - return true; - } - break; - - case X86::VCMPPDrmi: case X86::VCMPPDrri: - case X86::VCMPPDYrmi: case X86::VCMPPDYrri: - case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: - case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: - case X86::VCMPPDZrmi: case X86::VCMPPDZrri: - case X86::VCMPPSrmi: case X86::VCMPPSrri: - case X86::VCMPPSYrmi: case X86::VCMPPSYrri: - case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: - case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: - case X86::VCMPPSZrmi: case X86::VCMPPSZrri: - case X86::VCMPSDrm: case X86::VCMPSDrr: - case X86::VCMPSDZrm: case X86::VCMPSDZrr: - case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: - case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: - case X86::VCMPSSrm: case X86::VCMPSSrr: - case X86::VCMPSSZrm: case X86::VCMPSSZrr: - case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: - case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: - case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: - case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: - case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: - case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: - case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: - case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: - case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: - case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: - case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: - case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: - case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: - case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: - case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: - case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: - case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: - case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: - case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: - case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: - if (Imm >= 0 && Imm <= 31) { - OS << '\t'; - printCMPMnemonic(MI, /*IsVCMP*/true, OS); - - unsigned CurOp = 0; - printOperand(MI, CurOp++, OS); - - if (Desc.TSFlags & X86II::EVEX_K) { - // Print mask operand. - OS << " {"; - printOperand(MI, CurOp++, OS); - OS << "}"; - } - OS << ", "; - printOperand(MI, CurOp++, OS); - OS << ", "; - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if (Desc.TSFlags & X86II::EVEX_B) { - // Broadcast form. - // Load size is based on W-bit. - if (Desc.TSFlags & X86II::VEX_W) - printqwordmem(MI, CurOp++, OS); - else - printdwordmem(MI, CurOp++, OS); - - // Print the number of elements broadcasted. - unsigned NumElts; - if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; - else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; - else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; - OS << "{1to" << NumElts << "}"; - } else { - if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) - printdwordmem(MI, CurOp++, OS); - else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) - printqwordmem(MI, CurOp++, OS); - else if (Desc.TSFlags & X86II::EVEX_L2) - printzmmwordmem(MI, CurOp++, OS); - else if (Desc.TSFlags & X86II::VEX_L) - printymmwordmem(MI, CurOp++, OS); - else - printxmmwordmem(MI, CurOp++, OS); - } - } else { - printOperand(MI, CurOp++, OS); - if (Desc.TSFlags & X86II::EVEX_B) - OS << ", {sae}"; - } - - return true; - } - break; - - case X86::VPCOMBmi: case X86::VPCOMBri: - case X86::VPCOMDmi: case X86::VPCOMDri: - case X86::VPCOMQmi: case X86::VPCOMQri: - case X86::VPCOMUBmi: case X86::VPCOMUBri: - case X86::VPCOMUDmi: case X86::VPCOMUDri: - case X86::VPCOMUQmi: case X86::VPCOMUQri: - case X86::VPCOMUWmi: case X86::VPCOMUWri: - case X86::VPCOMWmi: case X86::VPCOMWri: - if (Imm >= 0 && Imm <= 7) { - OS << '\t'; - printVPCOMMnemonic(MI, OS); - printOperand(MI, 0, OS); - OS << ", "; - printOperand(MI, 1, OS); - OS << ", "; - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) - printxmmwordmem(MI, 2, OS); - else - printOperand(MI, 2, OS); - return true; - } - break; - - case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: - case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: - case X86::VPCMPBZrmi: case X86::VPCMPBZrri: - case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: - case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: - case X86::VPCMPDZrmi: case X86::VPCMPDZrri: - case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: - case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: - case X86::VPCMPQZrmi: case X86::VPCMPQZrri: - case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: - case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: - case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: - case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: - case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: - case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: - case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: - case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: - case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: - case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: - case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri: - case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: - case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: - case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: - case X86::VPCMPWZrmi: case X86::VPCMPWZrri: - case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: - case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: - case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: - case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: - case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: - case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: - case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: - case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: - case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: - case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: - case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: - case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: - case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: - case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: - case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: - case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: - case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: - case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: - case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: - case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik: - case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: - case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: - case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: - case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: - case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: - case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: - case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: - case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: - case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: - case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: - case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: - case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: - case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: - case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: - case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: - case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: - if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) { - OS << '\t'; - printVPCMPMnemonic(MI, OS); - - unsigned CurOp = 0; - printOperand(MI, CurOp++, OS); - - if (Desc.TSFlags & X86II::EVEX_K) { - // Print mask operand. - OS << " {"; - printOperand(MI, CurOp++, OS); - OS << "}"; - } - OS << ", "; - printOperand(MI, CurOp++, OS); - OS << ", "; - - if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { - if (Desc.TSFlags & X86II::EVEX_B) { - // Broadcast form. - // Load size is based on W-bit as only D and Q are supported. - if (Desc.TSFlags & X86II::VEX_W) - printqwordmem(MI, CurOp++, OS); - else - printdwordmem(MI, CurOp++, OS); - - // Print the number of elements broadcasted. - unsigned NumElts; - if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; - else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; - else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; - OS << "{1to" << NumElts << "}"; - } else { - if (Desc.TSFlags & X86II::EVEX_L2) - printzmmwordmem(MI, CurOp++, OS); - else if (Desc.TSFlags & X86II::VEX_L) - printymmwordmem(MI, CurOp++, OS); - else - printxmmwordmem(MI, CurOp++, OS); - } - } else { - printOperand(MI, CurOp++, OS); - } - - return true; - } - break; - } - - return false; -} - -void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - printRegName(O, Op.getReg()); - } else if (Op.isImm()) { - O << formatImm((int64_t)Op.getImm()); - } else { - assert(Op.isExpr() && "unknown operand kind in printOperand"); - O << "offset "; - Op.getExpr()->print(O, &MAI); - } -} - -void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, - raw_ostream &O) { - const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); - unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); - const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); - const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); - - // If this has a segment register, print it. - printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O); - - O << '['; - - bool NeedPlus = false; - if (BaseReg.getReg()) { - printOperand(MI, Op+X86::AddrBaseReg, O); - NeedPlus = true; - } - - if (IndexReg.getReg()) { - if (NeedPlus) O << " + "; - if (ScaleVal != 1) - O << ScaleVal << '*'; - printOperand(MI, Op+X86::AddrIndexReg, O); - NeedPlus = true; - } - - if (!DispSpec.isImm()) { - if (NeedPlus) O << " + "; - assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); - DispSpec.getExpr()->print(O, &MAI); - } else { - int64_t DispVal = DispSpec.getImm(); - if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { - if (NeedPlus) { - if (DispVal > 0) - O << " + "; - else { - O << " - "; - DispVal = -DispVal; - } - } - O << formatImm(DispVal); - } - } - - O << ']'; -} - -void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, - raw_ostream &O) { - // If this has a segment register, print it. - printOptionalSegReg(MI, Op + 1, O); - O << '['; - printOperand(MI, Op, O); - O << ']'; -} - -void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, - raw_ostream &O) { - // DI accesses are always ES-based. - O << "es:["; - printOperand(MI, Op, O); - O << ']'; -} - -void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, - raw_ostream &O) { - const MCOperand &DispSpec = MI->getOperand(Op); - - // If this has a segment register, print it. - printOptionalSegReg(MI, Op + 1, O); - - O << '['; - - if (DispSpec.isImm()) { - O << formatImm(DispSpec.getImm()); - } else { - assert(DispSpec.isExpr() && "non-immediate displacement?"); - DispSpec.getExpr()->print(O, &MAI); - } - - O << ']'; -} - -void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op, - raw_ostream &O) { - if (MI->getOperand(Op).isExpr()) - return MI->getOperand(Op).getExpr()->print(O, &MAI); - - O << formatImm(MI->getOperand(Op).getImm() & 0xff); -} - -void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &OS) { - const MCOperand &Op = MI->getOperand(OpNo); - unsigned Reg = Op.getReg(); - // Override the default printing to print st(0) instead st. - if (Reg == X86::ST0) - OS << "st(0)"; - else - printRegName(OS, Reg); -} Index: lib/Target/X86/LLVMBuild.txt =================================================================== --- lib/Target/X86/LLVMBuild.txt +++ lib/Target/X86/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo Utils [component_0] type = TargetGroup @@ -30,5 +30,5 @@ type = Library name = X86CodeGen parent = X86 -required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils GlobalISel ProfileData +required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86Desc X86Info X86Utils GlobalISel ProfileData add_to_library_groups = X86 Index: lib/Target/X86/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/X86/MCTargetDesc/CMakeLists.txt +++ lib/Target/X86/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,9 @@ add_llvm_library(LLVMX86Desc + X86ATTInstPrinter.cpp X86AsmBackend.cpp + X86IntelInstPrinter.cpp + X86InstComments.cpp + X86InstPrinterCommon.cpp X86MCTargetDesc.cpp X86MCAsmInfo.cpp X86MCCodeEmitter.cpp Index: lib/Target/X86/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/X86/MCTargetDesc/LLVMBuild.txt +++ lib/Target/X86/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = X86Desc parent = X86 -required_libraries = MC MCDisassembler Object Support X86AsmPrinter X86Info +required_libraries = MC MCDisassembler Object Support X86Info X86Utils add_to_library_groups = X86 Index: lib/Target/X86/MCTargetDesc/X86MCExpr.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCExpr.h +++ lib/Target/X86/MCTargetDesc/X86MCExpr.h @@ -14,7 +14,7 @@ #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCEXPR_H #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCEXPR_H -#include "InstPrinter/X86ATTInstPrinter.h" +#include "MCTargetDesc/X86ATTInstPrinter.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -11,9 +11,9 @@ //===----------------------------------------------------------------------===// #include "X86MCTargetDesc.h" -#include "InstPrinter/X86ATTInstPrinter.h" -#include "InstPrinter/X86IntelInstPrinter.h" +#include "X86ATTInstPrinter.h" #include "X86BaseInfo.h" +#include "X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/Triple.h" Index: lib/Target/X86/X86AsmPrinter.cpp =================================================================== --- lib/Target/X86/X86AsmPrinter.cpp +++ lib/Target/X86/X86AsmPrinter.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "X86AsmPrinter.h" -#include "InstPrinter/X86ATTInstPrinter.h" +#include "MCTargetDesc/X86ATTInstPrinter.h" #include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86TargetStreamer.h" #include "X86InstrInfo.h" Index: lib/Target/X86/X86EvexToVex.cpp =================================================================== --- lib/Target/X86/X86EvexToVex.cpp +++ lib/Target/X86/X86EvexToVex.cpp @@ -19,8 +19,8 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/X86InstComments.h" #include "MCTargetDesc/X86BaseInfo.h" +#include "MCTargetDesc/X86InstComments.h" #include "X86.h" #include "X86InstrInfo.h" #include "X86Subtarget.h" Index: lib/Target/X86/X86MCInstLower.cpp =================================================================== --- lib/Target/X86/X86MCInstLower.cpp +++ lib/Target/X86/X86MCInstLower.cpp @@ -11,9 +11,9 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/X86ATTInstPrinter.h" -#include "InstPrinter/X86InstComments.h" +#include "MCTargetDesc/X86ATTInstPrinter.h" #include "MCTargetDesc/X86BaseInfo.h" +#include "MCTargetDesc/X86InstComments.h" #include "MCTargetDesc/X86TargetStreamer.h" #include "Utils/X86ShuffleDecode.h" #include "X86AsmPrinter.h" Index: lib/Target/XCore/CMakeLists.txt =================================================================== --- lib/Target/XCore/CMakeLists.txt +++ lib/Target/XCore/CMakeLists.txt @@ -28,6 +28,5 @@ ) add_subdirectory(Disassembler) -add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) Index: lib/Target/XCore/InstPrinter/CMakeLists.txt =================================================================== --- lib/Target/XCore/InstPrinter/CMakeLists.txt +++ lib/Target/XCore/InstPrinter/CMakeLists.txt @@ -1,3 +0,0 @@ -add_llvm_library(LLVMXCoreAsmPrinter - XCoreInstPrinter.cpp - ) Index: lib/Target/XCore/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/XCore/InstPrinter/LLVMBuild.txt +++ lib/Target/XCore/InstPrinter/LLVMBuild.txt @@ -1,22 +0,0 @@ -;===- ./lib/Target/XCore/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; -; -; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -; See https://llvm.org/LICENSE.txt for license information. -; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -; -;===------------------------------------------------------------------------===; -; -; This is an LLVMBuild description file for the components in this subdirectory. -; -; For more information on the LLVMBuild system, please see: -; -; http://llvm.org/docs/LLVMBuild.html -; -;===------------------------------------------------------------------------===; - -[component_0] -type = Library -name = XCoreAsmPrinter -parent = XCore -required_libraries = MC Support -add_to_library_groups = XCore Index: lib/Target/XCore/InstPrinter/XCoreInstPrinter.h =================================================================== --- lib/Target/XCore/InstPrinter/XCoreInstPrinter.h +++ lib/Target/XCore/InstPrinter/XCoreInstPrinter.h @@ -1,46 +0,0 @@ -//== XCoreInstPrinter.h - Convert XCore MCInst to assembly syntax -*- C++ -*-=// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This file contains the declaration of the XCoreInstPrinter class, -/// which is used to print XCore MCInst to a .s file. -/// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_XCORE_INSTPRINTER_XCOREINSTPRINTER_H -#define LLVM_LIB_TARGET_XCORE_INSTPRINTER_XCOREINSTPRINTER_H - -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCInstPrinter.h" - -namespace llvm { - -class XCoreInstPrinter : public MCInstPrinter { -public: - XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} - - // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); - - void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, - const MCSubtargetInfo &STI) override; - -private: - void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O); - void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O); - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_XCORE_INSTPRINTER_XCOREINSTPRINTER_H Index: lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp =================================================================== --- lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp +++ lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp @@ -1,89 +0,0 @@ -//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax ----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This class prints an XCore MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#include "XCoreInstPrinter.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSymbol.h" -#include "llvm/Support/Casting.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include - -using namespace llvm; - -#define DEBUG_TYPE "asm-printer" - -#include "XCoreGenAsmWriter.inc" - -void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << StringRef(getRegisterName(RegNo)).lower(); -} - -void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot, const MCSubtargetInfo &STI) { - printInstruction(MI, O); - printAnnotation(O, Annot); -} - -void XCoreInstPrinter:: -printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) { - report_fatal_error("can't handle InlineJT"); -} - -void XCoreInstPrinter:: -printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) { - report_fatal_error("can't handle InlineJT32"); -} - -static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI, - raw_ostream &OS) { - int Offset = 0; - const MCSymbolRefExpr *SRE; - - if (const MCBinaryExpr *BE = dyn_cast(Expr)) { - SRE = dyn_cast(BE->getLHS()); - const MCConstantExpr *CE = dyn_cast(BE->getRHS()); - assert(SRE && CE && "Binary expression must be sym+const."); - Offset = CE->getValue(); - } else { - SRE = dyn_cast(Expr); - assert(SRE && "Unexpected MCExpr type."); - } - assert(SRE->getKind() == MCSymbolRefExpr::VK_None); - - SRE->getSymbol().print(OS, MAI); - - if (Offset) { - if (Offset > 0) - OS << '+'; - OS << Offset; - } -} - -void XCoreInstPrinter:: -printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isReg()) { - printRegName(O, Op.getReg()); - return; - } - - if (Op.isImm()) { - O << Op.getImm(); - return; - } - - assert(Op.isExpr() && "unknown operand kind in printOperand"); - printExpr(Op.getExpr(), &MAI, O); -} Index: lib/Target/XCore/LLVMBuild.txt =================================================================== --- lib/Target/XCore/LLVMBuild.txt +++ lib/Target/XCore/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo +subdirectories = Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -38,7 +38,6 @@ Support Target TransformUtils - XCoreAsmPrinter XCoreDesc XCoreInfo add_to_library_groups = XCore Index: lib/Target/XCore/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/XCore/MCTargetDesc/CMakeLists.txt +++ lib/Target/XCore/MCTargetDesc/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMXCoreDesc + XCoreInstPrinter.cpp XCoreMCTargetDesc.cpp XCoreMCAsmInfo.cpp ) Index: lib/Target/XCore/MCTargetDesc/LLVMBuild.txt =================================================================== --- lib/Target/XCore/MCTargetDesc/LLVMBuild.txt +++ lib/Target/XCore/MCTargetDesc/LLVMBuild.txt @@ -18,5 +18,5 @@ type = Library name = XCoreDesc parent = XCore -required_libraries = MC Support XCoreAsmPrinter XCoreInfo +required_libraries = MC Support XCoreInfo add_to_library_groups = XCore Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/XCoreMCTargetDesc.h" -#include "InstPrinter/XCoreInstPrinter.h" +#include "MCTargetDesc/XCoreInstPrinter.h" #include "MCTargetDesc/XCoreMCAsmInfo.h" #include "XCoreTargetStreamer.h" #include "llvm/ADT/StringRef.h" Index: lib/Target/XCore/XCoreAsmPrinter.cpp =================================================================== --- lib/Target/XCore/XCoreAsmPrinter.cpp +++ lib/Target/XCore/XCoreAsmPrinter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "InstPrinter/XCoreInstPrinter.h" +#include "MCTargetDesc/XCoreInstPrinter.h" #include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreMCInstLower.h"