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Differential D60580

[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only
ClosedPublic

Authored by aemerson on Apr 11 2019, 1:55 PM.

Details

Reviewers
aditya_nandakumar
paquette
qcolombet
arsenm
Petar.Avramovic
rovka
kristof.beyls
Commits
rG946b1246d6c8: [GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants…
rL358369: [GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants…
Summary

Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't be degraded.

This change also improves the IRTranslator so that in most places, but not all, it creates constants using the MIRBuilder directly instead of first creating a new destination vreg and then creating a constant. By doing this, the buildConstant() method can just return the vreg of an existing G_CONSTANT instead of having to create a COPY from it.

I measured a 0.2% improvement in compile time and a 0.9% improvement in code size at -O0.

Compile time:
Program                                        base   cse    diff
test-suite...ark/tramp3d-v4/tramp3d-v4.test     9.04   9.12  0.8%
test-suite...Mark/mafft/pairlocalalign.test     2.68   2.66 -0.7%
test-suite...-typeset/consumer-typeset.test     5.53   5.51 -0.4%
test-suite :: CTMark/lencod/lencod.test         5.30   5.28 -0.3%
test-suite :: CTMark/Bullet/bullet.test        25.82  25.76 -0.2%
test-suite...:: CTMark/ClamAV/clamscan.test     6.92   6.90 -0.2%
test-suite...TMark/7zip/7zip-benchmark.test    34.24  34.17 -0.2%
test-suite :: CTMark/SPASS/SPASS.test           6.25   6.24 -0.1%
test-suite...:: CTMark/sqlite3/sqlite3.test     1.66   1.66 -0.1%
test-suite :: CTMark/kimwitu++/kc.test         13.61  13.60 -0.0%
Geomean difference                                          -0.2%

Code size:
Program                                        base     cse      diff
test-suite...-typeset/consumer-typeset.test    1315632  1266480 -3.7%
test-suite...:: CTMark/ClamAV/clamscan.test    1313892  1297508 -1.2%
test-suite :: CTMark/lencod/lencod.test        1439504  1423112 -1.1%
test-suite...TMark/7zip/7zip-benchmark.test    2936980  2904172 -1.1%
test-suite :: CTMark/Bullet/bullet.test        3478276  3445460 -0.9%
test-suite...ark/tramp3d-v4/tramp3d-v4.test    8082868  8033492 -0.6%
test-suite :: CTMark/kimwitu++/kc.test         3870380  3853972 -0.4%
test-suite :: CTMark/SPASS/SPASS.test          1434904  1434896 -0.0%
test-suite...Mark/mafft/pairlocalalign.test    764528   764528   0.0%
test-suite...:: CTMark/sqlite3/sqlite3.test    782092   782092   0.0%
Geomean difference                                              -0.9%

Diff Detail

Repository
rL LLVM

Event Timeline

aemerson created this revision.Apr 11 2019, 1:55 PM
Herald added subscribers: volkan, atanasyan, jrtc27 and 7 others. · View Herald TranscriptApr 11 2019, 1:55 PM
aditya_nandakumar added a comment.Apr 11 2019, 2:08 PM

Looks mostly good - there are some minor comments from my side.

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
218 ↗(On Diff #194748)

Nit : {} not necessary

llvm/lib/CodeGen/TargetPassConfig.cpp
1228 ↗(On Diff #194748)

Maybe we should add a hook so targets can return the appropriate CSEConfigs for the opt level instead of the core passes making this decision for them?

llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
18 ↗(On Diff #194748)

Did you look why these copies are generated?

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
307 ↗(On Diff #194748)

Similar here.

aemerson marked 3 inline comments as done.Apr 11 2019, 3:04 PM
aemerson added inline comments.
llvm/lib/CodeGen/TargetPassConfig.cpp
1228 ↗(On Diff #194748)

Given that we're only doing constants here, I'd like all targets to be consistent as much as possible.

llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
18 ↗(On Diff #194748)

This was a custom legalization, I'll fix it.

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
307 ↗(On Diff #194748)

Another custom legalization.

aemerson updated this revision to Diff 194774.Apr 11 2019, 3:09 PM

Fixed the places where custom legalization was not using full CSE.

aditya_nandakumar added inline comments.Apr 11 2019, 3:12 PM
llvm/lib/CodeGen/TargetPassConfig.cpp
1228 ↗(On Diff #194748)

The reason I mentioned adding a hook is that there's no easy way for a target to override the opcodes that are CSEd for any opt level (the pass chooses it for them) and the only option would be to modify it out of tree. Instead I was wondering something like

std::unique_ptr<CSEConfig> TargetPassConfig::getCSEConfigForOptLevel() {
 return O0? make_unique<ConstantOnlyConfig>() : make_unique<CSEConfig>();
}

This would mean you wouldn't need to update both passes to check for opt level, and additionally this allows targets to override this with their own CSEConfig..

aemerson marked an inline comment as done.Apr 11 2019, 3:16 PM
aemerson added inline comments.
llvm/lib/CodeGen/TargetPassConfig.cpp
1228 ↗(On Diff #194748)

Ah, fair enough, I'll do that.

aemerson updated this revision to Diff 194980.Apr 12 2019, 4:26 PM

New patch uses a new CSEConfigBase class as the interface between TargetPassConfig and GlobalISel targets, since CodeGen can't depend on the GlobalISel lib.

Unfortunately it does mean that targets need to opt-in to CSE.

aditya_nandakumar added a comment.Apr 12 2019, 4:33 PM

Looks reasonable. Could you please split out the CSEConfigBase into it's own commit?
Also I only see the includes for the CSEConfigBase.h but not the header file in this patch. Maybe you forgot to include it?

aemerson updated this revision to Diff 194981.Apr 12 2019, 4:40 PM

Yep, forgot to git add it. It's in this new diff, but I'll add it as a separate commit. Ok to proceed?

aditya_nandakumar accepted this revision.Apr 12 2019, 5:14 PM

LGTM. Thanks - please address the minor nit and proceed with two commits.

llvm/include/llvm/CodeGen/CSEConfigBase.h
14 ↗(On Diff #194981)

Could you please add a comment on why this class is defined here? Otherwise LGTM.

This revision is now accepted and ready to land.Apr 12 2019, 5:14 PM
aemerson mentioned this in rL358368: [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their….Apr 14 2019, 9:53 PM
aemerson mentioned this in rGd189680baa07: [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their….
Closed by commit rL358369: [GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants… (authored by aemerson). · Explain WhyApr 14 2019, 10:08 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
GlobalISel/
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Target/
AArch64/
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AMDGPU/
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test/
CodeGen/
AArch64/
GlobalISel/
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AMDGPU/
GlobalISel/
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ARM/
GlobalISel/
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Mips/
GlobalISel/
legalizer/
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llvm-ir/
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X86/
GlobalISel/
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Diff 195093

llvm/trunk/lib/CodeGen/GlobalISel/CSEInfo.cpp

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) { bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) {
return Opc == TargetOpcode::G_CONSTANT; return Opc == TargetOpcode::G_CONSTANT;
} }
std::unique_ptr<CSEConfigBase> std::unique_ptr<CSEConfigBase>
llvm::getStandardCSEConfigForOpt(CodeGenOpt::Level Level) { llvm::getStandardCSEConfigForOpt(CodeGenOpt::Level Level) {
std::unique_ptr<CSEConfigBase> Config; std::unique_ptr<CSEConfigBase> Config;
if (Level == CodeGenOpt::None) if (Level == CodeGenOpt::None)
Config = make_unique<CSEConfigBase>(); Config = make_unique<CSEConfigConstantOnly>();
else else
Config = make_unique<CSEConfigFull>(); Config = make_unique<CSEConfigFull>();
return Config; return Config;
} }
/// ----------------------------------------- /// -----------------------------------------
/// -------- GISelCSEInfo -------------// /// -------- GISelCSEInfo -------------//
▲ Show 20 Lines • Show All 305 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 639 Lines • ▼ Show 20 Lines if (StructType *StTy = GTI.getStructTypeOrNull()) {
// handle it quickly. // handle it quickly.
if (const auto *CI = dyn_cast<ConstantInt>(Idx)) { if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
Offset += ElementSize * CI->getSExtValue(); Offset += ElementSize * CI->getSExtValue();
continue; continue;
} }
if (Offset != 0) { if (Offset != 0) {
unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy); unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
unsigned OffsetReg = LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset)); auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg); MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));
BaseReg = NewBaseReg; BaseReg = NewBaseReg;
Offset = 0; Offset = 0;
} }
unsigned IdxReg = getOrCreateVReg(*Idx); unsigned IdxReg = getOrCreateVReg(*Idx);
if (MRI->getType(IdxReg) != OffsetTy) { if (MRI->getType(IdxReg) != OffsetTy) {
unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy); unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg); MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
IdxReg = NewIdxReg; IdxReg = NewIdxReg;
} }
// N = N + Idx * ElementSize; // N = N + Idx * ElementSize;
// Avoid doing it for ElementSize of 1. // Avoid doing it for ElementSize of 1.
unsigned GepOffsetReg; unsigned GepOffsetReg;
if (ElementSize != 1) { if (ElementSize != 1) {
unsigned ElementSizeReg =
getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy); GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg); auto ElementSizeMIB = MIRBuilder.buildConstant(
getLLTForType(*OffsetIRTy, *DL), ElementSize);
MIRBuilder.buildMul(GepOffsetReg, ElementSizeMIB.getReg(0), IdxReg);
} else } else
GepOffsetReg = IdxReg; GepOffsetReg = IdxReg;
unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy); unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg); MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
BaseReg = NewBaseReg; BaseReg = NewBaseReg;
} }
} }
if (Offset != 0) { if (Offset != 0) {
unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset)); auto OffsetMIB =
MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg); MIRBuilder.buildConstant(getLLTForType(*OffsetIRTy, *DL), Offset);
MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
return true; return true;
} }
MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
return true; return true;
} }
bool IRTranslator::translateMemfunc(const CallInst &CI, bool IRTranslator::translateMemfunc(const CallInst &CI,
▲ Show 20 Lines • Show All 1,210 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp

Show All 21 Lines
#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h" #include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Target/TargetMachine.h"
#include <iterator> #include <iterator>
#define DEBUG_TYPE "legalizer" #define DEBUG_TYPE "legalizer"
using namespace llvm; using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 LinesMachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
assert(ValueTy.isScalar() && "invalid offset type"); assert(ValueTy.isScalar() && "invalid offset type");
if (Value == 0) { if (Value == 0) {
Res = Op0; Res = Op0;
return None; return None;
} }
Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0)); Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy); auto Cst = buildConstant(ValueTy, Value);
return buildGEP(Res, Op0, Cst.getReg(0));
buildConstant(TmpReg, Value);
return buildGEP(Res, Op0, TmpReg);
} }
MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0, MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
uint32_t NumBits) { uint32_t NumBits) {
assert(getMRI()->getType(Res).isPointer() && assert(getMRI()->getType(Res).isPointer() &&
getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch"); getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
return buildInstr(TargetOpcode::G_PTR_MASK) return buildInstr(TargetOpcode::G_PTR_MASK)
▲ Show 20 Lines • Show All 855 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/TargetPassConfig.cpp

Show First 20 Lines • Show All 1,220 Lines • ▼ Show 20 Linesbool TargetPassConfig::isGlobalISelAbortEnabled() const {
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable; return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
} }
bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const { bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
} }
bool TargetPassConfig::isGISelCSEEnabled() const { bool TargetPassConfig::isGISelCSEEnabled() const {
return getOptLevel() != CodeGenOpt::Level::None; return true;
} }
std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const { std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
return make_unique<CSEConfigBase>(); return make_unique<CSEConfigBase>();
} }

llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 642 Lines • ▼ Show 20 Lines if (Align > PtrSize) {
DstPtr = List; DstPtr = List;
uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8; uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8;
MIRBuilder.buildLoad( MIRBuilder.buildLoad(
Dst, DstPtr, Dst, DstPtr,
*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad, *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
ValSize, std::max(Align, PtrSize))); ValSize, std::max(Align, PtrSize)));
unsigned SizeReg = MRI.createGenericVirtualRegister(IntPtrTy); auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrSize));
MIRBuilder.buildConstant(SizeReg, alignTo(ValSize, PtrSize));
unsigned NewList = MRI.createGenericVirtualRegister(PtrTy); unsigned NewList = MRI.createGenericVirtualRegister(PtrTy);
MIRBuilder.buildGEP(NewList, DstPtr, SizeReg); MIRBuilder.buildGEP(NewList, DstPtr, Size.getReg(0));
MIRBuilder.buildStore( MIRBuilder.buildStore(
NewList, ListPtr, NewList, ListPtr,
*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore, *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore,
PtrSize, /* Align = */ PtrSize)); PtrSize, /* Align = */ PtrSize));
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 692 Lines • ▼ Show 20 Lines if (ST.hasApertureRegs()) {
unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ? unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE : AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE; AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
unsigned Encoding = unsigned Encoding =
AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ | AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ | Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_; WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
unsigned ShiftAmt = MRI.createGenericVirtualRegister(S32);
unsigned ApertureReg = MRI.createGenericVirtualRegister(S32); unsigned ApertureReg = MRI.createGenericVirtualRegister(S32);
unsigned GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); unsigned GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
MIRBuilder.buildInstr(AMDGPU::S_GETREG_B32) MIRBuilder.buildInstr(AMDGPU::S_GETREG_B32)
.addDef(GetReg) .addDef(GetReg)
.addImm(Encoding); .addImm(Encoding);
MRI.setType(GetReg, S32); MRI.setType(GetReg, S32);
MIRBuilder.buildConstant(ShiftAmt, WidthM1 + 1); auto ShiftAmt = MIRBuilder.buildConstant(S32, WidthM1 + 1);
MIRBuilder.buildInstr(TargetOpcode::G_SHL) MIRBuilder.buildInstr(TargetOpcode::G_SHL)
.addDef(ApertureReg) .addDef(ApertureReg)
.addUse(GetReg) .addUse(GetReg)
.addUse(ShiftAmt); .addUse(ShiftAmt.getReg(0));
return ApertureReg; return ApertureReg;
} }
unsigned QueuePtr = MRI.createGenericVirtualRegister( unsigned QueuePtr = MRI.createGenericVirtualRegister(
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
// FIXME: Placeholder until we can track the input registers. // FIXME: Placeholder until we can track the input registers.
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines if (ST.getTargetLowering()->isNoopAddrSpaceCast(SrcAS, DestAS)) {
return true; return true;
} }
if (SrcAS == AMDGPUAS::FLAT_ADDRESS) { if (SrcAS == AMDGPUAS::FLAT_ADDRESS) {
assert(DestAS == AMDGPUAS::LOCAL_ADDRESS || assert(DestAS == AMDGPUAS::LOCAL_ADDRESS ||
DestAS == AMDGPUAS::PRIVATE_ADDRESS); DestAS == AMDGPUAS::PRIVATE_ADDRESS);
unsigned NullVal = TM.getNullPointerValue(DestAS); unsigned NullVal = TM.getNullPointerValue(DestAS);
unsigned SegmentNullReg = MRI.createGenericVirtualRegister(DstTy); auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
unsigned FlatNullReg = MRI.createGenericVirtualRegister(SrcTy); auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
MIRBuilder.buildConstant(SegmentNullReg, NullVal);
MIRBuilder.buildConstant(FlatNullReg, 0);
unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy); unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
// Extract low 32-bits of the pointer. // Extract low 32-bits of the pointer.
MIRBuilder.buildExtract(PtrLo32, Src, 0); MIRBuilder.buildExtract(PtrLo32, Src, 0);
unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1)); unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNullReg); MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNullReg); MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
assert(SrcAS == AMDGPUAS::LOCAL_ADDRESS || assert(SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
SrcAS == AMDGPUAS::PRIVATE_ADDRESS); SrcAS == AMDGPUAS::PRIVATE_ADDRESS);
unsigned FlatNullReg = MRI.createGenericVirtualRegister(DstTy); auto SegmentNull =
unsigned SegmentNullReg = MRI.createGenericVirtualRegister(SrcTy); MIRBuilder.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
MIRBuilder.buildConstant(SegmentNullReg, TM.getNullPointerValue(SrcAS)); auto FlatNull =
MIRBuilder.buildConstant(FlatNullReg, TM.getNullPointerValue(DestAS)); MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder); unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1)); unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNullReg); MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy); unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy);
// Coerce the type of the low half of the result so we can use merge_values. // Coerce the type of the low half of the result so we can use merge_values.
unsigned SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32)); unsigned SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT) MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
.addDef(SrcAsInt) .addDef(SrcAsInt)
.addUse(Src); .addUse(Src);
// TODO: Should we allow mismatched types but matching sizes in merges to // TODO: Should we allow mismatched types but matching sizes in merges to
// avoid the ptrtoint? // avoid the ptrtoint?
MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg}); MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNullReg); MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Show First 20 Lines • Show All 580 Lines • ▼ Show 20 Linesnext:
%sum2 = add i32 %in, 1 %sum2 = add i32 %in, 1
%res = add i32 %sum1, %sum2 %res = add i32 %sum1, %sum2
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: name: constant_int_start ; CHECK-LABEL: name: constant_int_start
; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[TWO]], [[ANSWER]] ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
define i32 @constant_int_start() { define i32 @constant_int_start() {
%res = add i32 2, 42 %res = add i32 2, 42
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: name: test_undef ; CHECK-LABEL: name: test_undef
; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[UNDEF]] ; CHECK: $w0 = COPY [[UNDEF]]
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; CHECK-LABEL: name: test_struct_memops ; CHECK-LABEL: name: test_struct_memops
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4) ; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4)
; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64)
; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr + 4) ; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr + 4)
; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store 1 into %ir.addr, align 4) ; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST1]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST2]](s64)
; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store 4 into %ir.addr + 4) ; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store 4 into %ir.addr + 4)
define void @test_struct_memops({ i8, i32 }* %addr) { define void @test_struct_memops({ i8, i32 }* %addr) {
%val = load { i8, i32 }, { i8, i32 }* %addr %val = load { i8, i32 }, { i8, i32 }* %addr
store { i8, i32 } %val, { i8, i32 }* %addr store { i8, i32 } %val, { i8, i32 }* %addr
ret void ret void
} }
; CHECK-LABEL: name: test_i1_memops ; CHECK-LABEL: name: test_i1_memops
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load 1 from %ir.addr + 4, align 4) ; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load 1 from %ir.addr + 4, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64) ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.addr + 8) ; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.addr + 8)
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64) ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12) ; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store 1 into %ir.addr2, align 4) ; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store 1 into %ir.addr2, align 4)
; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %1, [[CST1]](s64)
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %1, [[CST4]](s64)
; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store 4 into %ir.addr2 + 4) ; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store 4 into %ir.addr2 + 4)
define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) { define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
%struct = load %struct.nested, %struct.nested* %addr %struct = load %struct.nested, %struct.nested* %addr
%res = extractvalue %struct.nested %struct, 1 %res = extractvalue %struct.nested %struct, 1
store {i8, i32} %res, {i8, i32}* %addr2 store {i8, i32} %res, {i8, i32}* %addr2
ret void ret void
} }
; CHECK-LABEL: name: test_insertvalue ; CHECK-LABEL: name: test_insertvalue
; CHECK: %0:_(p0) = COPY $x0 ; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(s32) = COPY $w1 ; CHECK: %1:_(s32) = COPY $w1
; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4) ; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4)
; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load 1 from %ir.addr + 4, align 4) ; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load 1 from %ir.addr + 4, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64) ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.addr + 8) ; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.addr + 8)
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64) ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12) ; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store 1 into %ir.addr, align 4) ; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store 1 into %ir.addr + 4, align 4) ; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store 1 into %ir.addr + 4, align 4)
; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST5]](s64)
; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store 4 into %ir.addr + 8) ; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store 4 into %ir.addr + 8)
; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 ; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST6]](s64)
; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 12) ; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 12)
define void @test_insertvalue(%struct.nested* %addr, i32 %val) { define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
%struct = load %struct.nested, %struct.nested* %addr %struct = load %struct.nested, %struct.nested* %addr
%newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1 %newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1
store %struct.nested %newstruct, %struct.nested* %addr store %struct.nested %newstruct, %struct.nested* %addr
ret void ret void
} }
Show All 18 Lines
; CHECK-LABEL: name: test_insertvalue_agg ; CHECK-LABEL: name: test_insertvalue_agg
; CHECK: %0:_(p0) = COPY $x0 ; CHECK: %0:_(p0) = COPY $x0
; CHECK: %1:_(p0) = COPY $x1 ; CHECK: %1:_(p0) = COPY $x1
; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %1(p0) :: (load 1 from %ir.addr2, align 4) ; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %1(p0) :: (load 1 from %ir.addr2, align 4)
; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %1, [[CST1]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %1, [[CST1]](s64)
; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr2 + 4) ; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.addr2 + 4)
; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4) ; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr, align 4)
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP %0, [[CST2]](s64)
; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load 1 from %ir.addr + 4, align 4) ; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load 1 from %ir.addr + 4, align 4)
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64) ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[LD5:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 8) ; CHECK: [[LD5:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.addr + 8)
; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 ; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64) ; CHECK: [[GEP4:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load 4 from %ir.addr + 12) ; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load 4 from %ir.addr + 12)
; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store 1 into %ir.addr, align 4) ; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store 1 into %ir.addr, align 4)
; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST1]](s64)
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP %0, [[CST5]](s64)
; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store 1 into %ir.addr + 4, align 4) ; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store 1 into %ir.addr + 4, align 4)
; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST3]](s64)
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP %0, [[CST6]](s64)
; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 8) ; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store 4 into %ir.addr + 8)
; CHECK: [[CST7:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 ; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP %0, [[CST4]](s64)
; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP %0, [[CST7]](s64)
; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store 4 into %ir.addr + 12) ; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store 4 into %ir.addr + 12)
define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) { define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
%smallstruct = load {i8, i32}, {i8, i32}* %addr2 %smallstruct = load {i8, i32}, {i8, i32}* %addr2
%struct = load %struct.nested, %struct.nested* %addr %struct = load %struct.nested, %struct.nested* %addr
%res = insertvalue %struct.nested %struct, {i8, i32} %smallstruct, 1 %res = insertvalue %struct.nested %struct, {i8, i32} %smallstruct, 1
store %struct.nested %res, %struct.nested* %addr store %struct.nested %res, %struct.nested* %addr
ret void ret void
} }
▲ Show 20 Lines • Show All 1,314 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64 ; CHECK: [[EXT2:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64) ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]](s64)
; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1) ; CHECK: G_STORE [[EXT1]](s64), [[ADDR]](p0) :: (store 8 into stack, align 1)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]] ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1) ; CHECK: G_STORE [[EXT2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)
define void @test_split_struct([2 x i64]* %ptr) { define void @test_split_struct([2 x i64]* %ptr) {
%struct = load [2 x i64], [2 x i64]* %ptr %struct = load [2 x i64], [2 x i64]* %ptr
call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3, call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
i64 4, i64 5, i64 6, i64 4, i64 5, i64 6,
[2 x i64] %struct) [2 x i64] %struct)
ret void ret void
Show All 18 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0 ; CHECK: [[EXTLO:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 0
; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64 ; CHECK: [[EXTHI:%[0-9]+]]:_(s64) = G_EXTRACT [[INS2]](s128), 64
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64) ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST2]](s64)
; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1) ; CHECK: G_STORE [[EXTLO]](s64), [[GEP2]](p0) :: (store 8 into stack, align 1)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[CST3:%[0-9]+]]:_(s64) = COPY [[CST]]
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64) ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[CST3]](s64)
; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1) ; CHECK: G_STORE [[EXTHI]](s64), [[GEP3]](p0) :: (store 8 into stack + 8, align 1)
define void @test_split_struct([2 x i64]* %ptr) { define void @test_split_struct([2 x i64]* %ptr) {
%struct = load [2 x i64], [2 x i64]* %ptr %struct = load [2 x i64], [2 x i64]* %ptr
call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3, call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
i64 4, i64 5, i64 6, i64 4, i64 5, i64 6,
[2 x i64] %struct) [2 x i64] %struct)
ret void ret void
Show All 18 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_icmp name: test_icmp
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_icmp ; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32) ; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32) ; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32) ; CHECK: $w0 = COPY [[COPY4]](s32)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
Show All 15 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_div name: test_div
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_div ; CHECK-LABEL: name: test_div
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32) ; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C2]]
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32) ; CHECK: $w0 = COPY [[COPY3]](s32)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1 %1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64) %3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_SDIV %2, %3 %4:_(s8) = G_SDIV %2, %3
Show All 36 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: $w0 = COPY [[AND2]](s32) ; CHECK: $w0 = COPY [[AND2]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC8]](s32) ; CHECK: $w0 = COPY [[TRUNC8]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]] ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]]
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]] ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]]
; CHECK: $w0 = COPY [[ASHR2]](s32) ; CHECK: $w0 = COPY [[ASHR2]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C6]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C4]]
; CHECK: $w0 = COPY [[AND3]](s32) ; CHECK: $w0 = COPY [[AND3]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC11]](s32) ; CHECK: $w0 = COPY [[TRUNC11]](s32)
; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC12]](s32) ; CHECK: $w0 = COPY [[TRUNC12]](s32)
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32) ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
; CHECK: $x0 = COPY [[FPEXT]](s64) ; CHECK: $x0 = COPY [[FPEXT]](s64)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: $w0 = COPY [[C7]](s32) ; CHECK: $w0 = COPY [[C7]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: $w0 = COPY [[C8]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[DEF]](s32) ; CHECK: $w0 = COPY [[DEF]](s32)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64) %1:_(s1) = G_TRUNC %0(s64)
%19:_(s32) = G_ANYEXT %1(s1) %19:_(s32) = G_ANYEXT %1(s1)
$w0 = COPY %19(s32) $w0 = COPY %19(s32)
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%20:_(s32) = G_ANYEXT %2(s8) %20:_(s32) = G_ANYEXT %2(s8)
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir

Show All 12 Lines bb.1:
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, align 4) ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, align 4)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8, align 4) ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8, align 4)
; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8, align 4) ; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8, align 4)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8, align 4) ; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s128) = G_LOAD %0(p0) :: (load 16, align 4) %2:_(s128) = G_LOAD %0(p0) :: (load 16, align 4)
G_STORE %2(s128), %1(p0) :: (store 16, align 4) G_STORE %2(s128), %1(p0) :: (store 16, align 4)
RET_ReallyLR RET_ReallyLR
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir

Show All 9 Lines bb.0:
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C4]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C3]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY1]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8) ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s8) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s8)
; CHECK: $x0 = COPY [[ANYEXT]](s64) ; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = G_CONSTANT i64 0 %0:_(s64) = G_CONSTANT i64 0
%1:_(s4) = G_TRUNC %0 %1:_(s4) = G_TRUNC %0
%2:_(s8) = G_MERGE_VALUES %1, %1 %2:_(s8) = G_MERGE_VALUES %1, %1
%3:_(s8) = COPY %2 %3:_(s8) = COPY %2
%4:_(s64) = G_ANYEXT %3 %4:_(s64) = G_ANYEXT %3
$x0 = COPY %4 $x0 = COPY %4
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC4]](s16), %bb.2 ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC4]](s16), %bb.2
; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC3]](s16), %bb.2 ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: $w0 = COPY [[ADD2]](s32) ; CHECK: $w0 = COPY [[ADD2]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $w0 liveins: $w0
; Make sure that we correctly insert the new legalized G_PHI at the ; Make sure that we correctly insert the new legalized G_PHI at the
; correct location (ie make sure G_PHIs are the first insts in the BB). ; correct location (ie make sure G_PHIs are the first insts in the BB).
▲ Show 20 Lines • Show All 139 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_srem_8 ; CHECK-LABEL: name: test_srem_8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]] ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]] ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C]]
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]] ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]]
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]] ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

Show All 11 Lines bb.0.entry:
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; CHECK: $w0 = COPY [[COPY2]](s32) ; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32) ; CHECK: $w0 = COPY [[COPY3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C4]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[AND3]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[AND3]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32) ; CHECK: $w0 = COPY [[COPY4]](s32)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1 %1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64) %3:_(s8) = G_TRUNC %1(s64)
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64) ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s64) ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s64) ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[SHL]], [[C2]] ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[SHL]], [[C1]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[SHL2]] ; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[SHL2]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV1]], [[SELECT1]] ; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV1]], [[SELECT1]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64) ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; CHECK: $q0 = COPY [[MV]](s128) ; CHECK: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0 %0:_(s128) = COPY $q0
%1:_(s128) = COPY $q1 %1:_(s128) = COPY $q1
%2:_(s128) = G_SHL %0, %1 %2:_(s128) = G_SHL %0, %1
$q0 = COPY %2 $q0 = COPY %2
Show All 16 Lines bb.0:
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[TRUNC]](s64), [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[TRUNC]](s64), [[C1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[TRUNC]](s64) ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[TRUNC]](s64)
; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64) ; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[TRUNC]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s64) ; CHECK: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[LSHR2]] ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[OR]], [[LSHR2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV]], [[SELECT]] ; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UV]], [[SELECT]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[LSHR]], [[C2]] ; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC1]](s1), [[LSHR]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; CHECK: $q0 = COPY [[MV]](s128) ; CHECK: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0 %0:_(s128) = COPY $q0
%1:_(s128) = COPY $q1 %1:_(s128) = COPY $q1
%2:_(s128) = G_LSHR %0, %1 %2:_(s128) = G_LSHR %0, %1
$q0 = COPY %2 $q0 = COPY %2
... ...
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir

Show All 12 Linesbody: |
bb.0: bb.0:
; CHECK-LABEL: name: test_vaarg ; CHECK-LABEL: name: test_vaarg
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8) ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s64)
; CHECK: G_STORE [[GEP]](p0), [[COPY]](p0) :: (store 8) ; CHECK: G_STORE [[GEP]](p0), [[COPY]](p0) :: (store 8)
; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8) ; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C]](s64)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C1]](s64)
; CHECK: G_STORE [[GEP1]](p0), [[COPY]](p0) :: (store 8) ; CHECK: G_STORE [[GEP1]](p0), [[COPY]](p0) :: (store 8)
; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8) ; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[LOAD2]], [[C2]](s64) ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[LOAD2]], [[C1]](s64)
; CHECK: [[PTR_MASK:%[0-9]+]]:_(p0) = G_PTR_MASK [[GEP2]], 4 ; CHECK: [[PTR_MASK:%[0-9]+]]:_(p0) = G_PTR_MASK [[GEP2]], 4
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[PTR_MASK]], [[C]](s64)
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[PTR_MASK]], [[C3]](s64)
; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8) ; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8)
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_VAARG %0(p0), 1 %1:_(s8) = G_VAARG %0(p0), 1
%2:_(s64) = G_VAARG %0(p0), 8 %2:_(s64) = G_VAARG %0(p0), 8
%3:_(s64) = G_VAARG %0(p0), 16 %3:_(s64) = G_VAARG %0(p0), 16
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
%type = type [4 x {i8, i32}] %type = type [4 x {i8, i32}]
define i8* @translate_element_size1(i64 %arg) { define i8* @translate_element_size1(i64 %arg) {
; CHECK-LABEL: name: translate_element_size1 ; CHECK-LABEL: name: translate_element_size1
; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: bb.1 (%ir-block.0):
; CHECK: [[ZERO:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: liveins: $x0
; CHECK: [[BASE:%[0-9]+]]:_(p0) = G_INTTOPTR [[ZERO]] ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]] ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[INTTOPTR]], [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
; CHECK: $x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit $x0
%tmp = getelementptr i8, i8* null, i64 %arg %tmp = getelementptr i8, i8* null, i64 %arg
ret i8* %tmp ret i8* %tmp
} }
define %type* @first_offset_const(%type* %addr) { define %type* @first_offset_const(%type* %addr) {
; CHECK-LABEL: name: first_offset_const ; CHECK-LABEL: name: first_offset_const
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
Show All 39 Lines
define %type* @first_offset_ext(%type* %addr, i32 %idx) { define %type* @first_offset_ext(%type* %addr, i32 %idx) {
; CHECK-LABEL: name: first_offset_ext ; CHECK-LABEL: name: first_offset_ext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $w1, $x0 ; CHECK: liveins: $w1, $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32) ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 %idx %res = getelementptr %type, %type* %addr, i32 %idx
ret %type* %res ret %type* %res
} }
%type1 = type [4 x [4 x i32]] %type1 = type [4 x [4 x i32]]
define i32* @const_then_var(%type1* %addr, i64 %idx) { define i32* @const_then_var(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: const_then_var ; CHECK-LABEL: name: const_then_var
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C1]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C1]], [[COPY1]]
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[MUL]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP1]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP1]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx %res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
ret i32* %res ret i32* %res
} }
define i32* @var_then_const(%type1* %addr, i64 %idx) { define i32* @var_then_const(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: var_then_const ; CHECK-LABEL: name: var_then_const
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[C1]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[C1]](s64)
; CHECK: $x0 = COPY [[GEP1]](p0) ; CHECK: $x0 = COPY [[GEP1]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2 %res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
ret i32* %res ret i32* %res
} }

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines bb.0:
; VI-LABEL: name: test_addrspacecast_v2p0_to_v2p3 ; VI-LABEL: name: test_addrspacecast_v2p0_to_v2p3
; VI: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>) ; VI: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; VI: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[UV]](p0), 0 ; VI: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[UV]](p0), 0
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]] ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
; VI: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]] ; VI: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]]
; VI: [[C2:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; VI: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; VI: [[EXTRACT1:%[0-9]+]]:_(p3) = G_EXTRACT [[UV1]](p0), 0 ; VI: [[EXTRACT1:%[0-9]+]]:_(p3) = G_EXTRACT [[UV1]](p0), 0
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C3]] ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
; VI: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[EXTRACT1]], [[C2]] ; VI: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[EXTRACT1]], [[C]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>) ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
; GFX9-LABEL: name: test_addrspacecast_v2p0_to_v2p3 ; GFX9-LABEL: name: test_addrspacecast_v2p0_to_v2p3
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>) ; GFX9: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
; GFX9: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; GFX9: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GFX9: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; GFX9: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GFX9: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[UV]](p0), 0 ; GFX9: [[EXTRACT:%[0-9]+]]:_(p3) = G_EXTRACT [[UV]](p0), 0
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
; GFX9: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]] ; GFX9: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[EXTRACT]], [[C]]
; GFX9: [[C2:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GFX9: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GFX9: [[EXTRACT1:%[0-9]+]]:_(p3) = G_EXTRACT [[UV1]](p0), 0 ; GFX9: [[EXTRACT1:%[0-9]+]]:_(p3) = G_EXTRACT [[UV1]](p0), 0
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C3]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
; GFX9: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[EXTRACT1]], [[C2]] ; GFX9: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[EXTRACT1]], [[C]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
%0:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<2 x p0>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x p3>) = G_ADDRSPACE_CAST %0 %1:_(<2 x p3>) = G_ADDRSPACE_CAST %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_addrspacecast_v2p3_to_v2p0 name: test_addrspacecast_v2p3_to_v2p0
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; VI-LABEL: name: test_addrspacecast_v2p3_to_v2p0 ; VI-LABEL: name: test_addrspacecast_v2p3_to_v2p0
; VI: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) ; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559 ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559
; VI: [[COPY1:%[0-9]+]]:_(p4) = COPY [[C2]](p4)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64) ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY1]], [[C3]](s64)
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]] ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]]
; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3) ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32) ; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32)
; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]] ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]]
; VI: [[C4:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64)
; VI: [[C5:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; VI: [[C6:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[C6]], [[C7]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C4]] ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C]]
; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3) ; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; VI: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[LOAD1]](s32) ; VI: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[LOAD1]](s32)
; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C5]] ; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
; GFX9-LABEL: name: test_addrspacecast_v2p3_to_v2p0 ; GFX9-LABEL: name: test_addrspacecast_v2p3_to_v2p0
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) ; GFX9: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX9: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; GFX9: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GFX9: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; GFX9: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GFX9: [[S_GETREG_B32_:%[0-9]+]]:sreg_32(s32) = S_GETREG_B32 30735 ; GFX9: [[S_GETREG_B32_:%[0-9]+]]:sreg_32(s32) = S_GETREG_B32 30735
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[S_GETREG_B32_]], [[C2]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[S_GETREG_B32_]], [[C2]](s32)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]]
; GFX9: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3) ; GFX9: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
; GFX9: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[SHL]](s32) ; GFX9: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[SHL]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]] ; GFX9: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]]
; GFX9: [[C3:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GFX9: [[C4:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; GFX9: [[S_GETREG_B32_1:%[0-9]+]]:sreg_32(s32) = S_GETREG_B32 30735 ; GFX9: [[S_GETREG_B32_1:%[0-9]+]]:sreg_32(s32) = S_GETREG_B32 30735
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[S_GETREG_B32_1]], [[C2]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[S_GETREG_B32_1]], [[C5]](s32) ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C3]]
; GFX9: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3) ; GFX9: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; GFX9: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[SHL1]](s32) ; GFX9: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[SHL1]](s32)
; GFX9: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C4]] ; GFX9: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1 %0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x p0>) = G_ADDRSPACE_CAST %0 %1:_(<2 x p0>) = G_ADDRSPACE_CAST %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
... ...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

Show First 20 Lines • Show All 902 Lines • ▼ Show 20 Lines
--- ---
name: test_ashr_s128_s32_23 name: test_ashr_s128_s32_23
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_ashr_s128_s32_23 ; SI-LABEL: name: test_ashr_s128_s32_23
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_ashr_s128_s32_23 ; VI-LABEL: name: test_ashr_s128_s32_23
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_ashr_s128_s32_23 ; GFX9-LABEL: name: test_ashr_s128_s32_23
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 23 %1:_(s32) = G_CONSTANT i32 23
%3:_(s128) = G_ASHR %0, %1 %3:_(s128) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_ashr_s128_s32_31 name: test_ashr_s128_s32_31
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_ashr_s128_s32_31 ; SI-LABEL: name: test_ashr_s128_s32_31
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_ashr_s128_s32_31 ; VI-LABEL: name: test_ashr_s128_s32_31
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_ashr_s128_s32_31 ; GFX9-LABEL: name: test_ashr_s128_s32_31
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 31 %1:_(s32) = G_CONSTANT i32 31
%3:_(s128) = G_ASHR %0, %1 %3:_(s128) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_ashr_s128_s32_32 name: test_ashr_s128_s32_32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_ashr_s128_s32_32 ; SI-LABEL: name: test_ashr_s128_s32_32
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_ashr_s128_s32_32 ; VI-LABEL: name: test_ashr_s128_s32_32
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_ashr_s128_s32_32 ; GFX9-LABEL: name: test_ashr_s128_s32_32
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 32 %1:_(s32) = G_CONSTANT i32 32
%3:_(s128) = G_ASHR %0, %1 %3:_(s128) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_ashr_s128_s32_33 name: test_ashr_s128_s32_33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_ashr_s128_s32_33 ; SI-LABEL: name: test_ashr_s128_s32_33
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_ashr_s128_s32_33 ; VI-LABEL: name: test_ashr_s128_s32_33
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_ashr_s128_s32_33 ; GFX9-LABEL: name: test_ashr_s128_s32_33
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 33 %1:_(s32) = G_CONSTANT i32 33
%3:_(s128) = G_ASHR %0, %1 %3:_(s128) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_ashr_s128_s32_127 name: test_ashr_s128_s32_127
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_ashr_s128_s32_127 ; SI-LABEL: name: test_ashr_s128_s32_127
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128) ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C1]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_ashr_s128_s32_127 ; VI-LABEL: name: test_ashr_s128_s32_127
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128) ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C1]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_ashr_s128_s32_127 ; GFX9-LABEL: name: test_ashr_s128_s32_127
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128) ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 127 %1:_(s32) = G_CONSTANT i32 127
%3:_(s128) = G_ASHR %0, %1 %3:_(s128) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
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; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
; SI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32) ; SI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]]
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C7]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C4]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; SI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; SI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]] ; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]]
; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; SI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]] ; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]]
; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C10]] ; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C4]]
; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]] ; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]]
; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; SI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C11]](s32) ; SI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; SI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; SI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C12]](s32)
; SI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; SI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; SI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32) ; SI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32) ; SI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; SI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32) ; SI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32)
; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]] ; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]]
; SI: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
; SI: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C15]](s32)
; SI: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32) ; SI: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]] ; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]] ; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]] ; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]]
; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; SI: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]] ; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]]
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; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32) ; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
; VI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32) ; VI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]]
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C7]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C4]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; VI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; VI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; VI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]] ; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]]
; VI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; VI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]] ; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]]
; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C10]] ; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C4]]
; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]] ; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]]
; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; VI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C11]](s32) ; VI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; VI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; VI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C12]](s32)
; VI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; VI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; VI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32) ; VI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32) ; VI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; VI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32) ; VI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32)
; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]] ; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]]
; VI: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
; VI: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C15]](s32)
; VI: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32) ; VI: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]] ; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]] ; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]] ; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]]
; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; VI: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]] ; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]]
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; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[TRUNC]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB3]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32) ; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32) ; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL]]
; GFX9: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR4]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C7]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR2]], [[C4]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; GFX9: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; GFX9: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; GFX9: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]] ; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL1]]
; GFX9: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; GFX9: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]] ; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR7]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C10]] ; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR5]], [[C4]]
; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]] ; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]]
; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; GFX9: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C11]](s32) ; GFX9: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
; GFX9: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C12]](s32)
; GFX9: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; GFX9: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; GFX9: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32) ; GFX9: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; GFX9: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32) ; GFX9: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; GFX9: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32) ; GFX9: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV11]], [[SUB9]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]] ; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[LSHR9]]
; GFX9: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
; GFX9: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C15]](s32)
; GFX9: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32) ; GFX9: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]] ; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]] ; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]] ; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[ASHR5]], [[ASHR6]]
; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; GFX9: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV12:%[0-9]+]]:_(s64), [[UV13:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]] ; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV12]], [[SELECT12]]
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; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32)
; SI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32) ; SI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; SI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32) ; SI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32)
; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; SI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C2]](s32)
; SI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C5]](s32)
; SI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32) ; SI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]]
; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; VI-LABEL: name: test_ashr_v2s128_v2s32 ; VI-LABEL: name: test_ashr_v2s128_v2s32
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; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32) ; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32)
; VI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32) ; VI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; VI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32) ; VI: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32)
; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32) ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; VI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C2]](s32)
; VI: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C5]](s32)
; VI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32) ; VI: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]]
; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; GFX9-LABEL: name: test_ashr_v2s128_v2s32 ; GFX9-LABEL: name: test_ashr_v2s128_v2s32
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; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[LSHR1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32) ; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[C2]](s32)
; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32) ; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV5]], [[SUB]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[ASHR2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; GFX9: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32) ; GFX9: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[UV3]](s32)
; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB3]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[LSHR3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C2]](s32)
; GFX9: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[C5]](s32)
; GFX9: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32) ; GFX9: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV7]], [[SUB2]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[ASHR5]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR3]], [[ASHR4]]
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5 %1:_(<2 x s32>) = COPY $vgpr4_vgpr5
%2:_(<2 x s128>) = G_ASHR %0, %1 %2:_(<2 x s128>) = G_ASHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
... ...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: bswap_v2s16 ; CHECK-LABEL: name: bswap_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]] ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[COPY1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
; CHECK: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT1]] ; CHECK: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP1]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP1]], [[C1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_BSWAP %0 %1:_(<2 x s16>) = G_BSWAP %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
Show All 18 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTLZ_ZERO_UNDEF %1 %2:_(s16) = G_CTLZ_ZERO_UNDEF %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ZEXT]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ZEXT]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ZEXT1]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ZEXT1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF1]], [[C]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_CTLZ_ZERO_UNDEF %0 %1:_(<2 x s16>) = G_CTLZ_ZERO_UNDEF %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
Show All 9 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTLZ_ZERO_UNDEF %1 %2:_(s7) = G_CTLZ_ZERO_UNDEF %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 32 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTLZ %1 %2:_(s16) = G_CTLZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ZEXT]](s32) ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ZEXT]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
; CHECK: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[ZEXT1]](s32) ; CHECK: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[ZEXT1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ1]], [[C]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_CTLZ %0 %1:_(<2 x s16>) = G_CTLZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
Show All 9 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTLZ %1 %2:_(s7) = G_CTLZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 32 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctpop_s16_s16 ; CHECK-LABEL: name: ctpop_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32) ; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTPOP %1 %2:_(s16) = G_CTPOP %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: ctpop_s7_s7 ; CHECK-LABEL: name: ctpop_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32) ; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTPOP %1 %2:_(s7) = G_CTPOP %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 26 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cttz_zero_undef_s16_s16 ; CHECK-LABEL: name: cttz_zero_undef_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTTZ_ZERO_UNDEF %1 %2:_(s16) = G_CTTZ_ZERO_UNDEF %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: cttz_zero_undef_s7_s7 ; CHECK-LABEL: name: cttz_zero_undef_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTTZ_ZERO_UNDEF %1 %2:_(s7) = G_CTTZ_ZERO_UNDEF %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 26 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTTZ %1 %2:_(s16) = G_CTTZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[C]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[C]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[C]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[C1]]
; CHECK: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[OR1]](s32) ; CHECK: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[OR1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_CTTZ %0 %1:_(<2 x s16>) = G_CTTZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
Show All 10 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTTZ %1 %2:_(s7) = G_CTTZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 28 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_icmp_s16 ; CHECK-LABEL: name: test_icmp_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]] ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32) ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
%0:_(s16) = G_CONSTANT i16 0 %0:_(s16) = G_CONSTANT i16 0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
Show All 10 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_icmp_s8 ; CHECK-LABEL: name: test_icmp_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]] ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: $vgpr0 = COPY [[COPY5]](s32) ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_lshr_s16_s16 ; SI-LABEL: name: test_lshr_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_s16_s16 ; VI-LABEL: name: test_lshr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_lshr_i8_i8 ; SI-LABEL: name: test_lshr_i8_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_i8_i8 ; VI-LABEL: name: test_lshr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]] ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16) ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i8_i8 ; GFX9-LABEL: name: test_lshr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]] ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16) ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
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--- ---
name: test_lshr_s128_s32_23 name: test_lshr_s128_s32_23
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_lshr_s128_s32_23 ; SI-LABEL: name: test_lshr_s128_s32_23
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_lshr_s128_s32_23 ; VI-LABEL: name: test_lshr_s128_s32_23
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_lshr_s128_s32_23 ; GFX9-LABEL: name: test_lshr_s128_s32_23
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 23 %1:_(s32) = G_CONSTANT i32 23
%3:_(s128) = G_LSHR %0, %1 %3:_(s128) = G_LSHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_lshr_s128_s32_31 name: test_lshr_s128_s32_31
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_lshr_s128_s32_31 ; SI-LABEL: name: test_lshr_s128_s32_31
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_lshr_s128_s32_31 ; VI-LABEL: name: test_lshr_s128_s32_31
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_lshr_s128_s32_31 ; GFX9-LABEL: name: test_lshr_s128_s32_31
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 31 %1:_(s32) = G_CONSTANT i32 31
%3:_(s128) = G_LSHR %0, %1 %3:_(s128) = G_LSHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_lshr_s128_s32_32 name: test_lshr_s128_s32_32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_lshr_s128_s32_32 ; SI-LABEL: name: test_lshr_s128_s32_32
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_lshr_s128_s32_32 ; VI-LABEL: name: test_lshr_s128_s32_32
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_lshr_s128_s32_32 ; GFX9-LABEL: name: test_lshr_s128_s32_32
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 32 %1:_(s32) = G_CONSTANT i32 32
%3:_(s128) = G_LSHR %0, %1 %3:_(s128) = G_LSHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_lshr_s128_s32_33 name: test_lshr_s128_s32_33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_lshr_s128_s32_33 ; SI-LABEL: name: test_lshr_s128_s32_33
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_lshr_s128_s32_33 ; VI-LABEL: name: test_lshr_s128_s32_33
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_lshr_s128_s32_33 ; GFX9-LABEL: name: test_lshr_s128_s32_33
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines bb.0:
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C4]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C7]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; SI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32) ; SI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]] ; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]]
; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32) ; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C10]] ; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]] ; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]] ; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]] ; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; SI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; SI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32) ; SI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32) ; SI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32) ; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]] ; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]]
; SI: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32) ; SI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]] ; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]] ; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C15]] ; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]] ; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; SI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]] ; SI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
; SI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C11]] ; SI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
; SI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; SI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; SI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; SI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
; VI-LABEL: name: test_lshr_s256_s256 ; VI-LABEL: name: test_lshr_s256_s256
; VI: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; VI: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
; VI: [[ZEXT:%[0-9]+]]:_(s256) = G_ZEXT [[COPY1]](s32) ; VI: [[ZEXT:%[0-9]+]]:_(s256) = G_ZEXT [[COPY1]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ZEXT]](s256) ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ZEXT]](s256)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; VI: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256) ; VI: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C]] ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C]]
; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32) ; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C4]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C7]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; VI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; VI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32) ; VI: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]] ; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]]
; VI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32) ; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C10]] ; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]] ; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]] ; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]] ; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; VI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; VI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32) ; VI: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32) ; VI: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32) ; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]] ; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]]
; VI: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32) ; VI: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]] ; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]] ; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C15]] ; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]] ; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; VI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]] ; VI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
; VI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C11]] ; VI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
; VI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; VI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; VI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; VI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
; GFX9-LABEL: name: test_lshr_s256_s256 ; GFX9-LABEL: name: test_lshr_s256_s256
; GFX9: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX9: [[ZEXT:%[0-9]+]]:_(s256) = G_ZEXT [[COPY1]](s32) ; GFX9: [[ZEXT:%[0-9]+]]:_(s256) = G_ZEXT [[COPY1]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ZEXT]](s256) ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ZEXT]](s256)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256) ; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C]] ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C]]
; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[TRUNC]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[TRUNC]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; GFX9: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C4]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[TRUNC]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[TRUNC]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; GFX9: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C7]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; GFX9: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32) ; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; GFX9: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32) ; GFX9: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]] ; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL3]], [[LSHR6]]
; GFX9: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32) ; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C10]] ; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]] ; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]] ; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]] ; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; GFX9: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; GFX9: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32) ; GFX9: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; GFX9: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32) ; GFX9: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32) ; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]] ; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR8]], [[SHL5]]
; GFX9: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32) ; GFX9: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]] ; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]] ; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C15]] ; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]] ; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]] ; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; GFX9: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]] ; GFX9: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
; GFX9: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C11]] ; GFX9: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
; GFX9: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; GFX9: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; GFX9: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; GFX9: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
%0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s32) = COPY $vgpr8 %1:_(s32) = COPY $vgpr8
%2:_(s256) = G_ZEXT %1 %2:_(s256) = G_ZEXT %1
%3:_(s256) = G_LSHR %0, %2 %3:_(s256) = G_LSHR %0, %2
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %3
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; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32) ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32) ; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C5]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C2]]
; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; VI-LABEL: name: test_lshr_v2s128_v2s32 ; VI-LABEL: name: test_lshr_v2s128_v2s32
; VI: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; VI: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; VI: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>) ; VI: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
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; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32) ; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32) ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32) ; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C5]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C2]]
; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; GFX9-LABEL: name: test_lshr_v2s128_v2s32 ; GFX9-LABEL: name: test_lshr_v2s128_v2s32
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>) ; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
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; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV4]], [[SELECT]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[UV3]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[UV3]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB3]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL1]]
; GFX9: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB2]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[LSHR5]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV6]], [[SELECT3]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C5]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR3]], [[C2]]
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5 %1:_(<2 x s32>) = COPY $vgpr4_vgpr5
%2:_(<2 x s128>) = G_LSHR %0, %1 %2:_(<2 x s128>) = G_LSHR %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
... ...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir

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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32) ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s16) = G_MERGE_VALUES %0, %1 %2:_(s16) = G_MERGE_VALUES %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
Show All 11 Lines bb.0:
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]]
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C7]](s32) ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C8]]
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]] ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
; CHECK: $vgpr0 = COPY [[COPY8]](s32) ; CHECK: $vgpr0 = COPY [[COPY8]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
Show All 10 Lines bb.0:
; CHECK-LABEL: name: test_merge_s32_s8_s8_s8_s8 ; CHECK-LABEL: name: test_merge_s32_s8_s8_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C5]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C8]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]] ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: $vgpr0 = COPY [[OR2]](s32) ; CHECK: $vgpr0 = COPY [[OR2]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2 %2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_CONSTANT i8 3 %3:_(s8) = G_CONSTANT i8 3
%4:_(s32) = G_MERGE_VALUES %0, %1, %2, %3 %4:_(s32) = G_MERGE_VALUES %0, %1, %2, %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

Show First 20 Lines • Show All 961 Lines • ▼ Show 20 Lines
--- ---
name: test_shl_s128_s32_23 name: test_shl_s128_s32_23
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_shl_s128_s32_23 ; SI-LABEL: name: test_shl_s128_s32_23
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_shl_s128_s32_23 ; VI-LABEL: name: test_shl_s128_s32_23
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_shl_s128_s32_23 ; GFX9-LABEL: name: test_shl_s128_s32_23
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 41 ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 23 %1:_(s32) = G_CONSTANT i32 23
%3:_(s128) = G_SHL %0, %1 %3:_(s128) = G_SHL %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_shl_s128_s32_31 name: test_shl_s128_s32_31
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_shl_s128_s32_31 ; SI-LABEL: name: test_shl_s128_s32_31
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_shl_s128_s32_31 ; VI-LABEL: name: test_shl_s128_s32_31
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_shl_s128_s32_31 ; GFX9-LABEL: name: test_shl_s128_s32_31
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 31 %1:_(s32) = G_CONSTANT i32 31
%3:_(s128) = G_SHL %0, %1 %3:_(s128) = G_SHL %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_shl_s128_s32_32 name: test_shl_s128_s32_32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_shl_s128_s32_32 ; SI-LABEL: name: test_shl_s128_s32_32
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_shl_s128_s32_32 ; VI-LABEL: name: test_shl_s128_s32_32
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_shl_s128_s32_32 ; GFX9-LABEL: name: test_shl_s128_s32_32
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 32 %1:_(s32) = G_CONSTANT i32 32
%3:_(s128) = G_SHL %0, %1 %3:_(s128) = G_SHL %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: test_shl_s128_s32_33 name: test_shl_s128_s32_33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; SI-LABEL: name: test_shl_s128_s32_33 ; SI-LABEL: name: test_shl_s128_s32_33
; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; SI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; VI-LABEL: name: test_shl_s128_s32_33 ; VI-LABEL: name: test_shl_s128_s32_33
; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; VI: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX9-LABEL: name: test_shl_s128_s32_33 ; GFX9-LABEL: name: test_shl_s128_s32_33
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[C1]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 33 %1:_(s32) = G_CONSTANT i32 33
%3:_(s128) = G_SHL %0, %1 %3:_(s128) = G_SHL %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.0:
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32) ; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C4]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; SI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; SI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32) ; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C7]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C3]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; SI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; SI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; SI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; SI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; SI: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; SI: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]] ; SI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]]
; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; SI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]] ; SI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]]
; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; SI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C10]] ; SI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C3]]
; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]] ; SI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]]
; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; SI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; SI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; SI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; SI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; SI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; SI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; SI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; SI: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; SI: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; SI: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; SI: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32) ; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]] ; SI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]]
; SI: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32) ; SI: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C15]] ; SI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]] ; SI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]] ; SI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C11]] ; SI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; SI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]] ; SI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; SI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; SI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]] ; SI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]]
; SI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]] ; SI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]]
; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; SI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; SI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
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; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32) ; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C4]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; VI: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; VI: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32) ; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C7]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C3]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; VI: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; VI: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; VI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; VI: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; VI: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; VI: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; VI: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]] ; VI: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]]
; VI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; VI: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]] ; VI: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]]
; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; VI: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C10]] ; VI: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C3]]
; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]] ; VI: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]]
; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; VI: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; VI: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; VI: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; VI: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; VI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; VI: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; VI: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; VI: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; VI: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; VI: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; VI: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32) ; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]] ; VI: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]]
; VI: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32) ; VI: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C15]] ; VI: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]] ; VI: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]] ; VI: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C11]] ; VI: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; VI: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]] ; VI: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; VI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; VI: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]] ; VI: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]]
; VI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]] ; VI: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]]
; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; VI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; VI: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
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; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]] ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]] ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; GFX9: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C4]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C5]] ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C2]]
; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[TRUNC]] ; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[TRUNC]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C2]]
; GFX9: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C5]] ; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C1]]
; GFX9: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C6]]
; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32) ; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[TRUNC]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; GFX9: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32) ; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB4]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C7]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL3]], [[C3]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[SHL5]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV5]], [[SELECT4]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]] ; GFX9: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]] ; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
; GFX9: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
; GFX9: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]] ; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32) ; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB1]](s32)
; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32) ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB1]](s32)
; GFX9: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32) ; GFX9: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB7]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]] ; GFX9: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL6]]
; GFX9: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32) ; GFX9: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV7]], [[SUB6]](s32)
; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]] ; GFX9: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[LSHR4]]
; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]] ; GFX9: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV6]], [[SELECT6]]
; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C10]] ; GFX9: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[LSHR2]], [[C3]]
; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]] ; GFX9: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT7]]
; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]] ; GFX9: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128) ; GFX9: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C13]] ; GFX9: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB]] ; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
; GFX9: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
; GFX9: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C13]] ; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
; GFX9: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C14]]
; GFX9: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; GFX9: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; GFX9: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32) ; GFX9: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32) ; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]] ; GFX9: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL8]], [[LSHR5]]
; GFX9: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32) ; GFX9: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C15]] ; GFX9: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]] ; GFX9: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]] ; GFX9: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C11]] ; GFX9: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C12]] ; GFX9: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]] ; GFX9: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; GFX9: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]] ; GFX9: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]] ; GFX9: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT14]]
; GFX9: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]] ; GFX9: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT15]]
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; GFX9: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128) ; GFX9: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
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; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32) ; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32)
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]] ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]] ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]] ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]]
; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64) ; SI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; SI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; SI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; SI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32)
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32) ; SI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32)
; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C5]] ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C2]]
; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]] ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]]
; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]] ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]]
; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64) ; SI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; VI-LABEL: name: test_shl_v2s128_v2s32 ; VI-LABEL: name: test_shl_v2s128_v2s32
; VI: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; VI: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
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; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32) ; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32)
; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]] ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]] ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]] ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]]
; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64) ; VI: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; VI: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; VI: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; VI: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32) ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32)
; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; VI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32) ; VI: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32)
; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C5]] ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C2]]
; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]] ; VI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]]
; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]] ; VI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]]
; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64) ; VI: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64)
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; GFX9-LABEL: name: test_shl_v2s128_v2s32 ; GFX9-LABEL: name: test_shl_v2s128_v2s32
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
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; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV4]], [[SUB]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]] ; GFX9: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]] ; GFX9: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]] ; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV5]], [[SELECT1]]
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128) ; GFX9: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C3]] ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV3]], [[C]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[UV3]] ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C]], [[UV3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[UV3]](s32), [[C3]] ; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C1]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](s32), [[C4]]
; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; GFX9: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32) ; GFX9: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[UV3]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB3]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; GFX9: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; GFX9: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32) ; GFX9: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB2]](s32)
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C5]] ; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C2]]
; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]] ; GFX9: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR1]], [[SHL5]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]] ; GFX9: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV7]], [[SELECT4]]
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(<2 x s32>) = COPY $vgpr4_vgpr5 %1:_(<2 x s32>) = COPY $vgpr4_vgpr5
%2:_(<2 x s128>) = G_SHL %0, %1 %2:_(<2 x s128>) = G_SHL %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %2
... ...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir

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liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_uaddo_s7 ; CHECK-LABEL: name: test_uaddo_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
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liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_uaddo_s16 ; CHECK-LABEL: name: test_uaddo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16), %5:_(s1) = G_UADDO %2, %3 %4:_(s16), %5:_(s1) = G_UADDO %2, %3
%6:_(s32) = G_ZEXT %4 %6:_(s32) = G_ZEXT %4
%7:_(s32) = G_ZEXT %5 %7:_(s32) = G_ZEXT %5
$vgpr0 = COPY %6 $vgpr0 = COPY %6
$vgpr1 = COPY %7 $vgpr1 = COPY %7
... ...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s48) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s48)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[TRUNC1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[TRUNC1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[SHL]](s64) ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[SHL]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]]
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 30 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[C3]](s64) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[C2]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC2]](s48) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC2]](s48)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64) ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[TRUNC3]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[TRUNC3]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[OR]](s64) ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SHL1]](s64) ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SHL1]](s64)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY3]], [[COPY4]] ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY3]], [[COPY4]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s48) = G_TRUNC [[OR1]](s64) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s48) = G_TRUNC [[OR1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC4]](s48) ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC4]](s48)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[COPY]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128) ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ANYEXT]](s128)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64) ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C2]](s64), [[C1]](s64)
; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C2]](s64), [[C3]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV1]](s128) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV1]](s128)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128) ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C4]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C3]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[TRUNC]] ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C4]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC]](s32), [[C3]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C5]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC]](s32), [[C4]]
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[TRUNC]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB1]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C6]] ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C1]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]] ; CHECK: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV3]], [[SELECT1]] ; CHECK: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV3]], [[SELECT1]]
; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128) ; CHECK: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s128)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[UV4]], [[SELECT]] ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[UV4]], [[SELECT]]
; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[UV5]], [[SELECT2]] ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[UV5]], [[SELECT2]]
; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 30 ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 30
; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C5]](s64), [[C1]](s64)
; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C7]](s64), [[C8]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV2]](s128) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV2]](s128)
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC1]], [[C3]]
; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[TRUNC1]], [[C9]] ; CHECK: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC1]]
; CHECK: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[TRUNC1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC1]](s32), [[C3]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC1]](s32), [[C4]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC1]](s32), [[C9]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC1]](s32), [[C10]]
; CHECK: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32) ; CHECK: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32)
; CHECK: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32) ; CHECK: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[TRUNC1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[SUB3]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[OR1]], [[SUB3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]] ; CHECK: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR1]]
; CHECK: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[SUB2]](s32) ; CHECK: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[SUB2]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C11]] ; CHECK: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL3]], [[C1]]
; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR3]], [[SHL5]] ; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR3]], [[SHL5]]
; CHECK: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[OR2]], [[SELECT4]] ; CHECK: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[OR2]], [[SELECT4]]
; CHECK: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SELECT3]] ; CHECK: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SELECT3]]
; CHECK: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[SELECT5]] ; CHECK: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[SELECT5]]
; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 45 ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 45
; CHECK: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C6]](s64), [[C1]](s64)
; CHECK: [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C12]](s64), [[C13]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s128) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s128)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC2]], [[C3]]
; CHECK: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[TRUNC2]], [[C14]] ; CHECK: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC2]]
; CHECK: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C14]], [[TRUNC2]] ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC2]](s32), [[C3]]
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC2]](s32), [[C4]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC2]](s32), [[C14]]
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC2]](s32), [[C15]]
; CHECK: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32) ; CHECK: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32)
; CHECK: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32) ; CHECK: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[OR5]], [[TRUNC2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[SUB5]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[OR4]], [[SUB5]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL7]], [[LSHR2]] ; CHECK: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL7]], [[LSHR2]]
; CHECK: [[C16:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[SUB4]](s32) ; CHECK: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[SUB4]](s32)
; CHECK: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL6]], [[C16]] ; CHECK: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[SHL6]], [[C1]]
; CHECK: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR6]], [[SHL8]] ; CHECK: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR6]], [[SHL8]]
; CHECK: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[OR5]], [[SELECT7]] ; CHECK: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[OR5]], [[SELECT7]]
; CHECK: [[OR7:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[SELECT6]] ; CHECK: [[OR7:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[SELECT6]]
; CHECK: [[OR8:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[SELECT8]] ; CHECK: [[OR8:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[SELECT8]]
; CHECK: [[C17:%[0-9]+]]:_(s64) = G_CONSTANT i64 60 ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
; CHECK: [[C18:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C7]](s64), [[C1]](s64)
; CHECK: [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C17]](s64), [[C18]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MV4]](s128) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MV4]](s128)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[C3]]
; CHECK: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[C19]] ; CHECK: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC3]]
; CHECK: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C19]], [[TRUNC3]] ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC3]](s32), [[C3]]
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC3]](s32), [[C4]]
; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC3]](s32), [[C19]]
; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC3]](s32), [[C20]]
; CHECK: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32) ; CHECK: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32)
; CHECK: [[SHL10:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32) ; CHECK: [[SHL10:%[0-9]+]]:_(s64) = G_SHL [[OR8]], [[TRUNC3]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR7]], [[SUB7]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[OR7]], [[SUB7]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s64) = G_OR [[SHL10]], [[LSHR3]] ; CHECK: [[OR9:%[0-9]+]]:_(s64) = G_OR [[SHL10]], [[LSHR3]]
; CHECK: [[C21:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL11:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[SUB6]](s32) ; CHECK: [[SHL11:%[0-9]+]]:_(s64) = G_SHL [[OR7]], [[SUB6]](s32)
; CHECK: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL9]], [[C21]] ; CHECK: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL9]], [[C1]]
; CHECK: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR9]], [[SHL11]] ; CHECK: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR9]], [[SHL11]]
; CHECK: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[OR8]], [[SELECT10]] ; CHECK: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[OR8]], [[SELECT10]]
; CHECK: [[OR10:%[0-9]+]]:_(s64) = G_OR [[OR7]], [[SELECT9]] ; CHECK: [[OR10:%[0-9]+]]:_(s64) = G_OR [[OR7]], [[SELECT9]]
; CHECK: [[OR11:%[0-9]+]]:_(s64) = G_OR [[OR8]], [[SELECT11]] ; CHECK: [[OR11:%[0-9]+]]:_(s64) = G_OR [[OR8]], [[SELECT11]]
; CHECK: [[C22:%[0-9]+]]:_(s64) = G_CONSTANT i64 75 ; CHECK: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 75
; CHECK: [[C23:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C8]](s64), [[C1]](s64)
; CHECK: [[MV5:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C22]](s64), [[C23]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[MV5]](s128) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[MV5]](s128)
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[TRUNC4]], [[C3]]
; CHECK: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[TRUNC4]], [[C24]] ; CHECK: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC4]]
; CHECK: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C24]], [[TRUNC4]] ; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC4]](s32), [[C3]]
; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC4]](s32), [[C4]]
; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC4]](s32), [[C24]]
; CHECK: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC4]](s32), [[C25]]
; CHECK: [[SHL12:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32) ; CHECK: [[SHL12:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32)
; CHECK: [[SHL13:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32) ; CHECK: [[SHL13:%[0-9]+]]:_(s64) = G_SHL [[OR11]], [[TRUNC4]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR10]], [[SUB9]](s32) ; CHECK: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[OR10]], [[SUB9]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[LSHR4]] ; CHECK: [[OR12:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[LSHR4]]
; CHECK: [[C26:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL14:%[0-9]+]]:_(s64) = G_SHL [[OR10]], [[SUB8]](s32) ; CHECK: [[SHL14:%[0-9]+]]:_(s64) = G_SHL [[OR10]], [[SUB8]](s32)
; CHECK: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL12]], [[C26]] ; CHECK: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL12]], [[C1]]
; CHECK: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR12]], [[SHL14]] ; CHECK: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR12]], [[SHL14]]
; CHECK: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[OR11]], [[SELECT13]] ; CHECK: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[OR11]], [[SELECT13]]
; CHECK: [[OR13:%[0-9]+]]:_(s64) = G_OR [[OR10]], [[SELECT12]] ; CHECK: [[OR13:%[0-9]+]]:_(s64) = G_OR [[OR10]], [[SELECT12]]
; CHECK: [[OR14:%[0-9]+]]:_(s64) = G_OR [[OR11]], [[SELECT14]] ; CHECK: [[OR14:%[0-9]+]]:_(s64) = G_OR [[OR11]], [[SELECT14]]
; CHECK: [[C27:%[0-9]+]]:_(s64) = G_CONSTANT i64 90 ; CHECK: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 90
; CHECK: [[C28:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C9]](s64), [[C1]](s64)
; CHECK: [[MV6:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C27]](s64), [[C28]](s64)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[MV6]](s128) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[MV6]](s128)
; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB10:%[0-9]+]]:_(s32) = G_SUB [[TRUNC5]], [[C3]]
; CHECK: [[SUB10:%[0-9]+]]:_(s32) = G_SUB [[TRUNC5]], [[C29]] ; CHECK: [[SUB11:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC5]]
; CHECK: [[SUB11:%[0-9]+]]:_(s32) = G_SUB [[C29]], [[TRUNC5]] ; CHECK: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC5]](s32), [[C3]]
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC5]](s32), [[C4]]
; CHECK: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC5]](s32), [[C29]]
; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC5]](s32), [[C30]]
; CHECK: [[SHL15:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32) ; CHECK: [[SHL15:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32)
; CHECK: [[SHL16:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32) ; CHECK: [[SHL16:%[0-9]+]]:_(s64) = G_SHL [[OR14]], [[TRUNC5]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR13]], [[SUB11]](s32) ; CHECK: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[OR13]], [[SUB11]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s64) = G_OR [[SHL16]], [[LSHR5]] ; CHECK: [[OR15:%[0-9]+]]:_(s64) = G_OR [[SHL16]], [[LSHR5]]
; CHECK: [[C31:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL17:%[0-9]+]]:_(s64) = G_SHL [[OR13]], [[SUB10]](s32) ; CHECK: [[SHL17:%[0-9]+]]:_(s64) = G_SHL [[OR13]], [[SUB10]](s32)
; CHECK: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[SHL15]], [[C31]] ; CHECK: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[SHL15]], [[C1]]
; CHECK: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[OR15]], [[SHL17]] ; CHECK: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP10]](s1), [[OR15]], [[SHL17]]
; CHECK: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP11]](s1), [[OR14]], [[SELECT16]] ; CHECK: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP11]](s1), [[OR14]], [[SELECT16]]
; CHECK: [[OR16:%[0-9]+]]:_(s64) = G_OR [[OR13]], [[SELECT15]] ; CHECK: [[OR16:%[0-9]+]]:_(s64) = G_OR [[OR13]], [[SELECT15]]
; CHECK: [[OR17:%[0-9]+]]:_(s64) = G_OR [[OR14]], [[SELECT17]] ; CHECK: [[OR17:%[0-9]+]]:_(s64) = G_OR [[OR14]], [[SELECT17]]
; CHECK: [[C32:%[0-9]+]]:_(s64) = G_CONSTANT i64 105 ; CHECK: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 105
; CHECK: [[C33:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C10]](s64), [[C1]](s64)
; CHECK: [[MV7:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C32]](s64), [[C33]](s64)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[MV7]](s128) ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[MV7]](s128)
; CHECK: [[C34:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 ; CHECK: [[SUB12:%[0-9]+]]:_(s32) = G_SUB [[TRUNC6]], [[C3]]
; CHECK: [[SUB12:%[0-9]+]]:_(s32) = G_SUB [[TRUNC6]], [[C34]] ; CHECK: [[SUB13:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[TRUNC6]]
; CHECK: [[SUB13:%[0-9]+]]:_(s32) = G_SUB [[C34]], [[TRUNC6]] ; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC6]](s32), [[C3]]
; CHECK: [[C35:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC6]](s32), [[C4]]
; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[TRUNC6]](s32), [[C34]]
; CHECK: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[TRUNC6]](s32), [[C35]]
; CHECK: [[SHL18:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32) ; CHECK: [[SHL18:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32)
; CHECK: [[SHL19:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32) ; CHECK: [[SHL19:%[0-9]+]]:_(s64) = G_SHL [[OR17]], [[TRUNC6]](s32)
; CHECK: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR16]], [[SUB13]](s32) ; CHECK: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[OR16]], [[SUB13]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s64) = G_OR [[SHL19]], [[LSHR6]] ; CHECK: [[OR18:%[0-9]+]]:_(s64) = G_OR [[SHL19]], [[LSHR6]]
; CHECK: [[C36:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[SHL20:%[0-9]+]]:_(s64) = G_SHL [[OR16]], [[SUB12]](s32) ; CHECK: [[SHL20:%[0-9]+]]:_(s64) = G_SHL [[OR16]], [[SUB12]](s32)
; CHECK: [[SELECT18:%[0-9]+]]:_(s64) = G_SELECT [[ICMP12]](s1), [[SHL18]], [[C36]] ; CHECK: [[SELECT18:%[0-9]+]]:_(s64) = G_SELECT [[ICMP12]](s1), [[SHL18]], [[C1]]
; CHECK: [[SELECT19:%[0-9]+]]:_(s64) = G_SELECT [[ICMP12]](s1), [[OR18]], [[SHL20]] ; CHECK: [[SELECT19:%[0-9]+]]:_(s64) = G_SELECT [[ICMP12]](s1), [[OR18]], [[SHL20]]
; CHECK: [[SELECT20:%[0-9]+]]:_(s64) = G_SELECT [[ICMP13]](s1), [[OR17]], [[SELECT19]] ; CHECK: [[SELECT20:%[0-9]+]]:_(s64) = G_SELECT [[ICMP13]](s1), [[OR17]], [[SELECT19]]
; CHECK: [[OR19:%[0-9]+]]:_(s64) = G_OR [[OR16]], [[SELECT18]] ; CHECK: [[OR19:%[0-9]+]]:_(s64) = G_OR [[OR16]], [[SELECT18]]
; CHECK: [[OR20:%[0-9]+]]:_(s64) = G_OR [[OR17]], [[SELECT20]] ; CHECK: [[OR20:%[0-9]+]]:_(s64) = G_OR [[OR17]], [[SELECT20]]
; CHECK: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR19]](s64) ; CHECK: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR19]](s64)
; CHECK: [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR20]](s64) ; CHECK: [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR20]](s64)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s16) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s16) ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s16)
Show All 34 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

Show All 28 Lines bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_usubo_s7 ; CHECK-LABEL: name: test_usubo_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
Show All 11 Lines bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_usubo_s16 ; CHECK-LABEL: name: test_usubo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16), %5:_(s1) = G_USUBO %2, %3 %4:_(s16), %5:_(s1) = G_USUBO %2, %3
%6:_(s32) = G_ZEXT %4 %6:_(s32) = G_ZEXT %4
%7:_(s32) = G_ZEXT %5 %7:_(s32) = G_ZEXT %5
$vgpr0 = COPY %6 $vgpr0 = COPY %6
$vgpr1 = COPY %7 $vgpr1 = COPY %7
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines bb.0:
; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), [[ZERO]] ; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), [[ZERO]]
; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[UNDEFCOUNT]] ; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[UNDEFCOUNT]]
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]] ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
%2(s16) = G_CTLZ %1 %2(s16) = G_CTLZ %1
; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]] ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]] ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]] ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%3(s32) = G_SEXT %2(s16) %3(s32) = G_SEXT %2(s16)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
Show All 30 Lines bb.0:
; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0 ; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0
; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = COPY $r0 ; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = COPY $r0
; LIBCALLS: ADJCALLSTACKUP ; LIBCALLS: ADJCALLSTACKUP
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]] ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
%2(s8) = G_CTLZ_ZERO_UNDEF %1 %2(s8) = G_CTLZ_ZERO_UNDEF %1
; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]] ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]] ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]] ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
%3(s32) = G_SEXT %2(s8) %3(s32) = G_SEXT %2(s8)
$r0 = COPY %3(s32) $r0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines bb.0:
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
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; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32) %3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
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; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer, ; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences. ; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
%0(s32) = COPY $r0 %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1 %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32) %3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
Show All 21 Lines

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

Show First 20 Lines • Show All 1,732 Lines • ▼ Show 20 Lines bb.0:
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: BL{{.*}} &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO2]]
; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the ; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines bb.0:
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN ; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r0 = COPY [[X]]
; SOFT-DAG: $r1 = COPY [[Y]] ; SOFT-DAG: $r1 = COPY [[Y]]
; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: BL{{.*}} &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO2]]
; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the ; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
▲ Show 20 Lines • Show All 846 Lines • ▼ Show 20 Lines bb.0:
; SOFT-DAG: $r0 = COPY [[X0]] ; SOFT-DAG: $r0 = COPY [[X0]]
; SOFT-DAG: $r1 = COPY [[X1]] ; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]] ; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]] ; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; SOFT-AEABI: BL{{.*}} &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO2]]
; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the ; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bb.0:
; SOFT-DAG: $r0 = COPY [[X0]] ; SOFT-DAG: $r0 = COPY [[X0]]
; SOFT-DAG: $r1 = COPY [[X1]] ; SOFT-DAG: $r1 = COPY [[X1]]
; SOFT-DAG: $r2 = COPY [[Y0]] ; SOFT-DAG: $r2 = COPY [[Y0]]
; SOFT-DAG: $r3 = COPY [[Y1]] ; SOFT-DAG: $r3 = COPY [[Y1]]
; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; SOFT-AEABI: BL{{.*}} &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO2]]
; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the ; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32) $r0 = COPY %7(s32)
; CHECK: $r0 = COPY [[REXT]] ; CHECK: $r0 = COPY [[REXT]]
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; Can't use the VFP support for unaligned operations, we need to use 32-bits ; Can't use the VFP support for unaligned operations, we need to use 32-bits
; operations instead. ; operations instead.
; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1) ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1) ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1) ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1)
%0(p0) = COPY $r0 %0(p0) = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8, align 1) %1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
G_STORE %1(s64), %0(p0) :: (store 8, align 1) G_STORE %1(s64), %0(p0) :: (store 8, align 1)
Show All 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $r0 liveins: $r0
; When we don't have VFP support, we need to use 32-bit operations. ; When we don't have VFP support, we need to use 32-bit operations.
; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1) ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1) ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1) ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1) ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1)
%0(p0) = COPY $r0 %0(p0) = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8, align 1) %1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
G_STORE %1(s64), %0(p0) :: (store 8, align 1) G_STORE %1(s64), %0(p0) :: (store 8, align 1)
; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4) ; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4)
; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4) ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4)
; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4) ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4)
; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]] ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4) ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4)
%2(s64) = G_LOAD %0(p0) :: (load 8, align 4) %2(s64) = G_LOAD %0(p0) :: (load 8, align 4)
G_STORE %2(s64), %0(p0) :: (store 8, align 4) G_STORE %2(s64), %0(p0) :: (store 8, align 4)
BX_RET 14, $noreg BX_RET 14, $noreg
Show All 26 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[COPY3]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[COPY3]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
; MIPS32: $v0 = COPY [[ADD3]](s32) ; MIPS32: $v0 = COPY [[ADD3]](s32)
; MIPS32: $v1 = COPY [[ADD1]](s32) ; MIPS32: $v1 = COPY [[ADD1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32) %0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
%4:_(s32) = COPY $a2 %4:_(s32) = COPY $a2
Show All 36 Lines bb.1.entry:
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD1]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD1]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND2]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND2]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD5]](s32), [[LOAD2]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD5]](s32), [[LOAD2]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[AND3]] ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[AND3]]
; MIPS32: $v0 = COPY [[ADD1]](s32) ; MIPS32: $v0 = COPY [[ADD1]](s32)
; MIPS32: $v1 = COPY [[ADD3]](s32) ; MIPS32: $v1 = COPY [[ADD3]](s32)
; MIPS32: $a0 = COPY [[ADD5]](s32) ; MIPS32: $a0 = COPY [[ADD5]](s32)
; MIPS32: $a1 = COPY [[ADD7]](s32) ; MIPS32: $a1 = COPY [[ADD7]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]] ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]]
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]] ; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]] ; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
; MIPS32: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]] ; MIPS32: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]]
; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]] ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]]
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]] ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]] ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]] ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]] ; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32) ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32)
; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]] ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]] ; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]]
; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]] ; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]] ; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32) ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32)
; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]] ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]] ; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]]
; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]] ; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]] ; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
; MIPS32: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]] ; MIPS32: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]]
; MIPS32: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]] ; MIPS32: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]]
; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]] ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]]
; MIPS32: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]] ; MIPS32: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]]
; MIPS32: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]] ; MIPS32: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]]
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; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]] ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]] ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]] ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]] ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]] ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]] ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]] ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
; MIPS32: $v0 = COPY [[ADD6]](s32) ; MIPS32: $v0 = COPY [[ADD6]](s32)
; MIPS32: $v1 = COPY [[ADD8]](s32) ; MIPS32: $v1 = COPY [[ADD8]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir

Show All 28 Lines bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: sdiv_i8 ; MIPS32-LABEL: name: sdiv_i8
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]] ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]] ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]] ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32) %0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32) %1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SDIV %1, %0 %4:_(s8) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s8) %5:_(s32) = G_SEXT %4(s8)
Show All 10 Lines bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: sdiv_i16 ; MIPS32-LABEL: name: sdiv_i16
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]] ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]] ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]] ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32) %0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32) %1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SDIV %1, %0 %4:_(s16) = G_SDIV %1, %0
%5:_(s32) = G_SEXT %4(s16) %5:_(s32) = G_SEXT %4(s16)
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: srem_i8 ; MIPS32-LABEL: name: srem_i8
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]] ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]] ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]] ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32) %0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32) %1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_SREM %1, %0 %4:_(s8) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s8) %5:_(s32) = G_SEXT %4(s8)
Show All 10 Lines bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: srem_i16 ; MIPS32-LABEL: name: srem_i16
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]] ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]] ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]] ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32) %0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32) %1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_SREM %1, %0 %4:_(s16) = G_SREM %1, %0
%5:_(s32) = G_SEXT %4(s16) %5:_(s32) = G_SEXT %4(s16)
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32-LABEL: name: udiv_i8 ; MIPS32-LABEL: name: udiv_i8
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32) %0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32) %1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UDIV %1, %0 %4:_(s8) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s8) %5:_(s32) = G_SEXT %4(s8)
Show All 11 Lines bb.1.entry:
; MIPS32-LABEL: name: udiv_i16 ; MIPS32-LABEL: name: udiv_i16
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32) %0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32) %1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UDIV %1, %0 %4:_(s16) = G_UDIV %1, %0
%5:_(s32) = G_SEXT %4(s16) %5:_(s32) = G_SEXT %4(s16)
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32-LABEL: name: urem_i8 ; MIPS32-LABEL: name: urem_i8
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32) %0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s8) = G_TRUNC %3(s32) %1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_UREM %1, %0 %4:_(s8) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s8) %5:_(s32) = G_SEXT %4(s8)
Show All 11 Lines bb.1.entry:
; MIPS32-LABEL: name: urem_i16 ; MIPS32-LABEL: name: urem_i16
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32) %0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
%1:_(s16) = G_TRUNC %3(s32) %1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_UREM %1, %0 %4:_(s16) = G_UREM %1, %0
%5:_(s32) = G_SEXT %4(s16) %5:_(s32) = G_SEXT %4(s16)
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]]
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]]
; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]] ; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]] ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]]
; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) ; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]]
; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]] ; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32) ; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]] ; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
; MIPS32: $v0 = COPY [[SUB]](s32) ; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: $v1 = COPY [[SUB2]](s32) ; MIPS32: $v1 = COPY [[SUB2]](s32)
; MIPS32: $a0 = COPY [[SUB4]](s32) ; MIPS32: $a0 = COPY [[SUB4]](s32)
; MIPS32: $a1 = COPY [[SUB6]](s32) ; MIPS32: $a1 = COPY [[SUB6]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1 ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0 %2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1 %3:_(s32) = COPY $a1
Show All 21 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; MIPS32-LABEL: add_i64: ; MIPS32-LABEL: add_i64:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 0 ; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: addu $2, $6, $4 ; MIPS32-NEXT: addu $2, $6, $4
; MIPS32-NEXT: ori $3, $zero, 1 ; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: and $1, $1, $3 ; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: addu $1, $2, $1 ; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: sltu $2, $1, $6 ; MIPS32-NEXT: sltu $2, $1, $6
; MIPS32-NEXT: addu $3, $7, $5 ; MIPS32-NEXT: addu $4, $7, $5
; MIPS32-NEXT: ori $4, $zero, 1 ; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: and $2, $2, $4 ; MIPS32-NEXT: addu $3, $4, $2
; MIPS32-NEXT: addu $3, $3, $2
; MIPS32-NEXT: move $2, $1 ; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%add = add i64 %b, %a %add = add i64 %b, %a
ret i64 %add ret i64 %add
} }
Show All 12 Lines
; MIPS32-NEXT: lw $8, 0($8) ; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: ori $9, $zero, 0 ; MIPS32-NEXT: ori $9, $zero, 0
; MIPS32-NEXT: addu $4, $1, $4 ; MIPS32-NEXT: addu $4, $1, $4
; MIPS32-NEXT: ori $10, $zero, 1 ; MIPS32-NEXT: ori $10, $zero, 1
; MIPS32-NEXT: and $9, $9, $10 ; MIPS32-NEXT: and $9, $9, $10
; MIPS32-NEXT: addu $4, $4, $9 ; MIPS32-NEXT: addu $4, $4, $9
; MIPS32-NEXT: sltu $1, $4, $1 ; MIPS32-NEXT: sltu $1, $4, $1
; MIPS32-NEXT: addu $5, $2, $5 ; MIPS32-NEXT: addu $5, $2, $5
; MIPS32-NEXT: ori $9, $zero, 1 ; MIPS32-NEXT: and $1, $1, $10
; MIPS32-NEXT: and $1, $1, $9
; MIPS32-NEXT: addu $1, $5, $1 ; MIPS32-NEXT: addu $1, $5, $1
; MIPS32-NEXT: sltu $2, $1, $2 ; MIPS32-NEXT: sltu $2, $1, $2
; MIPS32-NEXT: addu $5, $3, $6 ; MIPS32-NEXT: addu $5, $3, $6
; MIPS32-NEXT: ori $6, $zero, 1 ; MIPS32-NEXT: and $2, $2, $10
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: addu $2, $5, $2 ; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: sltu $3, $2, $3 ; MIPS32-NEXT: sltu $3, $2, $3
; MIPS32-NEXT: addu $5, $8, $7 ; MIPS32-NEXT: addu $5, $8, $7
; MIPS32-NEXT: ori $6, $zero, 1 ; MIPS32-NEXT: and $3, $3, $10
; MIPS32-NEXT: and $3, $3, $6
; MIPS32-NEXT: addu $5, $5, $3 ; MIPS32-NEXT: addu $5, $5, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $4 ; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: move $3, $1 ; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8 ; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
Show All 24 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: multu $1, $4 ; MIPS32-NEXT: multu $1, $4
; MIPS32-NEXT: mfhi $12 ; MIPS32-NEXT: mfhi $12
; MIPS32-NEXT: addu $10, $10, $11 ; MIPS32-NEXT: addu $10, $10, $11
; MIPS32-NEXT: sltu $11, $10, $11 ; MIPS32-NEXT: sltu $11, $10, $11
; MIPS32-NEXT: ori $13, $zero, 1 ; MIPS32-NEXT: ori $13, $zero, 1
; MIPS32-NEXT: and $11, $11, $13 ; MIPS32-NEXT: and $11, $11, $13
; MIPS32-NEXT: addu $10, $10, $12 ; MIPS32-NEXT: addu $10, $10, $12
; MIPS32-NEXT: sltu $12, $10, $12 ; MIPS32-NEXT: sltu $12, $10, $12
; MIPS32-NEXT: ori $13, $zero, 1
; MIPS32-NEXT: and $12, $12, $13 ; MIPS32-NEXT: and $12, $12, $13
; MIPS32-NEXT: addu $11, $11, $12 ; MIPS32-NEXT: addu $11, $11, $12
; MIPS32-NEXT: mul $12, $3, $4 ; MIPS32-NEXT: mul $12, $3, $4
; MIPS32-NEXT: mul $13, $2, $5 ; MIPS32-NEXT: mul $14, $2, $5
; MIPS32-NEXT: mul $14, $1, $6 ; MIPS32-NEXT: mul $15, $1, $6
; MIPS32-NEXT: multu $2, $4 ; MIPS32-NEXT: multu $2, $4
; MIPS32-NEXT: mfhi $15
; MIPS32-NEXT: multu $1, $5
; MIPS32-NEXT: mfhi $24 ; MIPS32-NEXT: mfhi $24
; MIPS32-NEXT: addu $12, $12, $13 ; MIPS32-NEXT: multu $1, $5
; MIPS32-NEXT: sltu $13, $12, $13 ; MIPS32-NEXT: mfhi $25
; MIPS32-NEXT: ori $25, $zero, 1
; MIPS32-NEXT: and $13, $13, $25
; MIPS32-NEXT: addu $12, $12, $14 ; MIPS32-NEXT: addu $12, $12, $14
; MIPS32-NEXT: sltu $14, $12, $14 ; MIPS32-NEXT: sltu $14, $12, $14
; MIPS32-NEXT: ori $25, $zero, 1 ; MIPS32-NEXT: and $14, $14, $13
; MIPS32-NEXT: and $14, $14, $25
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $15 ; MIPS32-NEXT: addu $12, $12, $15
; MIPS32-NEXT: sltu $14, $12, $15 ; MIPS32-NEXT: sltu $15, $12, $15
; MIPS32-NEXT: ori $15, $zero, 1 ; MIPS32-NEXT: and $15, $15, $13
; MIPS32-NEXT: and $14, $14, $15 ; MIPS32-NEXT: addu $14, $14, $15
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $24 ; MIPS32-NEXT: addu $12, $12, $24
; MIPS32-NEXT: sltu $14, $12, $24 ; MIPS32-NEXT: sltu $15, $12, $24
; MIPS32-NEXT: ori $15, $zero, 1 ; MIPS32-NEXT: and $15, $15, $13
; MIPS32-NEXT: and $14, $14, $15 ; MIPS32-NEXT: addu $14, $14, $15
; MIPS32-NEXT: addu $13, $13, $14 ; MIPS32-NEXT: addu $12, $12, $25
; MIPS32-NEXT: sltu $15, $12, $25
; MIPS32-NEXT: and $15, $15, $13
; MIPS32-NEXT: addu $14, $14, $15
; MIPS32-NEXT: addu $12, $12, $11 ; MIPS32-NEXT: addu $12, $12, $11
; MIPS32-NEXT: sltu $11, $12, $11 ; MIPS32-NEXT: sltu $11, $12, $11
; MIPS32-NEXT: ori $14, $zero, 1 ; MIPS32-NEXT: and $11, $11, $13
; MIPS32-NEXT: and $11, $11, $14 ; MIPS32-NEXT: addu $11, $14, $11
; MIPS32-NEXT: addu $11, $13, $11
; MIPS32-NEXT: mul $8, $8, $4 ; MIPS32-NEXT: mul $8, $8, $4
; MIPS32-NEXT: mul $13, $3, $5 ; MIPS32-NEXT: mul $13, $3, $5
; MIPS32-NEXT: mul $14, $2, $6 ; MIPS32-NEXT: mul $14, $2, $6
; MIPS32-NEXT: mul $7, $1, $7 ; MIPS32-NEXT: mul $7, $1, $7
; MIPS32-NEXT: multu $3, $4 ; MIPS32-NEXT: multu $3, $4
; MIPS32-NEXT: mfhi $3 ; MIPS32-NEXT: mfhi $3
; MIPS32-NEXT: multu $2, $5 ; MIPS32-NEXT: multu $2, $5
; MIPS32-NEXT: mfhi $2 ; MIPS32-NEXT: mfhi $2
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linesentry:
ret i64 %rem ret i64 %rem
} }
; udiv ; udiv
define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) { define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: udiv_i8: ; MIPS32-LABEL: udiv_i8:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 255 ; MIPS32-NEXT: ori $1, $zero, 255
; MIPS32-NEXT: and $1, $5, $1 ; MIPS32-NEXT: and $2, $5, $1
; MIPS32-NEXT: ori $2, $zero, 255 ; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: and $2, $4, $2 ; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: divu $zero, $1, $2 ; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1 ; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24 ; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%div = udiv i8 %b, %a %div = udiv i8 %b, %a
ret i8 %div ret i8 %div
} }
define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) { define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: udiv_i16: ; MIPS32-LABEL: udiv_i16:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 65535 ; MIPS32-NEXT: ori $1, $zero, 65535
; MIPS32-NEXT: and $1, $5, $1 ; MIPS32-NEXT: and $2, $5, $1
; MIPS32-NEXT: ori $2, $zero, 65535 ; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: and $2, $4, $2 ; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: divu $zero, $1, $2 ; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1 ; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 16 ; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16 ; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%div = udiv i16 %b, %a %div = udiv i16 %b, %a
ret i16 %div ret i16 %div
Show All 36 Linesentry:
ret i64 %div ret i64 %div
} }
; urem ; urem
define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: urem_i8: ; MIPS32-LABEL: urem_i8:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 255 ; MIPS32-NEXT: ori $1, $zero, 255
; MIPS32-NEXT: and $1, $5, $1 ; MIPS32-NEXT: and $2, $5, $1
; MIPS32-NEXT: ori $2, $zero, 255 ; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: and $2, $4, $2 ; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: divu $zero, $1, $2 ; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mfhi $1 ; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24 ; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%rem = urem i8 %b, %a %rem = urem i8 %b, %a
ret i8 %rem ret i8 %rem
} }
define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: urem_i16: ; MIPS32-LABEL: urem_i16:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 65535 ; MIPS32-NEXT: ori $1, $zero, 65535
; MIPS32-NEXT: and $1, $5, $1 ; MIPS32-NEXT: and $2, $5, $1
; MIPS32-NEXT: ori $2, $zero, 65535 ; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: and $2, $4, $2 ; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: divu $zero, $1, $2 ; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mfhi $1 ; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 16 ; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16 ; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%rem = urem i16 %b, %a %rem = urem i16 %b, %a
ret i16 %rem ret i16 %rem
Show All 38 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: addiu $3, $sp, 24 ; MIPS32-NEXT: addiu $3, $sp, 24
; MIPS32-NEXT: lw $3, 0($3) ; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 28 ; MIPS32-NEXT: addiu $8, $sp, 28
; MIPS32-NEXT: lw $8, 0($8) ; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: subu $9, $1, $4 ; MIPS32-NEXT: subu $9, $1, $4
; MIPS32-NEXT: sltu $1, $1, $4 ; MIPS32-NEXT: sltu $1, $1, $4
; MIPS32-NEXT: subu $4, $2, $5 ; MIPS32-NEXT: subu $4, $2, $5
; MIPS32-NEXT: ori $10, $zero, 1 ; MIPS32-NEXT: ori $10, $zero, 1
; MIPS32-NEXT: and $10, $1, $10 ; MIPS32-NEXT: and $11, $1, $10
; MIPS32-NEXT: subu $4, $4, $10 ; MIPS32-NEXT: subu $4, $4, $11
; MIPS32-NEXT: xor $10, $2, $5 ; MIPS32-NEXT: xor $11, $2, $5
; MIPS32-NEXT: sltiu $10, $10, 1 ; MIPS32-NEXT: sltiu $11, $11, 1
; MIPS32-NEXT: sltu $2, $2, $5 ; MIPS32-NEXT: sltu $2, $2, $5
; MIPS32-NEXT: ori $5, $zero, 1 ; MIPS32-NEXT: and $5, $11, $10
; MIPS32-NEXT: and $5, $10, $5
; MIPS32-NEXT: movn $2, $1, $5 ; MIPS32-NEXT: movn $2, $1, $5
; MIPS32-NEXT: subu $1, $3, $6 ; MIPS32-NEXT: subu $1, $3, $6
; MIPS32-NEXT: ori $5, $zero, 1 ; MIPS32-NEXT: and $5, $2, $10
; MIPS32-NEXT: and $5, $2, $5
; MIPS32-NEXT: subu $1, $1, $5 ; MIPS32-NEXT: subu $1, $1, $5
; MIPS32-NEXT: xor $5, $3, $6 ; MIPS32-NEXT: xor $5, $3, $6
; MIPS32-NEXT: sltiu $5, $5, 1 ; MIPS32-NEXT: sltiu $5, $5, 1
; MIPS32-NEXT: sltu $3, $3, $6 ; MIPS32-NEXT: sltu $3, $3, $6
; MIPS32-NEXT: ori $6, $zero, 1 ; MIPS32-NEXT: and $5, $5, $10
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: movn $3, $2, $5 ; MIPS32-NEXT: movn $3, $2, $5
; MIPS32-NEXT: subu $2, $8, $7 ; MIPS32-NEXT: subu $2, $8, $7
; MIPS32-NEXT: ori $5, $zero, 1 ; MIPS32-NEXT: and $3, $3, $10
; MIPS32-NEXT: and $3, $3, $5
; MIPS32-NEXT: subu $5, $2, $3 ; MIPS32-NEXT: subu $5, $2, $3
; MIPS32-NEXT: move $2, $9 ; MIPS32-NEXT: move $2, $9
; MIPS32-NEXT: move $3, $4 ; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: move $4, $1 ; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%sub = sub i128 %b, %a %sub = sub i128 %b, %a
ret i128 %sub ret i128 %sub
} }

llvm/trunk/test/CodeGen/X86/GlobalISel/add-ext.ll

Show All 40 Lines
; Use a negative constant (LEA displacement) to verify that's handled correctly. ; Use a negative constant (LEA displacement) to verify that's handled correctly.
define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) { define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) {
; CHECK-LABEL: add_nsw_sext_lsh_add: ; CHECK-LABEL: add_nsw_sext_lsh_add:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addl $-5, %edi ; CHECK-NEXT: addl $-5, %edi
; CHECK-NEXT: movslq %edi, %rax ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $3, %rcx ; CHECK-NEXT: movq $3, %rcx
; CHECK: retq ; CHECK-NEXT: shlq %cl, %rax
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: retq
%add = add nsw i32 %i, -5 %add = add nsw i32 %i, -5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%shl = shl i64 %ext, 3 %shl = shl i64 %ext, 3
%idx = add i64 %x, %shl %idx = add i64 %x, %shl
ret i64 %idx ret i64 %idx
} }
Show All 26 Lines; CHECK-NEXT: retq
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i8, i8* %x, i64 %ext %idx = getelementptr i8, i8* %x, i64 %ext
ret i8* %idx ret i8* %idx
} }
define i16* @gep16(i32 %i, i16* %x) { define i16* @gep16(i32 %i, i16* %x) {
; CHECK-LABEL: gep16: ; CHECK-LABEL: gep16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq $2, %rax
; CHECK-NEXT: addl $-5, %edi ; CHECK-NEXT: addl $-5, %edi
; CHECK-NEXT: movslq %edi, %rcx ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $2, %rcx
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: imulq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rcx), %rax ; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, -5 %add = add nsw i32 %i, -5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i16, i16* %x, i64 %ext %idx = getelementptr i16, i16* %x, i64 %ext
ret i16* %idx ret i16* %idx
} }
define i32* @gep32(i32 %i, i32* %x) { define i32* @gep32(i32 %i, i32* %x) {
; CHECK-LABEL: gep32: ; CHECK-LABEL: gep32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq $4, %rax
; CHECK-NEXT: addl $5, %edi ; CHECK-NEXT: addl $5, %edi
; CHECK-NEXT: movslq %edi, %rcx ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $4, %rcx
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: imulq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rcx), %rax ; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, 5 %add = add nsw i32 %i, 5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i32, i32* %x, i64 %ext %idx = getelementptr i32, i32* %x, i64 %ext
ret i32* %idx ret i32* %idx
} }
define i64* @gep64(i32 %i, i64* %x) { define i64* @gep64(i32 %i, i64* %x) {
; CHECK-LABEL: gep64: ; CHECK-LABEL: gep64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq $8, %rax
; CHECK-NEXT: addl $-5, %edi ; CHECK-NEXT: addl $-5, %edi
; CHECK-NEXT: movslq %edi, %rcx ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $8, %rcx
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: imulq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rcx), %rax ; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, -5 %add = add nsw i32 %i, -5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i64, i64* %x, i64 %ext %idx = getelementptr i64, i64* %x, i64 %ext
ret i64* %idx ret i64* %idx
} }
; LEA can't scale by 16, but the adds can still be combined into an LEA. ; LEA can't scale by 16, but the adds can still be combined into an LEA.
define i128* @gep128(i32 %i, i128* %x) { define i128* @gep128(i32 %i, i128* %x) {
; CHECK-LABEL: gep128: ; CHECK-LABEL: gep128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq $16, %rax
; CHECK-NEXT: addl $5, %edi ; CHECK-NEXT: addl $5, %edi
; CHECK-NEXT: movslq %edi, %rcx ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $16, %rcx
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: imulq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rcx), %rax ; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, 5 %add = add nsw i32 %i, 5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i128, i128* %x, i64 %ext %idx = getelementptr i128, i128* %x, i64 %ext
ret i128* %idx ret i128* %idx
} }
; A bigger win can be achieved when there is more than one use of the ; A bigger win can be achieved when there is more than one use of the
; sign extended value. In this case, we can eliminate sign extension ; sign extended value. In this case, we can eliminate sign extension
; instructions plus use more efficient addressing modes for memory ops. ; instructions plus use more efficient addressing modes for memory ops.
define void @PR20134(i32* %a, i32 %i) { define void @PR20134(i32* %a, i32 %i) {
; CHECK-LABEL: PR20134: ; CHECK-LABEL: PR20134:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK: movq $4, %rax ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: leal 1(%rsi), %ecx ; CHECK-NEXT: leal 1(%rsi), %eax
; CHECK-NEXT: movslq %ecx, %rcx ; CHECK-NEXT: cltq
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: movq $4, %rcx
; CHECK-NEXT: leaq (%rdi,%rcx), %rcx ; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: leaq (%rdi,%rax), %rax
; CHECK-NEXT: leal 2(%rsi), %edx ; CHECK-NEXT: leal 2(%rsi), %edx
; CHECK-NEXT: movslq %edx, %rdx ; CHECK-NEXT: movslq %edx, %rdx
; CHECK-NEXT: imulq %rax, %rdx ; CHECK-NEXT: imulq %rcx, %rdx
; CHECK-NEXT: leaq (%rdi,%rdx), %rdx ; CHECK-NEXT: leaq (%rdi,%rdx), %rdx
; CHECK-NEXT: movl (%rdx), %edx ; CHECK-NEXT: movl (%rdx), %edx
; CHECK-NEXT: addl (%rcx), %edx ; CHECK-NEXT: addl (%rax), %edx
; CHECK-NEXT: movslq %esi, %rcx ; CHECK-NEXT: movslq %esi, %rax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: leaq (%rdi,%rcx), %rax ; CHECK-NEXT: leaq (%rdi,%rax), %rax
; CHECK-NEXT: movl %edx, (%rax) ; CHECK-NEXT: movl %edx, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add1 = add nsw i32 %i, 1 %add1 = add nsw i32 %i, 1
%idx1 = sext i32 %add1 to i64 %idx1 = sext i32 %add1 to i64
%gep1 = getelementptr i32, i32* %a, i64 %idx1 %gep1 = getelementptr i32, i32* %a, i64 %idx1
%load1 = load i32, i32* %gep1, align 4 %load1 = load i32, i32* %gep1, align 4
%add2 = add nsw i32 %i, 2 %add2 = add nsw i32 %i, 2
%idx2 = sext i32 %add2 to i64 %idx2 = sext i32 %add2 to i64
%gep2 = getelementptr i32, i32* %a, i64 %idx2 %gep2 = getelementptr i32, i32* %a, i64 %idx2
%load2 = load i32, i32* %gep2, align 4 %load2 = load i32, i32* %gep2, align 4
%add3 = add i32 %load1, %load2 %add3 = add i32 %load1, %load2
%idx3 = sext i32 %i to i64 %idx3 = sext i32 %i to i64
%gep3 = getelementptr i32, i32* %a, i64 %idx3 %gep3 = getelementptr i32, i32* %a, i64 %idx3
store i32 %add3, i32* %gep3, align 4 store i32 %add3, i32* %gep3, align 4
ret void ret void
} }
; The same as @PR20134 but sign extension is replaced with zero extension ; The same as @PR20134 but sign extension is replaced with zero extension
define void @PR20134_zext(i32* %a, i32 %i) { define void @PR20134_zext(i32* %a, i32 %i) {
; CHECK-LABEL: PR20134_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK: movq $4, %rax ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: leal 1(%rsi), %ecx ; CHECK-NEXT: leal 1(%rsi), %eax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: movq $4, %rcx
; CHECK-NEXT: leaq (%rdi,%rcx), %rcx ; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: leaq (%rdi,%rax), %rax
; CHECK-NEXT: leal 2(%rsi), %edx ; CHECK-NEXT: leal 2(%rsi), %edx
; CHECK-NEXT: imulq %rax, %rdx ; CHECK-NEXT: imulq %rcx, %rdx
; CHECK-NEXT: leaq (%rdi,%rdx), %rdx ; CHECK-NEXT: leaq (%rdi,%rdx), %rdx
; CHECK-NEXT: movl (%rdx), %edx ; CHECK-NEXT: movl (%rdx), %edx
; CHECK-NEXT: addl (%rcx), %edx ; CHECK-NEXT: addl (%rax), %edx
; CHECK-NEXT: imulq %rax, %rsi ; CHECK-NEXT: imulq %rcx, %rsi
; CHECK-NEXT: leaq (%rdi,%rsi), %rax ; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: movl %edx, (%rax) ; CHECK-NEXT: movl %edx, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add1 = add nuw i32 %i, 1 %add1 = add nuw i32 %i, 1
%idx1 = zext i32 %add1 to i64 %idx1 = zext i32 %add1 to i64
%gep1 = getelementptr i32, i32* %a, i64 %idx1 %gep1 = getelementptr i32, i32* %a, i64 %idx1
%load1 = load i32, i32* %gep1, align 4 %load1 = load i32, i32* %gep1, align 4
%add2 = add nuw i32 %i, 2 %add2 = add nuw i32 %i, 2
Show All 10 Lines

llvm/trunk/test/CodeGen/X86/GlobalISel/gep.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64_GISEL ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64_GISEL
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
define i32* @test_gep_i8(i32 *%arr, i8 %ind) { define i32* @test_gep_i8(i32 *%arr, i8 %ind) {
; X64_GISEL-LABEL: test_gep_i8: ; X64_GISEL-LABEL: test_gep_i8:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
; X64_GISEL-NEXT: movq $4, %rax
; X64_GISEL-NEXT: movq $56, %rcx ; X64_GISEL-NEXT: movq $56, %rcx
; X64_GISEL-NEXT: shlq %cl, %rsi ; X64_GISEL-NEXT: shlq %cl, %rsi
; X64_GISEL-NEXT: movq $56, %rcx ; X64_GISEL-NEXT: movq $56, %rcx
; X64_GISEL-NEXT: sarq %cl, %rsi ; X64_GISEL-NEXT: sarq %cl, %rsi
; X64_GISEL-NEXT: imulq %rax, %rsi ; X64_GISEL-NEXT: movq $4, %rax
; X64_GISEL-NEXT: leaq (%rdi,%rsi), %rax ; X64_GISEL-NEXT: imulq %rsi, %rax
; X64_GISEL-NEXT: leaq (%rdi,%rax), %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i8: ; X64-LABEL: test_gep_i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movsbq %sil, %rax ; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq ; X64-NEXT: retq
Show All 15 Lines; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i8 20 %arrayidx = getelementptr i32, i32* %arr, i8 20
ret i32* %arrayidx ret i32* %arrayidx
} }
define i32* @test_gep_i16(i32 *%arr, i16 %ind) { define i32* @test_gep_i16(i32 *%arr, i16 %ind) {
; X64_GISEL-LABEL: test_gep_i16: ; X64_GISEL-LABEL: test_gep_i16:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
; X64_GISEL-NEXT: movq $4, %rax
; X64_GISEL-NEXT: movq $48, %rcx ; X64_GISEL-NEXT: movq $48, %rcx
; X64_GISEL-NEXT: shlq %cl, %rsi ; X64_GISEL-NEXT: shlq %cl, %rsi
; X64_GISEL-NEXT: movq $48, %rcx ; X64_GISEL-NEXT: movq $48, %rcx
; X64_GISEL-NEXT: sarq %cl, %rsi ; X64_GISEL-NEXT: sarq %cl, %rsi
; X64_GISEL-NEXT: imulq %rax, %rsi ; X64_GISEL-NEXT: movq $4, %rax
; X64_GISEL-NEXT: leaq (%rdi,%rsi), %rax ; X64_GISEL-NEXT: imulq %rsi, %rax
; X64_GISEL-NEXT: leaq (%rdi,%rax), %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i16: ; X64-LABEL: test_gep_i16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movswq %si, %rax ; X64-NEXT: movswq %si, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq ; X64-NEXT: retq
Show All 14 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i16 20 %arrayidx = getelementptr i32, i32* %arr, i16 20
ret i32* %arrayidx ret i32* %arrayidx
} }
define i32* @test_gep_i32(i32 *%arr, i32 %ind) { define i32* @test_gep_i32(i32 *%arr, i32 %ind) {
; X64_GISEL-LABEL: test_gep_i32: ; X64_GISEL-LABEL: test_gep_i32:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: movq $4, %rax ; X64_GISEL-NEXT: movslq %esi, %rax
; X64_GISEL-NEXT: movslq %esi, %rcx ; X64_GISEL-NEXT: movq $4, %rcx
; X64_GISEL-NEXT: imulq %rax, %rcx ; X64_GISEL-NEXT: imulq %rax, %rcx
; X64_GISEL-NEXT: leaq (%rdi,%rcx), %rax ; X64_GISEL-NEXT: leaq (%rdi,%rcx), %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i32: ; X64-LABEL: test_gep_i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movslq %esi, %rax ; X64-NEXT: movslq %esi, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
} }
define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) { define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) {
; X32-LABEL: name: test_v8i32_args ; X32-LABEL: name: test_v8i32_args
; X32: bb.1 (%ir-block.0): ; X32: bb.1 (%ir-block.0):
; X32: liveins: $xmm0, $xmm1 ; X32: liveins: $xmm0, $xmm1
; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X32: [[MV:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) ; X32: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>)
; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV]](<8 x s32>) ; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
; X32: $xmm0 = COPY [[UV]](<4 x s32>) ; X32: $xmm0 = COPY [[UV]](<4 x s32>)
; X32: $xmm1 = COPY [[UV1]](<4 x s32>) ; X32: $xmm1 = COPY [[UV1]](<4 x s32>)
; X32: RET 0, implicit $xmm0, implicit $xmm1 ; X32: RET 0, implicit $xmm0, implicit $xmm1
; X64-LABEL: name: test_v8i32_args ; X64-LABEL: name: test_v8i32_args
; X64: bb.1 (%ir-block.0): ; X64: bb.1 (%ir-block.0):
; X64: liveins: $xmm0, $xmm1 ; X64: liveins: $xmm0, $xmm1
; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X64: [[MV:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) ; X64: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>)
; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV]](<8 x s32>) ; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<8 x s32>)
; X64: $xmm0 = COPY [[UV]](<4 x s32>) ; X64: $xmm0 = COPY [[UV]](<4 x s32>)
; X64: $xmm1 = COPY [[UV1]](<4 x s32>) ; X64: $xmm1 = COPY [[UV1]](<4 x s32>)
; X64: RET 0, implicit $xmm0, implicit $xmm1 ; X64: RET 0, implicit $xmm0, implicit $xmm1
ret <8 x i32> %arg1 ret <8 x i32> %arg1
} }
define void @test_void_return() { define void @test_void_return() {
; X32-LABEL: name: test_void_return ; X32-LABEL: name: test_void_return
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Linesdefine <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) {
; X32-LABEL: name: test_split_return_callee ; X32-LABEL: name: test_split_return_callee
; X32: bb.1 (%ir-block.0): ; X32: bb.1 (%ir-block.0):
; X32: liveins: $xmm0, $xmm1, $xmm2 ; X32: liveins: $xmm0, $xmm1, $xmm2
; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X32: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $xmm2 ; X32: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $xmm2
; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; X32: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 16 from %fixed-stack.0, align 1) ; X32: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 16 from %fixed-stack.0, align 1)
; X32: [[MV:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) ; X32: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>)
; X32: [[MV1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<4 x s32>), [[LOAD]](<4 x s32>) ; X32: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<4 x s32>), [[LOAD]](<4 x s32>)
; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV1]](<8 x s32>) ; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<8 x s32>)
; X32: $xmm0 = COPY [[UV]](<4 x s32>) ; X32: $xmm0 = COPY [[UV]](<4 x s32>)
; X32: $xmm1 = COPY [[UV1]](<4 x s32>) ; X32: $xmm1 = COPY [[UV1]](<4 x s32>)
; X32: CALLpcrel32 @split_return_callee, csr_32, implicit $esp, implicit $ssp, implicit $xmm0, implicit $xmm1, implicit-def $xmm0, implicit-def $xmm1 ; X32: CALLpcrel32 @split_return_callee, csr_32, implicit $esp, implicit $ssp, implicit $xmm0, implicit $xmm1, implicit-def $xmm0, implicit-def $xmm1
; X32: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X32: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X32: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X32: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X32: [[MV2:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY3]](<4 x s32>), [[COPY4]](<4 x s32>) ; X32: [[CONCAT_VECTORS2:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY3]](<4 x s32>), [[COPY4]](<4 x s32>)
; X32: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[MV]], [[MV2]] ; X32: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS2]]
; X32: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>) ; X32: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
; X32: $xmm0 = COPY [[UV2]](<4 x s32>) ; X32: $xmm0 = COPY [[UV2]](<4 x s32>)
; X32: $xmm1 = COPY [[UV3]](<4 x s32>) ; X32: $xmm1 = COPY [[UV3]](<4 x s32>)
; X32: RET 0, implicit $xmm0, implicit $xmm1 ; X32: RET 0, implicit $xmm0, implicit $xmm1
; X64-LABEL: name: test_split_return_callee ; X64-LABEL: name: test_split_return_callee
; X64: bb.1 (%ir-block.0): ; X64: bb.1 (%ir-block.0):
; X64: liveins: $xmm0, $xmm1, $xmm2, $xmm3 ; X64: liveins: $xmm0, $xmm1, $xmm2, $xmm3
; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X64: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $xmm2 ; X64: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $xmm2
; X64: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $xmm3 ; X64: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $xmm3
; X64: [[MV:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) ; X64: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>)
; X64: [[MV1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<4 x s32>), [[COPY3]](<4 x s32>) ; X64: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY2]](<4 x s32>), [[COPY3]](<4 x s32>)
; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV1]](<8 x s32>) ; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<8 x s32>)
; X64: $xmm0 = COPY [[UV]](<4 x s32>) ; X64: $xmm0 = COPY [[UV]](<4 x s32>)
; X64: $xmm1 = COPY [[UV1]](<4 x s32>) ; X64: $xmm1 = COPY [[UV1]](<4 x s32>)
; X64: CALL64pcrel32 @split_return_callee, csr_64, implicit $rsp, implicit $ssp, implicit $xmm0, implicit $xmm1, implicit-def $xmm0, implicit-def $xmm1 ; X64: CALL64pcrel32 @split_return_callee, csr_64, implicit $rsp, implicit $ssp, implicit $xmm0, implicit $xmm1, implicit-def $xmm0, implicit-def $xmm1
; X64: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0 ; X64: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $xmm0
; X64: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X64: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1
; X64: [[MV2:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<4 x s32>), [[COPY5]](<4 x s32>) ; X64: [[CONCAT_VECTORS2:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY4]](<4 x s32>), [[COPY5]](<4 x s32>)
; X64: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; X64: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; X64: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[MV]], [[MV2]] ; X64: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS2]]
; X64: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>) ; X64: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
; X64: $xmm0 = COPY [[UV2]](<4 x s32>) ; X64: $xmm0 = COPY [[UV2]](<4 x s32>)
; X64: $xmm1 = COPY [[UV3]](<4 x s32>) ; X64: $xmm1 = COPY [[UV3]](<4 x s32>)
; X64: RET 0, implicit $xmm0, implicit $xmm1 ; X64: RET 0, implicit $xmm0, implicit $xmm1
%call = call <8 x i32> @split_return_callee(<8 x i32> %arg2) %call = call <8 x i32> @split_return_callee(<8 x i32> %arg2)
%r = add <8 x i32> %arg1, %call %r = add <8 x i32> %arg1, %call
ret <8 x i32> %r ret <8 x i32> %r
} }
Show All 32 Linesdefine void @test_abi_exts_call(i8* %addr) {
; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32)
; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8) ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)
; X32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack, align 1) ; X32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack, align 1)
; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp
; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp
; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[COPY2]](s32)
; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8) ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8)
; X32: G_STORE [[SEXT]](s32), [[GEP1]](p0) :: (store 4 into stack, align 1) ; X32: G_STORE [[SEXT]](s32), [[GEP1]](p0) :: (store 4 into stack, align 1)
; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp
; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: [[COPY2:%[0-9]+]]:_(p0) = COPY $esp ; X32: [[COPY3:%[0-9]+]]:_(p0) = COPY $esp
; X32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C2]](s32) ; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY3]], [[COPY4]](s32)
; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8) ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; X32: G_STORE [[ZEXT]](s32), [[GEP2]](p0) :: (store 4 into stack, align 1) ; X32: G_STORE [[ZEXT]](s32), [[GEP2]](p0) :: (store 4 into stack, align 1)
; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X32: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp
; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X32: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp
; X32: RET 0 ; X32: RET 0
; X64-LABEL: name: test_abi_exts_call ; X64-LABEL: name: test_abi_exts_call
; X64: bb.1 (%ir-block.0): ; X64: bb.1 (%ir-block.0):
; X64: liveins: $rdi ; X64: liveins: $rdi
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llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines bb.0:
; X32-LABEL: name: test_memop_s64 ; X32-LABEL: name: test_memop_s64
; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8) ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32) ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4) ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4)
; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8) ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4) ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4)
%0:_(p0) = IMPLICIT_DEF %0:_(p0) = IMPLICIT_DEF
%1:_(s64) = G_LOAD %0 :: (load 8) %1:_(s64) = G_LOAD %0 :: (load 8)
G_STORE %1, %0 :: (store 8) G_STORE %1, %0 :: (store 8)
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL
%struct.f1 = type { float } %struct.f1 = type { float }
%struct.d1 = type { double } %struct.d1 = type { double }
%struct.d2 = type { double, double } %struct.d2 = type { double, double }
%struct.i1 = type { i32 } %struct.i1 = type { i32 }
%struct.i2 = type { i32, i32 } %struct.i2 = type { i32, i32 }
%struct.i3 = type { i32, i32, i32 } %struct.i3 = type { i32, i32, i32 }
%struct.i4 = type { i32, i32, i32, i32 } %struct.i4 = type { i32, i32, i32, i32 }
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define { double, double } @test_return_d2(double %d.coerce0, double %d.coerce1) { define { double, double } @test_return_d2(double %d.coerce0, double %d.coerce1) {
; ALL-LABEL: name: test_return_d2 ; ALL-LABEL: name: test_return_d2
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $xmm0, $xmm1 ; ALL: liveins: $xmm0, $xmm1
; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1 ; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) ; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d
; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1) ; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1)
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C]](s64) ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64)
; ALL: G_STORE [[TRUNC1]](s64), [[GEP]](p0) :: (store 8 into %ir.2) ; ALL: G_STORE [[TRUNC1]](s64), [[GEP]](p0) :: (store 8 into %ir.2)
; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: $rdi = COPY [[FRAME_INDEX]](p0) ; ALL: $rdi = COPY [[FRAME_INDEX]](p0)
; ALL: $rsi = COPY [[FRAME_INDEX1]](p0) ; ALL: $rsi = COPY [[FRAME_INDEX1]](p0)
; ALL: $rdx = COPY [[C1]](s64) ; ALL: $rdx = COPY [[C]](s64)
; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx ; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx
; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5)
; ALL: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C2]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8) ; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8)
; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64) ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64)
; ALL: $xmm0 = COPY [[ANYEXT]](s128) ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
; ALL: [[ANYEXT1:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64) ; ALL: [[ANYEXT1:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64)
; ALL: $xmm1 = COPY [[ANYEXT1]](s128) ; ALL: $xmm1 = COPY [[ANYEXT1]](s128)
; ALL: RET 0, implicit $xmm0, implicit $xmm1 ; ALL: RET 0, implicit $xmm0, implicit $xmm1
entry: entry:
%retval = alloca %struct.d2, align 8 %retval = alloca %struct.d2, align 8
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} }
define { i64, i32 } @test_return_i3(i64 %i.coerce0, i32 %i.coerce1) { define { i64, i32 } @test_return_i3(i64 %i.coerce0, i32 %i.coerce1) {
; ALL-LABEL: name: test_return_i3 ; ALL-LABEL: name: test_return_i3
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $esi, $rdi ; ALL: liveins: $esi, $rdi
; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi ; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.coerce ; ALL: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.coerce
; ALL: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.tmp ; ALL: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.tmp
; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX2]](p0) :: (store 8 into %ir.0, align 4) ; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX2]](p0) :: (store 8 into %ir.0, align 4)
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX2]], [[C]](s64) ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX2]], [[C1]](s64)
; ALL: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.1) ; ALL: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.1)
; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: $rdi = COPY [[FRAME_INDEX1]](p0) ; ALL: $rdi = COPY [[FRAME_INDEX1]](p0)
; ALL: $rsi = COPY [[FRAME_INDEX2]](p0) ; ALL: $rsi = COPY [[FRAME_INDEX2]](p0)
; ALL: $rdx = COPY [[C1]](s64) ; ALL: $rdx = COPY [[C]](s64)
; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx ; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx
; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: $rdi = COPY [[FRAME_INDEX]](p0) ; ALL: $rdi = COPY [[FRAME_INDEX]](p0)
; ALL: $rsi = COPY [[FRAME_INDEX1]](p0) ; ALL: $rsi = COPY [[FRAME_INDEX1]](p0)
; ALL: $rdx = COPY [[C1]](s64) ; ALL: $rdx = COPY [[C]](s64)
; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx ; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx
; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: $rdi = COPY [[FRAME_INDEX3]](p0) ; ALL: $rdi = COPY [[FRAME_INDEX3]](p0)
; ALL: $rsi = COPY [[FRAME_INDEX]](p0) ; ALL: $rsi = COPY [[FRAME_INDEX]](p0)
; ALL: $rdx = COPY [[C1]](s64) ; ALL: $rdx = COPY [[C]](s64)
; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx ; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx
; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 8 from %ir.tmp) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 8 from %ir.tmp)
; ALL: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX3]], [[C1]](s64)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX3]], [[C2]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.tmp + 8, align 8) ; ALL: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.tmp + 8, align 8)
; ALL: $rax = COPY [[LOAD]](s64) ; ALL: $rax = COPY [[LOAD]](s64)
; ALL: $edx = COPY [[LOAD1]](s32) ; ALL: $edx = COPY [[LOAD1]](s32)
; ALL: RET 0, implicit $rax, implicit $edx ; ALL: RET 0, implicit $rax, implicit $edx
entry: entry:
%retval = alloca %struct.i3, align 4 %retval = alloca %struct.i3, align 4
%i = alloca %struct.i3, align 4 %i = alloca %struct.i3, align 4
%coerce = alloca { i64, i32 }, align 4 %coerce = alloca { i64, i32 }, align 4
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} }
define { i64, i64 } @test_return_i4(i64 %i.coerce0, i64 %i.coerce1) { define { i64, i64 } @test_return_i4(i64 %i.coerce0, i64 %i.coerce1) {
; ALL-LABEL: name: test_return_i4 ; ALL-LABEL: name: test_return_i4
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $rdi, $rsi ; ALL: liveins: $rdi, $rsi
; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi ; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi ; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1, align 4) ; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1, align 4)
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C]](s64) ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64)
; ALL: G_STORE [[COPY1]](s64), [[GEP]](p0) :: (store 8 into %ir.2, align 4) ; ALL: G_STORE [[COPY1]](s64), [[GEP]](p0) :: (store 8 into %ir.2, align 4)
; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: $rdi = COPY [[FRAME_INDEX]](p0) ; ALL: $rdi = COPY [[FRAME_INDEX]](p0)
; ALL: $rsi = COPY [[FRAME_INDEX1]](p0) ; ALL: $rsi = COPY [[FRAME_INDEX1]](p0)
; ALL: $rdx = COPY [[C1]](s64) ; ALL: $rdx = COPY [[C]](s64)
; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx ; ALL: CALL64pcrel32 &memcpy, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx
; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp ; ALL: ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5, align 4) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5, align 4)
; ALL: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C2]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8, align 4) ; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8, align 4)
; ALL: $rax = COPY [[LOAD]](s64) ; ALL: $rax = COPY [[LOAD]](s64)
; ALL: $rdx = COPY [[LOAD1]](s64) ; ALL: $rdx = COPY [[LOAD1]](s64)
; ALL: RET 0, implicit $rax, implicit $rdx ; ALL: RET 0, implicit $rax, implicit $rdx
entry: entry:
%retval = alloca %struct.i4, align 4 %retval = alloca %struct.i4, align 4
%i = alloca %struct.i4, align 4 %i = alloca %struct.i4, align 4
%0 = bitcast %struct.i4* %i to { i64, i64 }* %0 = bitcast %struct.i4* %i to { i64, i64 }*
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