diff --git a/llvm/test/TableGen/SchedModelError.td b/llvm/test/TableGen/SchedModelError.td
new file mode 100644
--- /dev/null
+++ b/llvm/test/TableGen/SchedModelError.td
@@ -0,0 +1,18 @@
+// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+
+include "llvm/Target/Target.td"
+
+def TestTarget : Target;
+
+// CHECK: [[FILE]]:[[@LINE+1]]:1: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
+def TestInst : Instruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  bits<8> Inst = 0b00101010;
+}
+
+def TestSchedModel : SchedMachineModel {
+  let CompleteModel = 1;
+}
+
+def TestProcessor : ProcessorModel<"testprocessor", TestSchedModel, []>;
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1935,7 +1935,8 @@
         if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
           PrintError(Inst->TheDef->getLoc(),
                      "No schedule information for instruction '" +
-                         Inst->TheDef->getName() + "'");
+                         Inst->TheDef->getName() + "' in SchedMachineModel '" +
+                     ProcModel.ModelDef->getName() + "'");
           Complete = false;
         }
         continue;