Index: llvm/include/llvm/CodeGen/TargetLowering.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -468,6 +468,12 @@
     return false;
   }
 
+  /// Return true if instruction generated for ICMP_EQ could be folded with
+  /// instruction generated for ICMP_S(G|L)T.
+  virtual bool isICMP_EQFoldedWithICMP_ST() const {
+    return true;
+  }
+
   /// Return true if it is safe to transform an integer-domain bitwise operation
   /// into the equivalent floating-point operation. This should be set to true
   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
Index: llvm/lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -222,6 +222,10 @@
                          cl::init(true),
                          cl::desc("Enable splitting large offset of GEP."));
 
+static cl::opt<bool> EnableICMP_EQToICMP_ST(
+    "cgp-icmp-eq2icmp-st", cl::Hidden, cl::init(false),
+    cl::desc("Enable ICMP_EQ to ICMP_S(L|G)T conversion."));
+
 namespace {
 
 enum ExtType {
@@ -1408,6 +1412,89 @@
   return MadeChange;
 }
 
+/// For pattern like:
+///
+///   DomCond = icmp sgt/slt CmpOp0, CmpOp1 (might not be in DomBB)
+///   ...
+/// DomBB:
+///   ...
+///   br DomCond, TrueBB, CmpBB
+/// CmpBB: (with DomBB being the single predecessor)
+///   ...
+///   Cmp = icmp eq CmpOp0, CmpOp1
+///   ...
+///
+/// It would use two comparison on targets that lowering of icmp sgt/slt is
+/// different from lowering of icmp eq (PowerPC). This function try to convert
+/// 'Cmp = icmp eq CmpOp0, CmpOp1' to ' Cmp = icmp slt/sgt CmpOp0, CmpOp1'.
+/// After that, DomCond and Cmp can use the same comparison so reduce one
+/// comparison.
+///
+/// Return true if any changes are made.
+static bool foldICmpWithDominatingICmp(CmpInst *Cmp,
+                                       const TargetLowering &TLI) {
+  if (!EnableICMP_EQToICMP_ST && TLI.isICMP_EQFoldedWithICMP_ST())
+    return false;
+
+  ICmpInst::Predicate Pred = Cmp->getPredicate();
+  if (Pred != ICmpInst::ICMP_EQ)
+    return false;
+
+  // If icmp eq is not only used by BranchInst or SelectInst, converting it to
+  // icmp slt/sgt would introduce more redundant LLVM IR.
+  for (User *U : Cmp->users()) {
+    if (isa<BranchInst>(U) && cast<BranchInst>(U)->isConditional())
+      continue;
+    if (isa<SelectInst>(U) && cast<SelectInst>(U)->getCondition() == Cmp)
+      continue;
+    return false;
+  }
+
+  // This is a cheap/incomplete check for dominance - just match a single
+  // predecessor with a conditional branch.
+  BasicBlock *CmpBB = Cmp->getParent();
+  BasicBlock *DomBB = CmpBB->getSinglePredecessor();
+  if (!DomBB)
+    return false;
+
+  Value *DomCond;
+  BasicBlock *TrueBB, *FalseBB;
+  if (!match(DomBB->getTerminator(), m_Br(m_Value(DomCond), TrueBB, FalseBB)))
+    return false;
+  if (CmpBB != FalseBB)
+    return false;
+
+  Value *CmpOp0 = Cmp->getOperand(0), *CmpOp1 = Cmp->getOperand(1);
+  ICmpInst::Predicate DomPred;
+  if (!match(DomCond, m_ICmp(DomPred, m_Specific(CmpOp0), m_Specific(CmpOp1))))
+    return false;
+  if (DomPred != ICmpInst::ICMP_SGT && DomPred != ICmpInst::ICMP_SLT)
+    return false;
+
+  ICmpInst::Predicate NewPred =
+      DomPred == ICmpInst::ICMP_SGT ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGT;
+
+  for (User *U : Cmp->users()) {
+    if (auto *BI = dyn_cast<BranchInst>(U)) {
+      assert(BI->isConditional() && "Must be conditional");
+      BI->swapSuccessors();
+      continue;
+    }
+    if (auto *SI = dyn_cast<SelectInst>(U)) {
+      // Swap operands
+      Value *TrueValue = SI->getTrueValue();
+      Value *FalseValue = SI->getFalseValue();
+      SI->setTrueValue(FalseValue);
+      SI->setFalseValue(TrueValue);
+      SI->swapProfMetadata();
+      continue;
+    }
+    llvm_unreachable("Must be a branch or a select");
+  }
+  Cmp->setPredicate(NewPred);
+  return true;
+}
+
 bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, bool &ModifiedDT) {
   if (sinkCmpExpression(Cmp, *TLI))
     return true;
@@ -1418,6 +1505,9 @@
   if (combineToUSubWithOverflow(Cmp, ModifiedDT))
     return true;
 
+  if (foldICmpWithDominatingICmp(Cmp, *TLI))
+    return true;
+
   return false;
 }
 
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -647,6 +647,10 @@
       return true;
     }
 
+    bool isICMP_EQFoldedWithICMP_ST() const override {
+      return false;
+    }
+
     bool hasAndNotCompare(SDValue) const override {
       return true;
     }
Index: llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
@@ -0,0 +1,547 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st < %s | FileCheck %s
+
+; Test cases are generated from:
+; long long NAME(PARAM a, PARAM b) {
+;   if (LHS > RHS)
+;     return b;
+;   if (LHS < RHS)
+;     return a;\
+;   return a * b;
+; }
+; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
+; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+
+define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmn x8, #2 // =2
+; CHECK-NEXT:    b.le .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    tbnz x8, #63, .LBB1_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB1_2: // %if.end
+; CHECK-NEXT:    cmn x8, #1 // =1
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #0 // =0
+; CHECK-NEXT:    b.le .LBB2_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB2_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #1 // =1
+; CHECK-NEXT:    b.le .LBB3_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB3_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl x8, x0, x1
+; CHECK-NEXT:    cmp x8, #2 // =2
+; CHECK-NEXT:    b.le .LBB4_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB4_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn x0, #2 // =2
+; CHECK-NEXT:    b.le .LBB5_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB5_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    tbnz x0, #63, .LBB6_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB6_2: // %if.end
+; CHECK-NEXT:    cmn x0, #1 // =1
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #0 // =0
+; CHECK-NEXT:    b.le .LBB7_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB7_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 0
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #1 // =1
+; CHECK-NEXT:    b.le .LBB8_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB8_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp x0, #2 // =2
+; CHECK-NEXT:    b.le .LBB9_2
+; CHECK-NEXT:  // %bb.1: // %return
+; CHECK-NEXT:    mov x0, x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB9_2: // %if.end
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
+; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmn w8, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmn w8, #1 // =1
+; CHECK-NEXT:    csinc w9, w1, wzr, eq
+; CHECK-NEXT:    mul w9, w9, w0
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csel w8, w1, w9, ge
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #0 // =0
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    lsl w8, w0, w1
+; CHECK-NEXT:    cmp w8, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn w0, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    csel w8, w1, w8, ge
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_0:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #0 // =0
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 0
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #1 // =1
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #2 // =2
+; CHECK-NEXT:    csinc w8, w1, wzr, eq
+; CHECK-NEXT:    mul w8, w8, w0
+; CHECK-NEXT:    csel w8, w1, w8, gt
+; CHECK-NEXT:    sxtw x0, w8
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp sgt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
Index: llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
+++ llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 < %s | FileCheck %s -check-prefix=PPC64LE
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
 
 ; Test cases are generated from:
 ; long long NAME(PARAM a, PARAM b) {
@@ -13,22 +13,21 @@
 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
 
 target datalayout = "e-m:e-i64:64-n32:64"
-target triple = "powerpc64le-unknown-linux-gnu"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, -2
-; PPC64LE-NEXT:    ble 0, .LBB0_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB0_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld 5, 3, 4
+; CHECK-NEXT:    cmpdi 5, -2
+; CHECK-NEXT:    ble 0, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
@@ -45,19 +44,19 @@
 }
 
 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, -1
-; PPC64LE-NEXT:    ble 0, .LBB1_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB1_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld 5, 3, 4
+; CHECK-NEXT:    cmpdi 5, -1
+; CHECK-NEXT:    ble 0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB1_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
@@ -74,19 +73,18 @@
 }
 
 define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld. 5, 3, 4
-; PPC64LE-NEXT:    ble 0, .LBB2_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB2_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 0
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld. 5, 3, 4
+; CHECK-NEXT:    ble 0, .LBB2_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB2_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
@@ -103,20 +101,19 @@
 }
 
 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, 1
-; PPC64LE-NEXT:    ble 0, .LBB3_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB3_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 1
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld 5, 3, 4
+; CHECK-NEXT:    cmpdi 5, 1
+; CHECK-NEXT:    ble 0, .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB3_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
@@ -133,20 +130,19 @@
 }
 
 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_op_b_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    sld 5, 3, 4
-; PPC64LE-NEXT:    cmpdi 5, 2
-; PPC64LE-NEXT:    ble 0, .LBB4_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB4_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 5, 2
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sld 5, 3, 4
+; CHECK-NEXT:    cmpdi 5, 2
+; CHECK-NEXT:    ble 0, .LBB4_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB4_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
@@ -163,18 +159,18 @@
 }
 
 define i64 @ll_a__2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, -2
-; PPC64LE-NEXT:    ble 0, .LBB5_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB5_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi 3, -2
+; CHECK-NEXT:    ble 0, .LBB5_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB5_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
@@ -190,18 +186,18 @@
 }
 
 define i64 @ll_a__1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, -1
-; PPC64LE-NEXT:    ble 0, .LBB6_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB6_2: # %if.end
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi 3, -1
+; CHECK-NEXT:    ble 0, .LBB6_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB6_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
@@ -217,19 +213,18 @@
 }
 
 define i64 @ll_a_0(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 0
-; PPC64LE-NEXT:    ble 0, .LBB7_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB7_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 0
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi 3, 0
+; CHECK-NEXT:    ble 0, .LBB7_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB7_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
@@ -245,19 +240,18 @@
 }
 
 define i64 @ll_a_1(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 1
-; PPC64LE-NEXT:    ble 0, .LBB8_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB8_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 1
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi 3, 1
+; CHECK-NEXT:    ble 0, .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB8_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
@@ -273,19 +267,18 @@
 }
 
 define i64 @ll_a_2(i64 %a, i64 %b) {
-; PPC64LE-LABEL: ll_a_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    cmpdi 3, 2
-; PPC64LE-NEXT:    ble 0, .LBB9_2
-; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    mr 3, 4
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB9_2: # %if.end
-; PPC64LE-NEXT:    cmpldi 3, 2
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    isel 4, 4, 5, 2
-; PPC64LE-NEXT:    mulld 3, 4, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: ll_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpdi 3, 2
+; CHECK-NEXT:    ble 0, .LBB9_2
+; CHECK-NEXT:  # %bb.1: # %return
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB9_2: # %if.end
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    isel 4, 5, 4, 0
+; CHECK-NEXT:    mulld 3, 4, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
@@ -301,16 +294,16 @@
 }
 
 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 6, -2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw 6, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 6, -2
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -2
@@ -329,16 +322,16 @@
 }
 
 define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 6, -1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw 6, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 6, -1
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -1
@@ -357,16 +350,16 @@
 }
 
 define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw. 5, 3, 4
-; PPC64LE-NEXT:    li 6, 1
-; PPC64LE-NEXT:    isel 6, 4, 6, 2
-; PPC64LE-NEXT:    cmpwi 5, 0
-; PPC64LE-NEXT:    mullw 3, 6, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw 6, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 6, 0
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 0
@@ -385,17 +378,16 @@
 }
 
 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 6, 1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 6, 1
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw 6, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 6, 1
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
@@ -414,17 +406,16 @@
 }
 
 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_op_b_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    slw 6, 3, 4
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 6, 2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 6, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    slw 6, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 6, 2
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 2
@@ -443,15 +434,15 @@
 }
 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a__2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 3, -2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 3, -2
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %return, label %if.end
@@ -469,15 +460,15 @@
 }
 
 define i64 @i_a__1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a__1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmpwi 3, -1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    mullw 3, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 3, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 3, -1
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %return, label %if.end
@@ -495,16 +486,15 @@
 }
 
 define i64 @i_a_0(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_0:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 0
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 0
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 3, 0
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %return, label %if.end
@@ -522,16 +512,15 @@
 }
 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_1:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 1
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 1
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 3, 1
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
@@ -549,16 +538,15 @@
 }
 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
-; PPC64LE-LABEL: i_a_2:
-; PPC64LE:       # %bb.0: # %entry
-; PPC64LE-NEXT:    li 5, 1
-; PPC64LE-NEXT:    cmplwi 3, 2
-; PPC64LE-NEXT:    isel 5, 4, 5, 2
-; PPC64LE-NEXT:    cmpwi 0, 3, 2
-; PPC64LE-NEXT:    mullw 5, 5, 3
-; PPC64LE-NEXT:    isel 3, 4, 5, 1
-; PPC64LE-NEXT:    extsw 3, 3
-; PPC64LE-NEXT:    blr
+; CHECK-LABEL: i_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    cmpwi 3, 2
+; CHECK-NEXT:    isel 5, 5, 4, 0
+; CHECK-NEXT:    mullw 3, 5, 3
+; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 2
   br i1 %cmp, label %return, label %if.end
Index: llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll
@@ -0,0 +1,615 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st < %s | FileCheck %s
+
+; Test cases are generated from:
+; long long NAME(PARAM a, PARAM b) {
+;   if (LHS > RHS)
+;     return b;
+;   if (LHS < RHS)
+;     return a;\
+;   return a * b;
+; }
+; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
+; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+
+define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $-2, %rdx
+; CHECK-NEXT:    jg .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB0_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    testq %rdx, %rdx
+; CHECK-NEXT:    js .LBB1_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB1_1: # %if.end
+; CHECK-NEXT:    cmpq $-1, %rdx
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, -1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    testq %rdx, %rdx
+; CHECK-NEXT:    jle .LBB2_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB2_1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovsq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 0
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $1, %rdx
+; CHECK-NEXT:    jg .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testq %rdx, %rdx
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovleq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB3_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 1
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $2, %rdx
+; CHECK-NEXT:    jg .LBB4_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB4_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i64 %a, %b
+  %cmp = icmp sgt i64 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i64 %shl, 2
+  %mul = select i1 %cmp2, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    cmpq $-2, %rdi
+; CHECK-NEXT:    jg .LBB5_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB5_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a__1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    js .LBB6_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB6_1: # %if.end
+; CHECK-NEXT:    cmpq $-1, %rdi
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, -1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_0(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    jle .LBB7_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB7_1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovsq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 0
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_1(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    cmpq $1, %rdi
+; CHECK-NEXT:    jg .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovleq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB8_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 1
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @ll_a_2(i64 %a, i64 %b) {
+; CHECK-LABEL: ll_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    cmpq $2, %rdi
+; CHECK-NEXT:    jg .LBB9_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
+; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB9_2: # %return
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i64 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i64 %a, 2
+  %mul = select i1 %cmp1, i64 %b, i64 1
+  %spec.select = mul nsw i64 %mul, %a
+  ret i64 %spec.select
+
+return:                                           ; preds = %entry
+  ret i64 %b
+}
+
+define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $-2, %eax
+; CHECK-NEXT:    jg .LBB10_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
+; CHECK-NEXT:  .LBB10_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    js .LBB11_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB11_1: # %if.end
+; CHECK-NEXT:    cmpl $-1, %eax
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, -1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jle .LBB12_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB12_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovsl %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 0
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $1, %eax
+; CHECK-NEXT:    jg .LBB13_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovlel %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
+; CHECK-NEXT:  .LBB13_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 1
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_op_b_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, %ecx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    cmpl $2, %eax
+; CHECK-NEXT:    jg .LBB14_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
+; CHECK-NEXT:  .LBB14_2: # %return
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %shl = shl i32 %a, %b
+  %cmp = icmp sgt i32 %shl, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp eq i32 %shl, 2
+  %mul = select i1 %cmp2, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $-2, %edi
+; CHECK-NEXT:    jg .LBB15_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
+; CHECK-NEXT:  .LBB15_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, -2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a__1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a__1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    js .LBB16_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB16_1: # %if.end
+; CHECK-NEXT:    cmpl $-1, %edi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, -1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_0(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    jle .LBB17_1
+; CHECK-NEXT:  # %bb.2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB17_1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovsl %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 0
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_1(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $1, %edi
+; CHECK-NEXT:    jg .LBB18_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovlel %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
+; CHECK-NEXT:  .LBB18_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 1
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}
+
+define i64 @i_a_2(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: i_a_2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $2, %edi
+; CHECK-NEXT:    jg .LBB19_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
+; CHECK-NEXT:  .LBB19_2: # %return
+; CHECK-NEXT:    movslq %esi, %rax
+; CHECK-NEXT:    retq
+entry:
+  %cmp = icmp sgt i32 %a, 2
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp1 = icmp eq i32 %a, 2
+  %mul = select i1 %cmp1, i32 %b, i32 1
+  %spec.select = mul nsw i32 %mul, %a
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
+  %retval.0 = sext i32 %retval.0.in to i64
+  ret i64 %retval.0
+}